hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
kernel/drivers/net/wireless/ath/ath9k/dynack.c
....@@ -20,10 +20,29 @@
2020
2121 #define COMPUTE_TO (5 * HZ)
2222 #define LATEACK_DELAY (10 * HZ)
23
-#define LATEACK_TO 256
24
-#define MAX_DELAY 300
2523 #define EWMA_LEVEL 96
2624 #define EWMA_DIV 128
25
+
26
+/**
27
+ * ath_dynack_get_max_to - set max timeout according to channel width
28
+ * @ah: ath hw
29
+ *
30
+ */
31
+static u32 ath_dynack_get_max_to(struct ath_hw *ah)
32
+{
33
+ const struct ath9k_channel *chan = ah->curchan;
34
+
35
+ if (!chan)
36
+ return 300;
37
+
38
+ if (IS_CHAN_HT40(chan))
39
+ return 300;
40
+ if (IS_CHAN_HALF_RATE(chan))
41
+ return 750;
42
+ if (IS_CHAN_QUARTER_RATE(chan))
43
+ return 1500;
44
+ return 600;
45
+}
2746
2847 /**
2948 * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
....@@ -79,6 +98,24 @@
7998 }
8099
81100 /**
101
+ * ath_dynack_set_timeout - configure timeouts/slottime registers
102
+ * @ah: ath hw
103
+ * @to: timeout value
104
+ *
105
+ */
106
+static void ath_dynack_set_timeout(struct ath_hw *ah, int to)
107
+{
108
+ struct ath_common *common = ath9k_hw_common(ah);
109
+ int slottime = (to - 3) / 2;
110
+
111
+ ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
112
+ to, slottime);
113
+ ath9k_hw_setslottime(ah, slottime);
114
+ ath9k_hw_set_ack_timeout(ah, to);
115
+ ath9k_hw_set_cts_timeout(ah, to);
116
+}
117
+
118
+/**
82119 * ath_dynack_compute_ackto - compute ACK timeout as the maximum STA timeout
83120 * @ah: ath hw
84121 *
....@@ -86,7 +123,6 @@
86123 */
87124 static void ath_dynack_compute_ackto(struct ath_hw *ah)
88125 {
89
- struct ath_common *common = ath9k_hw_common(ah);
90126 struct ath_dynack *da = &ah->dynack;
91127 struct ath_node *an;
92128 int to = 0;
....@@ -96,15 +132,8 @@
96132 to = an->ackto;
97133
98134 if (to && da->ackto != to) {
99
- u32 slottime;
100
-
101
- slottime = (to - 3) / 2;
135
+ ath_dynack_set_timeout(ah, to);
102136 da->ackto = to;
103
- ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
104
- da->ackto, slottime);
105
- ath9k_hw_setslottime(ah, slottime);
106
- ath9k_hw_set_ack_timeout(ah, da->ackto);
107
- ath9k_hw_set_cts_timeout(ah, da->ackto);
108137 }
109138 }
110139
....@@ -116,15 +145,16 @@
116145 */
117146 static void ath_dynack_compute_to(struct ath_hw *ah)
118147 {
119
- u32 ackto, ack_ts;
120
- u8 *dst, *src;
121
- struct ieee80211_sta *sta;
122
- struct ath_node *an;
123
- struct ts_info *st_ts;
124148 struct ath_dynack *da = &ah->dynack;
149
+ u32 ackto, ack_ts, max_to;
150
+ struct ieee80211_sta *sta;
151
+ struct ts_info *st_ts;
152
+ struct ath_node *an;
153
+ u8 *dst, *src;
125154
126155 rcu_read_lock();
127156
157
+ max_to = ath_dynack_get_max_to(ah);
128158 while (da->st_rbf.h_rb != da->st_rbf.t_rb &&
129159 da->ack_rbf.h_rb != da->ack_rbf.t_rb) {
130160 ack_ts = da->ack_rbf.tstamp[da->ack_rbf.h_rb];
....@@ -140,7 +170,7 @@
140170 if (ack_ts > st_ts->tstamp + st_ts->dur) {
141171 ackto = ack_ts - st_ts->tstamp - st_ts->dur;
142172
143
- if (ackto < MAX_DELAY) {
173
+ if (ackto < max_to) {
144174 sta = ieee80211_find_sta_by_ifaddr(ah->hw, dst,
145175 src);
146176 if (sta) {
....@@ -178,11 +208,12 @@
178208 struct ath_tx_status *ts,
179209 struct ieee80211_sta *sta)
180210 {
181
- u8 ridx;
182211 struct ieee80211_hdr *hdr;
183212 struct ath_dynack *da = &ah->dynack;
184213 struct ath_common *common = ath9k_hw_common(ah);
185214 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
215
+ u32 dur = ts->duration;
216
+ u8 ridx;
186217
187218 if (!da->enabled || (info->flags & IEEE80211_TX_CTL_NO_ACK))
188219 return;
....@@ -196,11 +227,10 @@
196227 if (ieee80211_is_assoc_req(hdr->frame_control) ||
197228 ieee80211_is_assoc_resp(hdr->frame_control) ||
198229 ieee80211_is_auth(hdr->frame_control)) {
199
- ath_dbg(common, DYNACK, "late ack\n");
230
+ u32 max_to = ath_dynack_get_max_to(ah);
200231
201
- ath9k_hw_setslottime(ah, (LATEACK_TO - 3) / 2);
202
- ath9k_hw_set_ack_timeout(ah, LATEACK_TO);
203
- ath9k_hw_set_cts_timeout(ah, LATEACK_TO);
232
+ ath_dbg(common, DYNACK, "late ack\n");
233
+ ath_dynack_set_timeout(ah, max_to);
204234 if (sta) {
205235 struct ath_node *an;
206236
....@@ -217,14 +247,13 @@
217247 ridx = ts->ts_rateindex;
218248
219249 da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
220
- da->st_rbf.ts[da->st_rbf.t_rb].dur = ts->duration;
221250 ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1);
222251 ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2);
223252
224253 if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
225
- u32 phy, sifs;
226254 const struct ieee80211_rate *rate;
227255 struct ieee80211_tx_rate *rates = info->status.rates;
256
+ u32 phy;
228257
229258 rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
230259 if (info->band == NL80211_BAND_2GHZ &&
....@@ -233,18 +262,17 @@
233262 else
234263 phy = WLAN_RC_PHY_OFDM;
235264
236
- sifs = ath_dynack_get_sifs(ah, phy);
237
- da->st_rbf.ts[da->st_rbf.t_rb].dur -= sifs;
265
+ dur -= ath_dynack_get_sifs(ah, phy);
238266 }
239
-
240
- ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
241
- hdr->addr1, da->st_rbf.ts[da->st_rbf.t_rb].tstamp,
242
- da->st_rbf.ts[da->st_rbf.t_rb].dur, da->st_rbf.h_rb,
243
- (da->st_rbf.t_rb + 1) % ATH_DYN_BUF);
267
+ da->st_rbf.ts[da->st_rbf.t_rb].dur = dur;
244268
245269 INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
246270 if (da->st_rbf.t_rb == da->st_rbf.h_rb)
247271 INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
272
+
273
+ ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
274
+ hdr->addr1, ts->ts_tstamp, dur, da->st_rbf.h_rb,
275
+ da->st_rbf.t_rb);
248276
249277 ath_dynack_compute_to(ah);
250278
....@@ -272,13 +300,12 @@
272300 spin_lock_bh(&da->qlock);
273301 da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
274302
275
- ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
276
- da->ack_rbf.tstamp[da->ack_rbf.t_rb],
277
- da->ack_rbf.h_rb, (da->ack_rbf.t_rb + 1) % ATH_DYN_BUF);
278
-
279303 INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
280304 if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
281305 INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
306
+
307
+ ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
308
+ ts, da->ack_rbf.h_rb, da->ack_rbf.t_rb);
282309
283310 ath_dynack_compute_to(ah);
284311
....@@ -294,11 +321,9 @@
294321 */
295322 void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an)
296323 {
297
- /* ackto = slottime + sifs + air delay */
298
- u32 ackto = 9 + 16 + 64;
299324 struct ath_dynack *da = &ah->dynack;
300325
301
- an->ackto = ackto;
326
+ an->ackto = da->ackto;
302327
303328 spin_lock_bh(&da->qlock);
304329 list_add_tail(&an->list, &da->nodes);
....@@ -329,22 +354,26 @@
329354 */
330355 void ath_dynack_reset(struct ath_hw *ah)
331356 {
332
- /* ackto = slottime + sifs + air delay */
333
- u32 ackto = 9 + 16 + 64;
334357 struct ath_dynack *da = &ah->dynack;
358
+ struct ath_node *an;
335359
336
- da->lto = jiffies;
337
- da->ackto = ackto;
360
+ spin_lock_bh(&da->qlock);
361
+
362
+ da->lto = jiffies + COMPUTE_TO;
338363
339364 da->st_rbf.t_rb = 0;
340365 da->st_rbf.h_rb = 0;
341366 da->ack_rbf.t_rb = 0;
342367 da->ack_rbf.h_rb = 0;
343368
369
+ da->ackto = ath_dynack_get_max_to(ah);
370
+ list_for_each_entry(an, &da->nodes, list)
371
+ an->ackto = da->ackto;
372
+
344373 /* init acktimeout */
345
- ath9k_hw_setslottime(ah, (ackto - 3) / 2);
346
- ath9k_hw_set_ack_timeout(ah, ackto);
347
- ath9k_hw_set_cts_timeout(ah, ackto);
374
+ ath_dynack_set_timeout(ah, da->ackto);
375
+
376
+ spin_unlock_bh(&da->qlock);
348377 }
349378 EXPORT_SYMBOL(ath_dynack_reset);
350379
....@@ -361,6 +390,8 @@
361390
362391 spin_lock_init(&da->qlock);
363392 INIT_LIST_HEAD(&da->nodes);
393
+ /* ackto = slottime + sifs + air delay */
394
+ da->ackto = 9 + 16 + 64;
364395
365396 ah->hw->wiphy->features |= NL80211_FEATURE_ACKTO_ESTIMATION;
366397 }