修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/net/dsa/b53/b53_srab.c
..
..
@@ -19,11 +19,13 @@
19
19
 #include <linux/kernel.h>
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 #include <linux/module.h>
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 #include <linux/delay.h>
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+#include <linux/interrupt.h>
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 #include <linux/platform_device.h>
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 #include <linux/platform_data/b53.h>
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 #include <linux/of.h>
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26
 
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 #include "b53_priv.h"
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+#include "b53_serdes.h"
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29
 
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 /* command and status register of the SRAB */
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 #define B53_SRAB_CMDSTAT		0x2c
..
..
@@ -47,6 +49,7 @@
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49
 
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 /* command and status register of the SRAB */
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 #define B53_SRAB_CTRLS			0x40
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+#define  B53_SRAB_CTRLS_HOST_INTR	BIT(1)
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53
 #define  B53_SRAB_CTRLS_RCAREQ		BIT(3)
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 #define  B53_SRAB_CTRLS_RCAGNT		BIT(4)
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 #define  B53_SRAB_CTRLS_SW_INIT_DONE	BIT(6)
..
..
@@ -60,8 +63,29 @@
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 #define  B53_SRAB_P7_SLEEP_TIMER	BIT(11)
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 #define  B53_SRAB_IMP0_SLEEP_TIMER	BIT(12)
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65
 
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+/* Port mux configuration registers */
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+#define B53_MUX_CONFIG_P5		0x00
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+#define  MUX_CONFIG_SGMII		0
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+#define  MUX_CONFIG_MII_LITE		1
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+#define  MUX_CONFIG_RGMII		2
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+#define  MUX_CONFIG_GMII		3
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+#define  MUX_CONFIG_GPHY		4
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+#define  MUX_CONFIG_INTERNAL		5
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+#define  MUX_CONFIG_MASK		0x7
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+#define B53_MUX_CONFIG_P4		0x04
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+
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+struct b53_srab_port_priv {
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+	int irq;
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+	bool irq_enabled;
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+	struct b53_device *dev;
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+	unsigned int num;
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+	phy_interface_t mode;
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+};
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+
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 struct b53_srab_priv {
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 	void __iomem *regs;
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+	void __iomem *mux_config;
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+	struct b53_srab_port_priv port_intrs[B53_N_PORTS];
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 };
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90
 
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 static int b53_srab_request_grant(struct b53_device *dev)
..
..
@@ -344,6 +368,81 @@
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 	return ret;
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 }
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370
 
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+static irqreturn_t b53_srab_port_thread(int irq, void *dev_id)
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+{
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+	struct b53_srab_port_priv *port = dev_id;
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+	struct b53_device *dev = port->dev;
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+
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+	if (port->mode == PHY_INTERFACE_MODE_SGMII)
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+		b53_port_event(dev->ds, port->num);
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+
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+	return IRQ_HANDLED;
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+}
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+
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+static irqreturn_t b53_srab_port_isr(int irq, void *dev_id)
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+{
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+	struct b53_srab_port_priv *port = dev_id;
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+	struct b53_device *dev = port->dev;
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+	struct b53_srab_priv *priv = dev->priv;
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+
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+	/* Acknowledge the interrupt */
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+	writel(BIT(port->num), priv->regs + B53_SRAB_INTR);
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+
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+	return IRQ_WAKE_THREAD;
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+}
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+
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+#if IS_ENABLED(CONFIG_B53_SERDES)
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+static u8 b53_srab_serdes_map_lane(struct b53_device *dev, int port)
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+{
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+	struct b53_srab_priv *priv = dev->priv;
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+	struct b53_srab_port_priv *p = &priv->port_intrs[port];
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+
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+	if (p->mode != PHY_INTERFACE_MODE_SGMII)
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+		return B53_INVALID_LANE;
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+
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+	switch (port) {
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+	case 5:
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+		return 0;
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+	case 4:
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+		return 1;
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+	default:
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+		return B53_INVALID_LANE;
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+	}
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+}
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+#endif
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+
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+static int b53_srab_irq_enable(struct b53_device *dev, int port)
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+{
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+	struct b53_srab_priv *priv = dev->priv;
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+	struct b53_srab_port_priv *p = &priv->port_intrs[port];
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+	int ret = 0;
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+
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+	/* Interrupt is optional and was not specified, do not make
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+	 * this fatal
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+	 */
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+	if (p->irq == -ENXIO)
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+		return ret;
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+
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+	ret = request_threaded_irq(p->irq, b53_srab_port_isr,
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+				   b53_srab_port_thread, 0,
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+				   dev_name(dev->dev), p);
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+	if (!ret)
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+		p->irq_enabled = true;
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+
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+	return ret;
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+}
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+
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+static void b53_srab_irq_disable(struct b53_device *dev, int port)
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+{
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+	struct b53_srab_priv *priv = dev->priv;
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+	struct b53_srab_port_priv *p = &priv->port_intrs[port];
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+
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+	if (p->irq_enabled) {
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+		free_irq(p->irq, p);
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+		p->irq_enabled = false;
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+	}
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+}
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+
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 static const struct b53_io_ops b53_srab_ops = {
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 	.read8 = b53_srab_read8,
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 	.read16 = b53_srab_read16,
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@@ -355,6 +454,16 @@
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 	.write32 = b53_srab_write32,
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 	.write48 = b53_srab_write48,
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 	.write64 = b53_srab_write64,
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+	.irq_enable = b53_srab_irq_enable,
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+	.irq_disable = b53_srab_irq_disable,
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+#if IS_ENABLED(CONFIG_B53_SERDES)
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+	.serdes_map_lane = b53_srab_serdes_map_lane,
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+	.serdes_link_state = b53_serdes_link_state,
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+	.serdes_config = b53_serdes_config,
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+	.serdes_an_restart = b53_serdes_an_restart,
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+	.serdes_link_set = b53_serdes_link_set,
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+	.serdes_phylink_validate = b53_serdes_phylink_validate,
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+#endif
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 };
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468
 
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 static const struct of_device_id b53_srab_of_match[] = {
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@@ -379,6 +488,102 @@
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 };
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489
 MODULE_DEVICE_TABLE(of, b53_srab_of_match);
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490
 
491
+static void b53_srab_intr_set(struct b53_srab_priv *priv, bool set)
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+{
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+	u32 reg;
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+
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+	reg = readl(priv->regs + B53_SRAB_CTRLS);
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+	if (set)
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+		reg |= B53_SRAB_CTRLS_HOST_INTR;
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+	else
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+		reg &= ~B53_SRAB_CTRLS_HOST_INTR;
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+	writel(reg, priv->regs + B53_SRAB_CTRLS);
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+}
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+
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+static void b53_srab_prepare_irq(struct platform_device *pdev)
504
+{
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+	struct b53_device *dev = platform_get_drvdata(pdev);
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+	struct b53_srab_priv *priv = dev->priv;
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+	struct b53_srab_port_priv *port;
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+	unsigned int i;
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+	char *name;
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+
511
+	/* Clear all pending interrupts */
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+	writel(0xffffffff, priv->regs + B53_SRAB_INTR);
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+
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+	for (i = 0; i < B53_N_PORTS; i++) {
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+		port = &priv->port_intrs[i];
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+
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+		/* There is no port 6 */
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+		if (i == 6)
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+			continue;
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+
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+		name = kasprintf(GFP_KERNEL, "link_state_p%d", i);
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+		if (!name)
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+			return;
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+
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+		port->num = i;
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+		port->dev = dev;
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+		port->irq = platform_get_irq_byname_optional(pdev, name);
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+		kfree(name);
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+	}
530
+
531
+	b53_srab_intr_set(priv, true);
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+}
533
+
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+static void b53_srab_mux_init(struct platform_device *pdev)
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+{
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+	struct b53_device *dev = platform_get_drvdata(pdev);
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+	struct b53_srab_priv *priv = dev->priv;
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+	struct b53_srab_port_priv *p;
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+	unsigned int port;
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+	u32 reg, off = 0;
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+	int ret;
542
+
543
+	if (dev->pdata && dev->pdata->chip_id != BCM58XX_DEVICE_ID)
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+		return;
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+
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+	priv->mux_config = devm_platform_ioremap_resource(pdev, 1);
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+	if (IS_ERR(priv->mux_config))
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+		return;
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+
550
+	/* Obtain the port mux configuration so we know which lanes
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+	 * actually map to SerDes lanes
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+	 */
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+	for (port = 5; port > 3; port--, off += 4) {
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+		p = &priv->port_intrs[port];
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+
556
+		reg = readl(priv->mux_config + B53_MUX_CONFIG_P5 + off);
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+		switch (reg & MUX_CONFIG_MASK) {
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+		case MUX_CONFIG_SGMII:
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+			p->mode = PHY_INTERFACE_MODE_SGMII;
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+			ret = b53_serdes_init(dev, port);
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+			if (ret)
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+				continue;
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+			break;
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+		case MUX_CONFIG_MII_LITE:
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+			p->mode = PHY_INTERFACE_MODE_MII;
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+			break;
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+		case MUX_CONFIG_GMII:
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+			p->mode = PHY_INTERFACE_MODE_GMII;
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+			break;
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+		case MUX_CONFIG_RGMII:
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+			p->mode = PHY_INTERFACE_MODE_RGMII;
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+			break;
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+		case MUX_CONFIG_INTERNAL:
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+			p->mode = PHY_INTERFACE_MODE_INTERNAL;
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+			break;
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+		default:
577
+			p->mode = PHY_INTERFACE_MODE_NA;
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+			break;
579
+		}
580
+
581
+		if (p->mode != PHY_INTERFACE_MODE_NA)
582
+			dev_info(&pdev->dev, "Port %d mode: %s\n",
583
+				 port, phy_modes(p->mode));
584
+	}
585
+}
586
+
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 static int b53_srab_probe(struct platform_device *pdev)
383
588
 {
384
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 	struct b53_platform_data *pdata = pdev->dev.platform_data;
..
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@@ -386,7 +591,6 @@
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 	const struct of_device_id *of_id = NULL;
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 	struct b53_srab_priv *priv;
388
593
 	struct b53_device *dev;
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-	struct resource *r;
390
594
 
391
595
 	if (dn)
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 		of_id = of_match_node(b53_srab_of_match, dn);
..
..
@@ -403,10 +607,9 @@
403
607
 	if (!priv)
404
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 		return -ENOMEM;
405
609
 
406
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407
-	priv->regs = devm_ioremap_resource(&pdev->dev, r);
610
+	priv->regs = devm_platform_ioremap_resource(pdev, 0);
408
611
 	if (IS_ERR(priv->regs))
409
-		return -ENOMEM;
612
+		return PTR_ERR(priv->regs);
410
613
 
411
614
 	dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, priv);
412
615
 	if (!dev)
..
..
@@ -417,13 +620,18 @@
417
620
 
418
621
 	platform_set_drvdata(pdev, dev);
419
622
 
623
+	b53_srab_prepare_irq(pdev);
624
+	b53_srab_mux_init(pdev);
625
+
420
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 	return b53_switch_register(dev);
421
627
 }
422
628
 
423
629
 static int b53_srab_remove(struct platform_device *pdev)
424
630
 {
425
631
 	struct b53_device *dev = platform_get_drvdata(pdev);
632
+	struct b53_srab_priv *priv = dev->priv;
426
633
 
634
+	b53_srab_intr_set(priv, false);
427
635
 	if (dev)
428
636
 		b53_switch_remove(dev);
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