.. | .. |
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375 | 375 | struct xiic_i2c *i2c = dev_id; |
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376 | 376 | u32 pend, isr, ier; |
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377 | 377 | u32 clr = 0; |
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| 378 | + int xfer_more = 0; |
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| 379 | + int wakeup_req = 0; |
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| 380 | + int wakeup_code = 0; |
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378 | 381 | |
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379 | 382 | /* Get the interrupt Status from the IPIF. There is no clearing of |
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380 | 383 | * interrupts in the IPIF. Interrupts must be cleared at the source. |
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.. | .. |
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411 | 414 | */ |
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412 | 415 | xiic_reinit(i2c); |
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413 | 416 | |
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414 | | - if (i2c->rx_msg) |
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415 | | - xiic_wakeup(i2c, STATE_ERROR); |
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416 | | - if (i2c->tx_msg) |
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417 | | - xiic_wakeup(i2c, STATE_ERROR); |
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| 417 | + if (i2c->rx_msg) { |
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| 418 | + wakeup_req = 1; |
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| 419 | + wakeup_code = STATE_ERROR; |
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| 420 | + } |
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| 421 | + if (i2c->tx_msg) { |
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| 422 | + wakeup_req = 1; |
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| 423 | + wakeup_code = STATE_ERROR; |
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| 424 | + } |
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| 425 | + /* don't try to handle other events */ |
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| 426 | + goto out; |
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418 | 427 | } |
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419 | 428 | if (pend & XIIC_INTR_RX_FULL_MASK) { |
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420 | 429 | /* Receive register/FIFO is full */ |
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.. | .. |
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448 | 457 | i2c->tx_msg++; |
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449 | 458 | dev_dbg(i2c->adap.dev.parent, |
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450 | 459 | "%s will start next...\n", __func__); |
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451 | | - |
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452 | | - __xiic_start_xfer(i2c); |
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| 460 | + xfer_more = 1; |
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453 | 461 | } |
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454 | 462 | } |
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455 | 463 | } |
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.. | .. |
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463 | 471 | if (!i2c->tx_msg) |
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464 | 472 | goto out; |
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465 | 473 | |
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466 | | - if ((i2c->nmsgs == 1) && !i2c->rx_msg && |
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467 | | - xiic_tx_space(i2c) == 0) |
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468 | | - xiic_wakeup(i2c, STATE_DONE); |
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| 474 | + wakeup_req = 1; |
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| 475 | + |
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| 476 | + if (i2c->nmsgs == 1 && !i2c->rx_msg && |
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| 477 | + xiic_tx_space(i2c) == 0) |
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| 478 | + wakeup_code = STATE_DONE; |
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469 | 479 | else |
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470 | | - xiic_wakeup(i2c, STATE_ERROR); |
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| 480 | + wakeup_code = STATE_ERROR; |
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471 | 481 | } |
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472 | 482 | if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { |
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473 | 483 | /* Transmit register/FIFO is empty or ½ empty */ |
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.. | .. |
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491 | 501 | if (i2c->nmsgs > 1) { |
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492 | 502 | i2c->nmsgs--; |
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493 | 503 | i2c->tx_msg++; |
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494 | | - __xiic_start_xfer(i2c); |
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| 504 | + xfer_more = 1; |
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495 | 505 | } else { |
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496 | 506 | xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); |
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497 | 507 | |
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.. | .. |
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509 | 519 | dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); |
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510 | 520 | |
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511 | 521 | xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); |
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| 522 | + if (xfer_more) |
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| 523 | + __xiic_start_xfer(i2c); |
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| 524 | + if (wakeup_req) |
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| 525 | + xiic_wakeup(i2c, wakeup_code); |
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| 526 | + |
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| 527 | + WARN_ON(xfer_more && wakeup_req); |
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| 528 | + |
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512 | 529 | mutex_unlock(&i2c->lock); |
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513 | 530 | return IRQ_HANDLED; |
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514 | 531 | } |
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