hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
kernel/drivers/i2c/busses/i2c-sh_mobile.c
....@@ -2,8 +2,7 @@
22 /*
33 * SuperH Mobile I2C Controller
44 *
5
- * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
6
- *
5
+ * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
76 * Copyright (C) 2008 Magnus Damm
87 *
98 * Portions of the code based on out-of-tree driver i2c-sh7343.c
....@@ -130,6 +129,7 @@
130129 int sr;
131130 bool send_stop;
132131 bool stop_after_dma;
132
+ bool atomic_xfer;
133133
134134 struct resource *res;
135135 struct dma_chan *dma_tx;
....@@ -145,9 +145,6 @@
145145 };
146146
147147 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
148
-
149
-#define STANDARD_MODE 100000
150
-#define FAST_MODE 400000
151148
152149 /* Register offsets */
153150 #define ICDR 0x00
....@@ -271,11 +268,11 @@
271268
272269 i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
273270
274
- if (pd->bus_speed == STANDARD_MODE) {
271
+ if (pd->bus_speed == I2C_MAX_STANDARD_MODE_FREQ) {
275272 tLOW = 47; /* tLOW = 4.7 us */
276273 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
277274 tf = 3; /* tf = 0.3 us */
278
- } else if (pd->bus_speed == FAST_MODE) {
275
+ } else if (pd->bus_speed == I2C_MAX_FAST_MODE_FREQ) {
279276 tLOW = 13; /* tLOW = 1.3 us */
280277 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
281278 tf = 3; /* tf = 0.3 us */
....@@ -303,13 +300,12 @@
303300 return sh_mobile_i2c_check_timing(pd);
304301 }
305302
306
-static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
307
- enum sh_mobile_i2c_op op, unsigned char data)
303
+static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
308304 {
309305 unsigned char ret = 0;
310306 unsigned long flags;
311307
312
- dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
308
+ dev_dbg(pd->dev, "op %d\n", op);
313309
314310 spin_lock_irqsave(&pd->lock, flags);
315311
....@@ -317,12 +313,12 @@
317313 case OP_START: /* issue start and trigger DTE interrupt */
318314 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
319315 break;
320
- case OP_TX_FIRST: /* disable DTE interrupt and write data */
316
+ case OP_TX_FIRST: /* disable DTE interrupt and write client address */
321317 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
322
- iic_wr(pd, ICDR, data);
318
+ iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
323319 break;
324320 case OP_TX: /* write data */
325
- iic_wr(pd, ICDR, data);
321
+ iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
326322 break;
327323 case OP_TX_STOP: /* issue a stop (or rep_start) */
328324 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
....@@ -335,13 +331,15 @@
335331 ret = iic_rd(pd, ICDR);
336332 break;
337333 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
338
- iic_wr(pd, ICIC,
339
- ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
334
+ if (!pd->atomic_xfer)
335
+ iic_wr(pd, ICIC,
336
+ ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
340337 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
341338 break;
342339 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
343
- iic_wr(pd, ICIC,
344
- ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
340
+ if (!pd->atomic_xfer)
341
+ iic_wr(pd, ICIC,
342
+ ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
345343 ret = iic_rd(pd, ICDR);
346344 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
347345 break;
....@@ -353,34 +351,17 @@
353351 return ret;
354352 }
355353
356
-static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
357
-{
358
- return pd->pos == -1;
359
-}
360
-
361
-static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
362
- unsigned char *buf)
363
-{
364
- switch (pd->pos) {
365
- case -1:
366
- *buf = i2c_8bit_addr_from_msg(pd->msg);
367
- break;
368
- default:
369
- *buf = pd->msg->buf[pd->pos];
370
- }
371
-}
372
-
373354 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
374355 {
375
- unsigned char data;
376
-
377356 if (pd->pos == pd->msg->len) {
378
- i2c_op(pd, OP_TX_STOP, 0);
357
+ i2c_op(pd, OP_TX_STOP);
379358 return 1;
380359 }
381360
382
- sh_mobile_i2c_get_data(pd, &data);
383
- i2c_op(pd, sh_mobile_i2c_is_first_byte(pd) ? OP_TX_FIRST : OP_TX, data);
361
+ if (pd->pos == -1)
362
+ i2c_op(pd, OP_TX_FIRST);
363
+ else
364
+ i2c_op(pd, OP_TX);
384365
385366 pd->pos++;
386367 return 0;
....@@ -388,48 +369,32 @@
388369
389370 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
390371 {
391
- unsigned char data;
392372 int real_pos;
393373
394
- do {
395
- if (pd->pos <= -1) {
396
- sh_mobile_i2c_get_data(pd, &data);
374
+ /* switch from TX (address) to RX (data) adds two interrupts */
375
+ real_pos = pd->pos - 2;
397376
398
- if (sh_mobile_i2c_is_first_byte(pd))
399
- i2c_op(pd, OP_TX_FIRST, data);
400
- else
401
- i2c_op(pd, OP_TX, data);
402
- break;
377
+ if (pd->pos == -1) {
378
+ i2c_op(pd, OP_TX_FIRST);
379
+ } else if (pd->pos == 0) {
380
+ i2c_op(pd, OP_TX_TO_RX);
381
+ } else if (pd->pos == pd->msg->len) {
382
+ if (pd->stop_after_dma) {
383
+ /* Simulate PIO end condition after DMA transfer */
384
+ i2c_op(pd, OP_RX_STOP);
385
+ pd->pos++;
386
+ goto done;
403387 }
404388
405
- if (pd->pos == 0) {
406
- i2c_op(pd, OP_TX_TO_RX, 0);
407
- break;
408
- }
389
+ if (real_pos < 0)
390
+ i2c_op(pd, OP_RX_STOP);
391
+ else
392
+ pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA);
393
+ } else if (real_pos >= 0) {
394
+ pd->msg->buf[real_pos] = i2c_op(pd, OP_RX);
395
+ }
409396
410
- real_pos = pd->pos - 2;
411
-
412
- if (pd->pos == pd->msg->len) {
413
- if (pd->stop_after_dma) {
414
- /* Simulate PIO end condition after DMA transfer */
415
- i2c_op(pd, OP_RX_STOP, 0);
416
- pd->pos++;
417
- break;
418
- }
419
-
420
- if (real_pos < 0) {
421
- i2c_op(pd, OP_RX_STOP, 0);
422
- break;
423
- }
424
- data = i2c_op(pd, OP_RX_STOP_DATA, 0);
425
- } else if (real_pos >= 0) {
426
- data = i2c_op(pd, OP_RX, 0);
427
- }
428
-
429
- if (real_pos >= 0)
430
- pd->msg->buf[real_pos] = data;
431
- } while (0);
432
-
397
+ done:
433398 pd->pos++;
434399 return pd->pos == (pd->msg->len + 2);
435400 }
....@@ -467,7 +432,8 @@
467432
468433 if (wakeup) {
469434 pd->sr |= SW_DONE;
470
- wake_up(&pd->wait);
435
+ if (!pd->atomic_xfer)
436
+ wake_up(&pd->wait);
471437 }
472438
473439 /* defeat write posting to avoid spurious WAIT interrupts */
....@@ -518,7 +484,7 @@
518484 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
519485 int ret;
520486
521
- chan = dma_request_slave_channel_reason(dev, chan_name);
487
+ chan = dma_request_chan(dev, chan_name);
522488 if (IS_ERR(chan)) {
523489 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
524490 PTR_ERR(chan));
....@@ -619,6 +585,9 @@
619585 pd->pos = -1;
620586 pd->sr = 0;
621587
588
+ if (pd->atomic_xfer)
589
+ return;
590
+
622591 pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
623592 if (pd->dma_buf)
624593 sh_mobile_i2c_xfer_dma(pd);
....@@ -675,15 +644,13 @@
675644 return i ? 0 : -ETIMEDOUT;
676645 }
677646
678
-static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
679
- struct i2c_msg *msgs,
680
- int num)
647
+static int sh_mobile_xfer(struct sh_mobile_i2c_data *pd,
648
+ struct i2c_msg *msgs, int num)
681649 {
682
- struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
683650 struct i2c_msg *msg;
684651 int err = 0;
685652 int i;
686
- long timeout;
653
+ long time_left;
687654
688655 /* Wake up device and enable clock */
689656 pm_runtime_get_sync(pd->dev);
....@@ -698,17 +665,37 @@
698665 start_ch(pd, msg, do_start);
699666
700667 if (do_start)
701
- i2c_op(pd, OP_START, 0);
668
+ i2c_op(pd, OP_START);
702669
703
- /* The interrupt handler takes care of the rest... */
704
- timeout = wait_event_timeout(pd->wait,
705
- pd->sr & (ICSR_TACK | SW_DONE),
706
- adapter->timeout);
670
+ if (pd->atomic_xfer) {
671
+ unsigned long j = jiffies + pd->adap.timeout;
707672
708
- /* 'stop_after_dma' tells if DMA transfer was complete */
709
- i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma);
673
+ time_left = time_before_eq(jiffies, j);
674
+ while (time_left &&
675
+ !(pd->sr & (ICSR_TACK | SW_DONE))) {
676
+ unsigned char sr = iic_rd(pd, ICSR);
710677
711
- if (!timeout) {
678
+ if (sr & (ICSR_AL | ICSR_TACK |
679
+ ICSR_WAIT | ICSR_DTE)) {
680
+ sh_mobile_i2c_isr(0, pd);
681
+ udelay(150);
682
+ } else {
683
+ cpu_relax();
684
+ }
685
+ time_left = time_before_eq(jiffies, j);
686
+ }
687
+ } else {
688
+ /* The interrupt handler takes care of the rest... */
689
+ time_left = wait_event_timeout(pd->wait,
690
+ pd->sr & (ICSR_TACK | SW_DONE),
691
+ pd->adap.timeout);
692
+
693
+ /* 'stop_after_dma' tells if DMA xfer was complete */
694
+ i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg,
695
+ pd->stop_after_dma);
696
+ }
697
+
698
+ if (!time_left) {
712699 dev_err(pd->dev, "Transfer request timed out\n");
713700 if (pd->dma_direction != DMA_NONE)
714701 sh_mobile_i2c_cleanup_dma(pd);
....@@ -734,14 +721,35 @@
734721 return err ?: num;
735722 }
736723
724
+static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
725
+ struct i2c_msg *msgs,
726
+ int num)
727
+{
728
+ struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
729
+
730
+ pd->atomic_xfer = false;
731
+ return sh_mobile_xfer(pd, msgs, num);
732
+}
733
+
734
+static int sh_mobile_i2c_xfer_atomic(struct i2c_adapter *adapter,
735
+ struct i2c_msg *msgs,
736
+ int num)
737
+{
738
+ struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
739
+
740
+ pd->atomic_xfer = true;
741
+ return sh_mobile_xfer(pd, msgs, num);
742
+}
743
+
737744 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
738745 {
739746 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
740747 }
741748
742749 static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
743
- .functionality = sh_mobile_i2c_func,
744
- .master_xfer = sh_mobile_i2c_xfer,
750
+ .functionality = sh_mobile_i2c_func,
751
+ .master_xfer = sh_mobile_i2c_xfer,
752
+ .master_xfer_atomic = sh_mobile_i2c_xfer_atomic,
745753 };
746754
747755 static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
....@@ -749,8 +757,7 @@
749757 };
750758
751759 /*
752
- * r8a7740 chip has lasting errata on I2C I/O pad reset.
753
- * this is work-around for it.
760
+ * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround.
754761 */
755762 static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
756763 {
....@@ -800,17 +807,17 @@
800807 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
801808 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
802809 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
803
- { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
810
+ { .compatible = "renesas,iic-r8a774c0", .data = &v2_freq_calc_dt_config },
804811 { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
805
- { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
806
- { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
807
- { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
808
- { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
809
- { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
810
- { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
811
- { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
812
- { .compatible = "renesas,iic-r8a77990", .data = &fast_clock_dt_config },
812
+ { .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config },
813
+ { .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config },
814
+ { .compatible = "renesas,iic-r8a7793", .data = &v2_freq_calc_dt_config },
815
+ { .compatible = "renesas,iic-r8a7794", .data = &v2_freq_calc_dt_config },
816
+ { .compatible = "renesas,iic-r8a7795", .data = &v2_freq_calc_dt_config },
817
+ { .compatible = "renesas,iic-r8a77990", .data = &v2_freq_calc_dt_config },
813818 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
819
+ { .compatible = "renesas,rcar-gen2-iic", .data = &v2_freq_calc_dt_config },
820
+ { .compatible = "renesas,rcar-gen3-iic", .data = &v2_freq_calc_dt_config },
814821 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
815822 {},
816823 };
....@@ -884,7 +891,7 @@
884891 return PTR_ERR(pd->reg);
885892
886893 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
887
- pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
894
+ pd->bus_speed = (ret || !bus_speed) ? I2C_MAX_STANDARD_MODE_FREQ : bus_speed;
888895 pd->clks_per_count = 1;
889896
890897 /* Newer variants come with two new bits in ICIC */
....@@ -949,27 +956,9 @@
949956 return 0;
950957 }
951958
952
-static int sh_mobile_i2c_runtime_nop(struct device *dev)
953
-{
954
- /* Runtime PM callback shared between ->runtime_suspend()
955
- * and ->runtime_resume(). Simply returns success.
956
- *
957
- * This driver re-initializes all registers after
958
- * pm_runtime_get_sync() anyway so there is no need
959
- * to save and restore registers here.
960
- */
961
- return 0;
962
-}
963
-
964
-static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
965
- .runtime_suspend = sh_mobile_i2c_runtime_nop,
966
- .runtime_resume = sh_mobile_i2c_runtime_nop,
967
-};
968
-
969959 static struct platform_driver sh_mobile_i2c_driver = {
970960 .driver = {
971961 .name = "i2c-sh_mobile",
972
- .pm = &sh_mobile_i2c_dev_pm_ops,
973962 .of_match_table = sh_mobile_i2c_dt_ids,
974963 },
975964 .probe = sh_mobile_i2c_probe,
....@@ -989,6 +978,7 @@
989978 module_exit(sh_mobile_i2c_adap_exit);
990979
991980 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
992
-MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
981
+MODULE_AUTHOR("Magnus Damm");
982
+MODULE_AUTHOR("Wolfram Sang");
993983 MODULE_LICENSE("GPL v2");
994984 MODULE_ALIAS("platform:i2c-sh_mobile");