forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/i2c/busses/i2c-rcar.c
....@@ -2,8 +2,8 @@
22 /*
33  * Driver for the Renesas R-Car I2C unit
44  *
5
- * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
6
- * Copyright (C) 2011-2015 Renesas Electronics Corporation
5
+ * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6
+ * Copyright (C) 2011-2019 Renesas Electronics Corporation
77  *
88  * Copyright (C) 2012-14 Renesas Solutions Corp.
99  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
....@@ -19,7 +19,9 @@
1919 #include <linux/err.h>
2020 #include <linux/interrupt.h>
2121 #include <linux/io.h>
22
+#include <linux/iopoll.h>
2223 #include <linux/i2c.h>
24
+#include <linux/i2c-smbus.h>
2325 #include <linux/kernel.h>
2426 #include <linux/module.h>
2527 #include <linux/of_device.h>
....@@ -39,8 +41,8 @@
3941 #define ICSAR	0x1C	/* slave address */
4042 #define ICMAR	0x20	/* master address */
4143 #define ICRXTX	0x24	/* data port */
42
-#define ICDMAER	0x3c	/* DMA enable */
43
-#define ICFBSCR	0x38	/* first bit setup cycle */
44
+#define ICFBSCR	0x38	/* first bit setup cycle (Gen3) */
45
+#define ICDMAER	0x3c	/* DMA enable (Gen3) */
4446 
4547 /* ICSCR */
4648 #define SDBS	(1 << 3)	/* slave data buffer select */
....@@ -83,13 +85,12 @@
8385 #define TMDMAE	(1 << 0)	/* DMA Master Transmitted Enable */
8486 
8587 /* ICFBSCR */
86
-#define TCYC06	0x04		/*  6*Tcyc delay 1st bit between SDA and SCL */
8788 #define TCYC17	0x0f		/* 17*Tcyc delay 1st bit between SDA and SCL */
8889 
90
+#define RCAR_MIN_DMA_LEN	8
8991 
9092 #define RCAR_BUS_PHASE_START	(MDBS | MIE | ESG)
9193 #define RCAR_BUS_PHASE_DATA	(MDBS | MIE)
92
-#define RCAR_BUS_MASK_DATA	(~(ESG | FSB) & 0xFF)
9394 #define RCAR_BUS_PHASE_STOP	(MDBS | MIE | FSB)
9495 
9596 #define RCAR_IRQ_SEND	(MNR | MAL | MST | MAT | MDE)
....@@ -105,10 +106,11 @@
105106 #define ID_ARBLOST	(1 << 3)
106107 #define ID_NACK		(1 << 4)
107108 /* persistent flags */
109
+#define ID_P_HOST_NOTIFY	BIT(28)
108110 #define ID_P_REP_AFTER_RD	BIT(29)
109111 #define ID_P_NO_RXDMA		BIT(30) /* HW forbids RXDMA sometimes */
110112 #define ID_P_PM_BLOCKED		BIT(31)
111
-#define ID_P_MASK		GENMASK(31, 29)
113
+#define ID_P_MASK		GENMASK(31, 28)
112114 
113115 enum rcar_i2c_type {
114116 	I2C_RCAR_GEN1,
....@@ -140,13 +142,12 @@
140142 
141143 	struct reset_control *rstc;
142144 	int irq;
145
+
146
+	struct i2c_client *host_notify_client;
143147 };
144148 
145149 #define rcar_i2c_priv_to_dev(p)		((p)->adap.dev.parent)
146150 #define rcar_i2c_is_recv(p)		((p)->msg->flags & I2C_M_RD)
147
-
148
-#define LOOP_TIMEOUT	1024
149
-
150151 
151152 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
152153 {
....@@ -213,35 +214,42 @@
213214 	rcar_i2c_write(priv, ICMSR, 0);
214215 	/* start clock */
215216 	rcar_i2c_write(priv, ICCCR, priv->icccr);
217
+
218
+	if (priv->devtype == I2C_RCAR_GEN3)
219
+		rcar_i2c_write(priv, ICFBSCR, TCYC17);
220
+
216221 }
217222 
218223 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
219224 {
220
-	int i;
225
+	int ret;
226
+	u32 val;
221227 
222
-	for (i = 0; i < LOOP_TIMEOUT; i++) {
223
-		/* make sure that bus is not busy */
224
-		if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
225
-			return 0;
226
-		udelay(1);
228
+	ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
229
+				 priv->adap.timeout);
230
+	if (ret) {
231
+		/* Waiting did not help, try to recover */
232
+		priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
233
+		ret = i2c_recover_bus(&priv->adap);
227234 	}
228235 
229
-	/* Waiting did not help, try to recover */
230
-	priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
231
-	return i2c_recover_bus(&priv->adap);
236
+	return ret;
232237 }
233238 
234
-static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
239
+static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
235240 {
236241 	u32 scgd, cdf, round, ick, sum, scl, cdf_width;
237242 	unsigned long rate;
238243 	struct device *dev = rcar_i2c_priv_to_dev(priv);
244
+	struct i2c_timings t = {
245
+		.bus_freq_hz		= I2C_MAX_STANDARD_MODE_FREQ,
246
+		.scl_fall_ns		= 35,
247
+		.scl_rise_ns		= 200,
248
+		.scl_int_delay_ns	= 50,
249
+	};
239250 
240251 	/* Fall back to previously used values if not supplied */
241
-	t->bus_freq_hz = t->bus_freq_hz ?: 100000;
242
-	t->scl_fall_ns = t->scl_fall_ns ?: 35;
243
-	t->scl_rise_ns = t->scl_rise_ns ?: 200;
244
-	t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
252
+	i2c_parse_fw_timings(dev, &t, false);
245253 
246254 	switch (priv->devtype) {
247255 	case I2C_RCAR_GEN1:
....@@ -287,7 +295,7 @@
287295 	 *  = F[sum * ick / 1000000000]
288296 	 *  = F[(ick / 1000000) * sum / 1000]
289297 	 */
290
-	sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
298
+	sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
291299 	round = (ick + 500000) / 1000000 * sum;
292300 	round = (round + 500) / 1000;
293301 
....@@ -305,7 +313,7 @@
305313 	 */
306314 	for (scgd = 0; scgd < 0x40; scgd++) {
307315 		scl = ick / (20 + (scgd * 8) + round);
308
-		if (scl <= t->bus_freq_hz)
316
+		if (scl <= t.bus_freq_hz)
309317 			goto scgd_find;
310318 	}
311319 	dev_err(dev, "it is impossible to calculate best SCL\n");
....@@ -313,7 +321,7 @@
313321 
314322 scgd_find:
315323 	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
316
-		scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
324
+		scl, t.bus_freq_hz, rate, round, cdf, scgd);
317325 
318326 	/* keep icccr value */
319327 	priv->icccr = scgd << cdf_width | cdf;
....@@ -356,19 +364,10 @@
356364 	rcar_i2c_prepare_msg(priv);
357365 }
358366 
359
-/*
360
- *		interrupt functions
361
- */
362367 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
363368 {
364369 	struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
365370 		? priv->dma_rx : priv->dma_tx;
366
-
367
-	/* Disable DMA Master Received/Transmitted */
368
-	rcar_i2c_write(priv, ICDMAER, 0);
369
-
370
-	/* Reset default delay */
371
-	rcar_i2c_write(priv, ICFBSCR, TCYC06);
372371 
373372 	dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
374373 			 sg_dma_len(&priv->sg), priv->dma_direction);
....@@ -379,6 +378,9 @@
379378 		priv->flags |= ID_P_NO_RXDMA;
380379 
381380 	priv->dma_direction = DMA_NONE;
381
+
382
+	/* Disable DMA Master Received/Transmitted, must be last! */
383
+	rcar_i2c_write(priv, ICDMAER, 0);
382384 }
383385 
384386 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
....@@ -402,7 +404,7 @@
402404 	rcar_i2c_dma_unmap(priv);
403405 }
404406 
405
-static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
407
+static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
406408 {
407409 	struct device *dev = rcar_i2c_priv_to_dev(priv);
408410 	struct i2c_msg *msg = priv->msg;
....@@ -416,9 +418,9 @@
416418 	int len;
417419 
418420 	/* Do various checks to see if DMA is feasible at all */
419
-	if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) ||
420
-	    (read && priv->flags & ID_P_NO_RXDMA))
421
-		return;
421
+	if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
422
+	    !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
423
+		return false;
422424 
423425 	if (read) {
424426 		/*
....@@ -438,7 +440,7 @@
438440 	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
439441 	if (dma_mapping_error(chan->device->dev, dma_addr)) {
440442 		dev_dbg(dev, "dma map failed, using PIO\n");
441
-		return;
443
+		return false;
442444 	}
443445 
444446 	sg_dma_len(&priv->sg) = len;
....@@ -452,7 +454,7 @@
452454 	if (!txdesc) {
453455 		dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
454456 		rcar_i2c_cleanup_dma(priv);
455
-		return;
457
+		return false;
456458 	}
457459 
458460 	txdesc->callback = rcar_i2c_dma_callback;
....@@ -462,11 +464,8 @@
462464 	if (dma_submit_error(cookie)) {
463465 		dev_dbg(dev, "submitting dma failed, using PIO\n");
464466 		rcar_i2c_cleanup_dma(priv);
465
-		return;
467
+		return false;
466468 	}
467
-
468
-	/* Set delay for DMA operations */
469
-	rcar_i2c_write(priv, ICFBSCR, TCYC17);
470469 
471470 	/* Enable DMA Master Received/Transmitted */
472471 	if (read)
....@@ -475,6 +474,7 @@
475474 		rcar_i2c_write(priv, ICDMAER, TMDMAE);
476475 
477476 	dma_async_issue_pending(chan);
477
+	return true;
478478 }
479479 
480480 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
....@@ -483,6 +483,10 @@
483483 
484484 	/* FIXME: sometimes, unknown interrupt happened. Do nothing */
485485 	if (!(msr & MDE))
486
+		return;
487
+
488
+	/* Check if DMA can be enabled and take over */
489
+	if (priv->pos == 1 && rcar_i2c_dma(priv))
486490 		return;
487491 
488492 	if (priv->pos < msg->len) {
....@@ -495,13 +499,6 @@
495499 		 */
496500 		rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
497501 		priv->pos++;
498
-
499
-		/*
500
-		 * Try to use DMA to transmit the rest of the data if
501
-		 * address transfer phase just finished.
502
-		 */
503
-		if (msr & MAT)
504
-			rcar_i2c_dma(priv);
505502 	} else {
506503 		/*
507504 		 * The last data was pushed to ICRXTX on _PREV_ empty irq.
....@@ -620,21 +617,19 @@
620617 	return true;
621618 }
622619 
623
-static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
620
+/*
621
+ * This driver has a lock-free design because there are IP cores (at least
622
+ * R-Car Gen2) which have an inherent race condition in their hardware design.
623
+ * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
624
+ * the interrupt was generated, otherwise an unwanted repeated message gets
625
+ * generated. It turned out that taking a spinlock at the beginning of the ISR
626
+ * was already causing repeated messages. Thus, this driver was converted to
627
+ * the now lockless behaviour. Please keep this in mind when hacking the driver.
628
+ * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
629
+ * likely affected. Therefore, we have different interrupt handler entries.
630
+ */
631
+static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
624632 {
625
-	struct rcar_i2c_priv *priv = ptr;
626
-	u32 msr, val;
627
-
628
-	/* Clear START or STOP immediately, except for REPSTART after read */
629
-	if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
630
-		val = rcar_i2c_read(priv, ICMCR);
631
-		rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
632
-	}
633
-
634
-	msr = rcar_i2c_read(priv, ICMSR);
635
-
636
-	/* Only handle interrupts that are currently enabled */
637
-	msr &= rcar_i2c_read(priv, ICMIER);
638633 	if (!msr) {
639634 		if (rcar_i2c_slave_irq(priv))
640635 			return IRQ_HANDLED;
....@@ -676,6 +671,41 @@
676671 	}
677672 
678673 	return IRQ_HANDLED;
674
+}
675
+
676
+static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
677
+{
678
+	struct rcar_i2c_priv *priv = ptr;
679
+	u32 msr;
680
+
681
+	/* Clear START or STOP immediately, except for REPSTART after read */
682
+	if (likely(!(priv->flags & ID_P_REP_AFTER_RD)))
683
+		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
684
+
685
+	/* Only handle interrupts that are currently enabled */
686
+	msr = rcar_i2c_read(priv, ICMSR);
687
+	msr &= rcar_i2c_read(priv, ICMIER);
688
+
689
+	return rcar_i2c_irq(irq, priv, msr);
690
+}
691
+
692
+static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
693
+{
694
+	struct rcar_i2c_priv *priv = ptr;
695
+	u32 msr;
696
+
697
+	/* Only handle interrupts that are currently enabled */
698
+	msr = rcar_i2c_read(priv, ICMSR);
699
+	msr &= rcar_i2c_read(priv, ICMIER);
700
+
701
+	/*
702
+	 * Clear START or STOP immediately, except for REPSTART after read or
703
+	 * if a spurious interrupt was detected.
704
+	 */
705
+	if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr))
706
+		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
707
+
708
+	return rcar_i2c_irq(irq, priv, msr);
679709 }
680710 
681711 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
....@@ -755,20 +785,14 @@
755785 /* I2C is a special case, we need to poll the status of a reset */
756786 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
757787 {
758
-	int i, ret;
788
+	int ret;
759789 
760790 	ret = reset_control_reset(priv->rstc);
761791 	if (ret)
762792 		return ret;
763793 
764
-	for (i = 0; i < LOOP_TIMEOUT; i++) {
765
-		ret = reset_control_status(priv->rstc);
766
-		if (ret == 0)
767
-			return 0;
768
-		udelay(1);
769
-	}
770
-
771
-	return -ETIMEDOUT;
794
+	return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
795
+					100, false, priv->rstc);
772796 }
773797 
774798 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
....@@ -879,14 +903,21 @@
879903 
880904 static u32 rcar_i2c_func(struct i2c_adapter *adap)
881905 {
906
+	struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
907
+
882908 	/*
883909 	 * This HW can't do:
884910 	 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
885911 	 * I2C_M_NOSTART (automatically sends address after START)
886912 	 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
887913 	 */
888
-	return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
889
-		(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
914
+	u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
915
+		   (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
916
+
917
+	if (priv->flags & ID_P_HOST_NOTIFY)
918
+		func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
919
+
920
+	return func;
890921 }
891922 
892923 static const struct i2c_algorithm rcar_i2c_algo = {
....@@ -923,8 +954,12 @@
923954 	struct rcar_i2c_priv *priv;
924955 	struct i2c_adapter *adap;
925956 	struct device *dev = &pdev->dev;
926
-	struct i2c_timings i2c_t;
957
+	unsigned long irqflags = 0;
958
+	irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
927959 	int ret;
960
+
961
+	/* Otherwise logic will break because some bytes must always use PIO */
962
+	BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
928963 
929964 	priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
930965 	if (!priv)
....@@ -936,9 +971,7 @@
936971 		return PTR_ERR(priv->clk);
937972 	}
938973 
939
-	priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940
-
941
-	priv->io = devm_ioremap_resource(dev, priv->res);
974
+	priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
942975 	if (IS_ERR(priv->io))
943976 		return PTR_ERR(priv->io);
944977 
....@@ -957,8 +990,6 @@
957990 	i2c_set_adapdata(adap, priv);
958991 	strlcpy(adap->name, pdev->name, sizeof(adap->name));
959992 
960
-	i2c_parse_fw_timings(dev, &i2c_t, false);
961
-
962993 	/* Init DMA */
963994 	sg_init_table(&priv->sg, 1);
964995 	priv->dma_direction = DMA_NONE;
....@@ -967,11 +998,18 @@
967998 	/* Activate device for clock calculation */
968999 	pm_runtime_enable(dev);
9691000 	pm_runtime_get_sync(dev);
970
-	ret = rcar_i2c_clock_calculate(priv, &i2c_t);
971
-	if (ret < 0)
972
-		goto out_pm_put;
1001
+	ret = rcar_i2c_clock_calculate(priv);
1002
+	if (ret < 0) {
1003
+		pm_runtime_put(dev);
1004
+		goto out_pm_disable;
1005
+	}
9731006 
9741007 	rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
1008
+
1009
+	if (priv->devtype < I2C_RCAR_GEN3) {
1010
+		irqflags |= IRQF_NO_THREAD;
1011
+		irqhandler = rcar_i2c_gen2_irq;
1012
+	}
9751013 
9761014 	if (priv->devtype == I2C_RCAR_GEN3) {
9771015 		priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
....@@ -988,26 +1026,42 @@
9881026 	else
9891027 		pm_runtime_put(dev);
9901028 
1029
+	if (of_property_read_bool(dev->of_node, "smbus"))
1030
+		priv->flags |= ID_P_HOST_NOTIFY;
9911031 
992
-	priv->irq = platform_get_irq(pdev, 0);
993
-	ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
1032
+	ret = platform_get_irq(pdev, 0);
1033
+	if (ret < 0)
1034
+		goto out_pm_put;
1035
+	priv->irq = ret;
1036
+	ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
9941037 	if (ret < 0) {
9951038 		dev_err(dev, "cannot get irq %d\n", priv->irq);
996
-		goto out_pm_disable;
1039
+		goto out_pm_put;
9971040 	}
9981041 
9991042 	platform_set_drvdata(pdev, priv);
10001043 
10011044 	ret = i2c_add_numbered_adapter(adap);
10021045 	if (ret < 0)
1003
-		goto out_pm_disable;
1046
+		goto out_pm_put;
1047
+
1048
+	if (priv->flags & ID_P_HOST_NOTIFY) {
1049
+		priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
1050
+		if (IS_ERR(priv->host_notify_client)) {
1051
+			ret = PTR_ERR(priv->host_notify_client);
1052
+			goto out_del_device;
1053
+		}
1054
+	}
10041055 
10051056 	dev_info(dev, "probed\n");
10061057 
10071058 	return 0;
10081059 
1060
+ out_del_device:
1061
+	i2c_del_adapter(&priv->adap);
10091062  out_pm_put:
1010
-	pm_runtime_put(dev);
1063
+	if (priv->flags & ID_P_PM_BLOCKED)
1064
+		pm_runtime_put(dev);
10111065  out_pm_disable:
10121066 	pm_runtime_disable(dev);
10131067 	return ret;
....@@ -1018,6 +1072,8 @@
10181072 	struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
10191073 	struct device *dev = &pdev->dev;
10201074 
1075
+	if (priv->host_notify_client)
1076
+		i2c_free_slave_host_notify_device(priv->host_notify_client);
10211077 	i2c_del_adapter(&priv->adap);
10221078 	rcar_i2c_release_dma(priv);
10231079 	if (priv->flags & ID_P_PM_BLOCKED)
....@@ -1027,10 +1083,37 @@
10271083 	return 0;
10281084 }
10291085 
1086
+#ifdef CONFIG_PM_SLEEP
1087
+static int rcar_i2c_suspend(struct device *dev)
1088
+{
1089
+	struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1090
+
1091
+	i2c_mark_adapter_suspended(&priv->adap);
1092
+	return 0;
1093
+}
1094
+
1095
+static int rcar_i2c_resume(struct device *dev)
1096
+{
1097
+	struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1098
+
1099
+	i2c_mark_adapter_resumed(&priv->adap);
1100
+	return 0;
1101
+}
1102
+
1103
+static const struct dev_pm_ops rcar_i2c_pm_ops = {
1104
+	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1105
+};
1106
+
1107
+#define DEV_PM_OPS (&rcar_i2c_pm_ops)
1108
+#else
1109
+#define DEV_PM_OPS NULL
1110
+#endif /* CONFIG_PM_SLEEP */
1111
+
10301112 static struct platform_driver rcar_i2c_driver = {
10311113 	.driver	= {
10321114 		.name	= "i2c-rcar",
10331115 		.of_match_table = rcar_i2c_dt_ids,
1116
+		.pm	= DEV_PM_OPS,
10341117 	},
10351118 	.probe		= rcar_i2c_probe,
10361119 	.remove		= rcar_i2c_remove,