.. | .. |
---|
1752 | 1752 | if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) { |
---|
1753 | 1753 | dev_err(qup->dev, "clock frequency not supported %d\n", |
---|
1754 | 1754 | clk_freq); |
---|
1755 | | - return -EINVAL; |
---|
| 1755 | + ret = -EINVAL; |
---|
| 1756 | + goto fail_dma; |
---|
1756 | 1757 | } |
---|
1757 | 1758 | |
---|
1758 | 1759 | qup->base = devm_platform_ioremap_resource(pdev, 0); |
---|
1759 | | - if (IS_ERR(qup->base)) |
---|
1760 | | - return PTR_ERR(qup->base); |
---|
| 1760 | + if (IS_ERR(qup->base)) { |
---|
| 1761 | + ret = PTR_ERR(qup->base); |
---|
| 1762 | + goto fail_dma; |
---|
| 1763 | + } |
---|
1761 | 1764 | |
---|
1762 | 1765 | qup->irq = platform_get_irq(pdev, 0); |
---|
1763 | | - if (qup->irq < 0) |
---|
1764 | | - return qup->irq; |
---|
| 1766 | + if (qup->irq < 0) { |
---|
| 1767 | + ret = qup->irq; |
---|
| 1768 | + goto fail_dma; |
---|
| 1769 | + } |
---|
1765 | 1770 | |
---|
1766 | 1771 | if (has_acpi_companion(qup->dev)) { |
---|
1767 | 1772 | ret = device_property_read_u32(qup->dev, |
---|
.. | .. |
---|
1775 | 1780 | qup->clk = devm_clk_get(qup->dev, "core"); |
---|
1776 | 1781 | if (IS_ERR(qup->clk)) { |
---|
1777 | 1782 | dev_err(qup->dev, "Could not get core clock\n"); |
---|
1778 | | - return PTR_ERR(qup->clk); |
---|
| 1783 | + ret = PTR_ERR(qup->clk); |
---|
| 1784 | + goto fail_dma; |
---|
1779 | 1785 | } |
---|
1780 | 1786 | |
---|
1781 | 1787 | qup->pclk = devm_clk_get(qup->dev, "iface"); |
---|
1782 | 1788 | if (IS_ERR(qup->pclk)) { |
---|
1783 | 1789 | dev_err(qup->dev, "Could not get iface clock\n"); |
---|
1784 | | - return PTR_ERR(qup->pclk); |
---|
| 1790 | + ret = PTR_ERR(qup->pclk); |
---|
| 1791 | + goto fail_dma; |
---|
1785 | 1792 | } |
---|
1786 | 1793 | qup_i2c_enable_clocks(qup); |
---|
1787 | 1794 | src_clk_freq = clk_get_rate(qup->clk); |
---|