~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,15 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2014 MediaTek Inc.
3	4	* Author: Xudong Chen <xudong.chen@mediatek.com>
4		- *
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License version 2 as
7		- * published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13	5	*/
14	6
15	7	#include <linux/clk.h>
..	..	@@ -35,6 +27,7 @@
35	27	#include <linux/slab.h>
36	28
37	29	#define I2C_RS_TRANSFER (1 << 4)
	30	+#define I2C_ARB_LOST (1 << 3)
38	31	#define I2C_HS_NACKERR (1 << 2)
39	32	#define I2C_ACKERR (1 << 1)
40	33	#define I2C_TRANSAC_COMP (1 << 0)
..	..	@@ -45,6 +38,7 @@
45	38	#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
46	39	#define I2C_IO_CONFIG_PUSH_PULL 0x0000
47	40	#define I2C_SOFT_RST 0x0001
	41	+#define I2C_HANDSHAKE_RST 0x0020
48	42	#define I2C_FIFO_ADDR_CLR 0x0001
49	43	#define I2C_DELAY_LEN 0x0002
50	44	#define I2C_ST_START_CON 0x8001
..	..	@@ -53,22 +47,28 @@
53	47	#define I2C_TIME_DEFAULT_VALUE 0x0003
54	48	#define I2C_WRRD_TRANAC_VALUE 0x0002
55	49	#define I2C_RD_TRANAC_VALUE 0x0001
	50	+#define I2C_SCL_MIS_COMP_VALUE 0x0000
	51	+#define I2C_CHN_CLR_FLAG 0x0000
56	52
57	53	#define I2C_DMA_CON_TX 0x0000
58	54	#define I2C_DMA_CON_RX 0x0001
	55	+#define I2C_DMA_ASYNC_MODE 0x0004
	56	+#define I2C_DMA_SKIP_CONFIG 0x0010
	57	+#define I2C_DMA_DIR_CHANGE 0x0200
59	58	#define I2C_DMA_START_EN 0x0001
60	59	#define I2C_DMA_INT_FLAG_NONE 0x0000
61	60	#define I2C_DMA_CLR_FLAG 0x0000
	61	+#define I2C_DMA_WARM_RST 0x0001
62	62	#define I2C_DMA_HARD_RST 0x0002
63		-#define I2C_DMA_4G_MODE 0x0001
	63	+#define I2C_DMA_HANDSHAKE_RST 0x0004
64	64
65		-#define I2C_DEFAULT_CLK_DIV 5
66		-#define I2C_DEFAULT_SPEED 100000 /* hz */
67		-#define MAX_FS_MODE_SPEED 400000
68		-#define MAX_HS_MODE_SPEED 3400000
69	65	#define MAX_SAMPLE_CNT_DIV 8
70	66	#define MAX_STEP_CNT_DIV 64
	67	+#define MAX_CLOCK_DIV 256
71	68	#define MAX_HS_STEP_CNT_DIV 8
	69	+#define I2C_STANDARD_MODE_BUFFER (1000 / 2)
	70	+#define I2C_FAST_MODE_BUFFER (300 / 2)
	71	+#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
72	72
73	73	#define I2C_CONTROL_RS (0x1 << 1)
74	74	#define I2C_CONTROL_DMA_EN (0x1 << 2)
..	..	@@ -76,6 +76,8 @@
76	76	#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
77	77	#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
78	78	#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
	79	+#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
	80	+#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
79	81	#define I2C_CONTROL_WRAPPER (0x1 << 0)
80	82
81	83	#define I2C_DRV_NAME "i2c-mt65xx"
..	..	@@ -106,40 +108,125 @@
106	108	};
107	109
108	110	enum I2C_REGS_OFFSET {
109		- OFFSET_DATA_PORT = 0x0,
110		- OFFSET_SLAVE_ADDR = 0x04,
111		- OFFSET_INTR_MASK = 0x08,
112		- OFFSET_INTR_STAT = 0x0c,
113		- OFFSET_CONTROL = 0x10,
114		- OFFSET_TRANSFER_LEN = 0x14,
115		- OFFSET_TRANSAC_LEN = 0x18,
116		- OFFSET_DELAY_LEN = 0x1c,
117		- OFFSET_TIMING = 0x20,
118		- OFFSET_START = 0x24,
119		- OFFSET_EXT_CONF = 0x28,
120		- OFFSET_FIFO_STAT = 0x30,
121		- OFFSET_FIFO_THRESH = 0x34,
122		- OFFSET_FIFO_ADDR_CLR = 0x38,
123		- OFFSET_IO_CONFIG = 0x40,
124		- OFFSET_RSV_DEBUG = 0x44,
125		- OFFSET_HS = 0x48,
126		- OFFSET_SOFTRESET = 0x50,
127		- OFFSET_DCM_EN = 0x54,
128		- OFFSET_PATH_DIR = 0x60,
129		- OFFSET_DEBUGSTAT = 0x64,
130		- OFFSET_DEBUGCTRL = 0x68,
131		- OFFSET_TRANSFER_LEN_AUX = 0x6c,
132		- OFFSET_CLOCK_DIV = 0x70,
	111	+ OFFSET_DATA_PORT,
	112	+ OFFSET_SLAVE_ADDR,
	113	+ OFFSET_INTR_MASK,
	114	+ OFFSET_INTR_STAT,
	115	+ OFFSET_CONTROL,
	116	+ OFFSET_TRANSFER_LEN,
	117	+ OFFSET_TRANSAC_LEN,
	118	+ OFFSET_DELAY_LEN,
	119	+ OFFSET_TIMING,
	120	+ OFFSET_START,
	121	+ OFFSET_EXT_CONF,
	122	+ OFFSET_FIFO_STAT,
	123	+ OFFSET_FIFO_THRESH,
	124	+ OFFSET_FIFO_ADDR_CLR,
	125	+ OFFSET_IO_CONFIG,
	126	+ OFFSET_RSV_DEBUG,
	127	+ OFFSET_HS,
	128	+ OFFSET_SOFTRESET,
	129	+ OFFSET_DCM_EN,
	130	+ OFFSET_PATH_DIR,
	131	+ OFFSET_DEBUGSTAT,
	132	+ OFFSET_DEBUGCTRL,
	133	+ OFFSET_TRANSFER_LEN_AUX,
	134	+ OFFSET_CLOCK_DIV,
	135	+ OFFSET_LTIMING,
	136	+ OFFSET_SCL_HIGH_LOW_RATIO,
	137	+ OFFSET_HS_SCL_HIGH_LOW_RATIO,
	138	+ OFFSET_SCL_MIS_COMP_POINT,
	139	+ OFFSET_STA_STO_AC_TIMING,
	140	+ OFFSET_HS_STA_STO_AC_TIMING,
	141	+ OFFSET_SDA_TIMING,
	142	+};
	143	+
	144	+static const u16 mt_i2c_regs_v1[] = {
	145	+ [OFFSET_DATA_PORT] = 0x0,
	146	+ [OFFSET_SLAVE_ADDR] = 0x4,
	147	+ [OFFSET_INTR_MASK] = 0x8,
	148	+ [OFFSET_INTR_STAT] = 0xc,
	149	+ [OFFSET_CONTROL] = 0x10,
	150	+ [OFFSET_TRANSFER_LEN] = 0x14,
	151	+ [OFFSET_TRANSAC_LEN] = 0x18,
	152	+ [OFFSET_DELAY_LEN] = 0x1c,
	153	+ [OFFSET_TIMING] = 0x20,
	154	+ [OFFSET_START] = 0x24,
	155	+ [OFFSET_EXT_CONF] = 0x28,
	156	+ [OFFSET_FIFO_STAT] = 0x30,
	157	+ [OFFSET_FIFO_THRESH] = 0x34,
	158	+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
	159	+ [OFFSET_IO_CONFIG] = 0x40,
	160	+ [OFFSET_RSV_DEBUG] = 0x44,
	161	+ [OFFSET_HS] = 0x48,
	162	+ [OFFSET_SOFTRESET] = 0x50,
	163	+ [OFFSET_DCM_EN] = 0x54,
	164	+ [OFFSET_PATH_DIR] = 0x60,
	165	+ [OFFSET_DEBUGSTAT] = 0x64,
	166	+ [OFFSET_DEBUGCTRL] = 0x68,
	167	+ [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
	168	+ [OFFSET_CLOCK_DIV] = 0x70,
	169	+ [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
	170	+ [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
	171	+ [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
	172	+ [OFFSET_STA_STO_AC_TIMING] = 0x80,
	173	+ [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
	174	+ [OFFSET_SDA_TIMING] = 0x88,
	175	+};
	176	+
	177	+static const u16 mt_i2c_regs_v2[] = {
	178	+ [OFFSET_DATA_PORT] = 0x0,
	179	+ [OFFSET_SLAVE_ADDR] = 0x4,
	180	+ [OFFSET_INTR_MASK] = 0x8,
	181	+ [OFFSET_INTR_STAT] = 0xc,
	182	+ [OFFSET_CONTROL] = 0x10,
	183	+ [OFFSET_TRANSFER_LEN] = 0x14,
	184	+ [OFFSET_TRANSAC_LEN] = 0x18,
	185	+ [OFFSET_DELAY_LEN] = 0x1c,
	186	+ [OFFSET_TIMING] = 0x20,
	187	+ [OFFSET_START] = 0x24,
	188	+ [OFFSET_EXT_CONF] = 0x28,
	189	+ [OFFSET_LTIMING] = 0x2c,
	190	+ [OFFSET_HS] = 0x30,
	191	+ [OFFSET_IO_CONFIG] = 0x34,
	192	+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
	193	+ [OFFSET_SDA_TIMING] = 0x3c,
	194	+ [OFFSET_TRANSFER_LEN_AUX] = 0x44,
	195	+ [OFFSET_CLOCK_DIV] = 0x48,
	196	+ [OFFSET_SOFTRESET] = 0x50,
	197	+ [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
	198	+ [OFFSET_DEBUGSTAT] = 0xe4,
	199	+ [OFFSET_DEBUGCTRL] = 0xe8,
	200	+ [OFFSET_FIFO_STAT] = 0xf4,
	201	+ [OFFSET_FIFO_THRESH] = 0xf8,
	202	+ [OFFSET_DCM_EN] = 0xf88,
133	203	};
134	204
135	205	struct mtk_i2c_compatible {
136	206	const struct i2c_adapter_quirks *quirks;
	207	+ const u16 *regs;
137	208	unsigned char pmic_i2c: 1;
138	209	unsigned char dcm: 1;
139	210	unsigned char auto_restart: 1;
140	211	unsigned char aux_len_reg: 1;
141		- unsigned char support_33bits: 1;
142	212	unsigned char timing_adjust: 1;
	213	+ unsigned char dma_sync: 1;
	214	+ unsigned char ltiming_adjust: 1;
	215	+ unsigned char apdma_sync: 1;
	216	+ unsigned char max_dma_support;
	217	+};
	218	+
	219	+struct mtk_i2c_ac_timing {
	220	+ u16 htiming;
	221	+ u16 ltiming;
	222	+ u16 hs;
	223	+ u16 ext;
	224	+ u16 inter_clk_div;
	225	+ u16 scl_hl_ratio;
	226	+ u16 hs_scl_hl_ratio;
	227	+ u16 sta_stop;
	228	+ u16 hs_sta_stop;
	229	+ u16 sda_timing;
143	230	};
144	231
145	232	struct mtk_i2c {
..	..	@@ -153,6 +240,7 @@
153	240	struct clk clk_main; / main clock for i2c bus */
154	241	struct clk clk_dma; / DMA clock for i2c via DMA */
155	242	struct clk clk_pmic; / PMIC clock for i2c from PMIC */
	243	+ struct clk clk_arb; / Arbitrator clock for i2c */
156	244	bool have_pmic; /* can use i2c pins from PMIC */
157	245	bool use_push_pull; /* IO config push-pull mode */
158	246
..	..	@@ -162,9 +250,46 @@
162	250	enum mtk_trans_op op;
163	251	u16 timing_reg;
164	252	u16 high_speed_reg;
	253	+ u16 ltiming_reg;
165	254	unsigned char auto_restart;
166	255	bool ignore_restart_irq;
	256	+ struct mtk_i2c_ac_timing ac_timing;
167	257	const struct mtk_i2c_compatible *dev_comp;
	258	+};
	259	+
	260	+/**
	261	+ * struct i2c_spec_values:
	262	+ * @min_low_ns: min LOW period of the SCL clock
	263	+ * @min_su_sta_ns: min set-up time for a repeated START condition
	264	+ * @max_hd_dat_ns: max data hold time
	265	+ * @min_su_dat_ns: min data set-up time
	266	+ */
	267	+struct i2c_spec_values {
	268	+ unsigned int min_low_ns;
	269	+ unsigned int min_su_sta_ns;
	270	+ unsigned int max_hd_dat_ns;
	271	+ unsigned int min_su_dat_ns;
	272	+};
	273	+
	274	+static const struct i2c_spec_values standard_mode_spec = {
	275	+ .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
	276	+ .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
	277	+ .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
	278	+ .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
	279	+};
	280	+
	281	+static const struct i2c_spec_values fast_mode_spec = {
	282	+ .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
	283	+ .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
	284	+ .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
	285	+ .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
	286	+};
	287	+
	288	+static const struct i2c_spec_values fast_mode_plus_spec = {
	289	+ .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
	290	+ .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
	291	+ .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
	292	+ .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
168	293	};
169	294
170	295	static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
..	..	@@ -180,52 +305,104 @@
180	305	.max_num_msgs = 255,
181	306	};
182	307
	308	+static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
	309	+ .flags = I2C_AQ_NO_ZERO_LEN,
	310	+};
	311	+
183	312	static const struct mtk_i2c_compatible mt2712_compat = {
	313	+ .regs = mt_i2c_regs_v1,
184	314	.pmic_i2c = 0,
185	315	.dcm = 1,
186	316	.auto_restart = 1,
187	317	.aux_len_reg = 1,
188		- .support_33bits = 1,
189	318	.timing_adjust = 1,
	319	+ .dma_sync = 0,
	320	+ .ltiming_adjust = 0,
	321	+ .apdma_sync = 0,
	322	+ .max_dma_support = 33,
190	323	};
191	324
192	325	static const struct mtk_i2c_compatible mt6577_compat = {
193	326	.quirks = &mt6577_i2c_quirks,
	327	+ .regs = mt_i2c_regs_v1,
194	328	.pmic_i2c = 0,
195	329	.dcm = 1,
196	330	.auto_restart = 0,
197	331	.aux_len_reg = 0,
198		- .support_33bits = 0,
199	332	.timing_adjust = 0,
	333	+ .dma_sync = 0,
	334	+ .ltiming_adjust = 0,
	335	+ .apdma_sync = 0,
	336	+ .max_dma_support = 32,
200	337	};
201	338
202	339	static const struct mtk_i2c_compatible mt6589_compat = {
203	340	.quirks = &mt6577_i2c_quirks,
	341	+ .regs = mt_i2c_regs_v1,
204	342	.pmic_i2c = 1,
205	343	.dcm = 0,
206	344	.auto_restart = 0,
207	345	.aux_len_reg = 0,
208		- .support_33bits = 0,
209	346	.timing_adjust = 0,
	347	+ .dma_sync = 0,
	348	+ .ltiming_adjust = 0,
	349	+ .apdma_sync = 0,
	350	+ .max_dma_support = 32,
210	351	};
211	352
212	353	static const struct mtk_i2c_compatible mt7622_compat = {
213	354	.quirks = &mt7622_i2c_quirks,
	355	+ .regs = mt_i2c_regs_v1,
214	356	.pmic_i2c = 0,
215	357	.dcm = 1,
216	358	.auto_restart = 1,
217	359	.aux_len_reg = 1,
218		- .support_33bits = 0,
219	360	.timing_adjust = 0,
	361	+ .dma_sync = 0,
	362	+ .ltiming_adjust = 0,
	363	+ .apdma_sync = 0,
	364	+ .max_dma_support = 32,
220	365	};
221	366
222	367	static const struct mtk_i2c_compatible mt8173_compat = {
	368	+ .regs = mt_i2c_regs_v1,
223	369	.pmic_i2c = 0,
224	370	.dcm = 1,
225	371	.auto_restart = 1,
226	372	.aux_len_reg = 1,
227		- .support_33bits = 1,
228	373	.timing_adjust = 0,
	374	+ .dma_sync = 0,
	375	+ .ltiming_adjust = 0,
	376	+ .apdma_sync = 0,
	377	+ .max_dma_support = 33,
	378	+};
	379	+
	380	+static const struct mtk_i2c_compatible mt8183_compat = {
	381	+ .quirks = &mt8183_i2c_quirks,
	382	+ .regs = mt_i2c_regs_v2,
	383	+ .pmic_i2c = 0,
	384	+ .dcm = 0,
	385	+ .auto_restart = 1,
	386	+ .aux_len_reg = 1,
	387	+ .timing_adjust = 1,
	388	+ .dma_sync = 1,
	389	+ .ltiming_adjust = 1,
	390	+ .apdma_sync = 0,
	391	+ .max_dma_support = 33,
	392	+};
	393	+
	394	+static const struct mtk_i2c_compatible mt8192_compat = {
	395	+ .quirks = &mt8183_i2c_quirks,
	396	+ .regs = mt_i2c_regs_v2,
	397	+ .pmic_i2c = 0,
	398	+ .dcm = 0,
	399	+ .auto_restart = 1,
	400	+ .aux_len_reg = 1,
	401	+ .timing_adjust = 1,
	402	+ .dma_sync = 1,
	403	+ .ltiming_adjust = 1,
	404	+ .apdma_sync = 1,
	405	+ .max_dma_support = 36,
229	406	};
230	407
231	408	static const struct of_device_id mtk_i2c_of_match[] = {
..	..	@@ -234,9 +411,22 @@
234	411	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
235	412	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
236	413	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
	414	+ { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
	415	+ { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
237	416	{}
238	417	};
239	418	MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
	419	+
	420	+static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
	421	+{
	422	+ return readw(i2c->base + i2c->dev_comp->regs[reg]);
	423	+}
	424	+
	425	+static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
	426	+ enum I2C_REGS_OFFSET reg)
	427	+{
	428	+ writew(val, i2c->base + i2c->dev_comp->regs[reg]);
	429	+}
240	430
241	431	static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
242	432	{
..	..	@@ -255,8 +445,18 @@
255	445	if (ret)
256	446	goto err_pmic;
257	447	}
	448	+
	449	+ if (i2c->clk_arb) {
	450	+ ret = clk_prepare_enable(i2c->clk_arb);
	451	+ if (ret)
	452	+ goto err_arb;
	453	+ }
	454	+
258	455	return 0;
259	456
	457	+err_arb:
	458	+ if (i2c->have_pmic)
	459	+ clk_disable_unprepare(i2c->clk_pmic);
260	460	err_pmic:
261	461	clk_disable_unprepare(i2c->clk_main);
262	462	err_main:
..	..	@@ -267,6 +467,9 @@
267	467
268	468	static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
269	469	{
	470	+ if (i2c->clk_arb)
	471	+ clk_disable_unprepare(i2c->clk_arb);
	472	+
270	473	if (i2c->have_pmic)
271	474	clk_disable_unprepare(i2c->clk_pmic);
272	475
..	..	@@ -277,36 +480,210 @@
277	480	static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
278	481	{
279	482	u16 control_reg;
	483	+ u16 intr_stat_reg;
	484	+ u16 ext_conf_val;
280	485
281		- writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
	486	+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
	487	+ intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
	488	+ mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
	489	+
	490	+ if (i2c->dev_comp->apdma_sync) {
	491	+ writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
	492	+ udelay(10);
	493	+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
	494	+ udelay(10);
	495	+ writel(I2C_DMA_HANDSHAKE_RST \| I2C_DMA_HARD_RST,
	496	+ i2c->pdmabase + OFFSET_RST);
	497	+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST \| I2C_SOFT_RST,
	498	+ OFFSET_SOFTRESET);
	499	+ udelay(10);
	500	+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
	501	+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
	502	+ } else {
	503	+ writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
	504	+ udelay(50);
	505	+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
	506	+ mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
	507	+ }
282	508
283	509	/* Set ioconfig */
284	510	if (i2c->use_push_pull)
285		- writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
	511	+ mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
286	512	else
287		- writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
	513	+ mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
288	514
289	515	if (i2c->dev_comp->dcm)
290		- writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
	516	+ mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
291	517
292		- if (i2c->dev_comp->timing_adjust)
293		- writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV);
	518	+ mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
	519	+ mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
	520	+ if (i2c->dev_comp->ltiming_adjust)
	521	+ mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
294	522
295		- writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
296		- writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
	523	+ if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
	524	+ ext_conf_val = I2C_ST_START_CON;
	525	+ else
	526	+ ext_conf_val = I2C_FS_START_CON;
	527	+
	528	+ if (i2c->dev_comp->timing_adjust) {
	529	+ ext_conf_val = i2c->ac_timing.ext;
	530	+ mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
	531	+ OFFSET_CLOCK_DIV);
	532	+ mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
	533	+ OFFSET_SCL_MIS_COMP_POINT);
	534	+ mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
	535	+ OFFSET_SDA_TIMING);
	536	+
	537	+ if (i2c->dev_comp->ltiming_adjust) {
	538	+ mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
	539	+ OFFSET_TIMING);
	540	+ mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
	541	+ mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
	542	+ OFFSET_LTIMING);
	543	+ } else {
	544	+ mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
	545	+ OFFSET_SCL_HIGH_LOW_RATIO);
	546	+ mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
	547	+ OFFSET_HS_SCL_HIGH_LOW_RATIO);
	548	+ mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
	549	+ OFFSET_STA_STO_AC_TIMING);
	550	+ mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
	551	+ OFFSET_HS_STA_STO_AC_TIMING);
	552	+ }
	553	+ }
	554	+ mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
297	555
298	556	/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
299	557	if (i2c->have_pmic)
300		- writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
	558	+ mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
301	559
302	560	control_reg = I2C_CONTROL_ACKERR_DET_EN \|
303	561	I2C_CONTROL_CLK_EXT_EN \| I2C_CONTROL_DMA_EN;
304		- writew(control_reg, i2c->base + OFFSET_CONTROL);
305		- writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
	562	+ if (i2c->dev_comp->dma_sync)
	563	+ control_reg \|= I2C_CONTROL_DMAACK_EN \| I2C_CONTROL_ASYNC_MODE;
306	564
307		- writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
308		- udelay(50);
309		- writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
	565	+ mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
	566	+ mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
	567	+}
	568	+
	569	+static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
	570	+{
	571	+ if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
	572	+ return &standard_mode_spec;
	573	+ else if (speed <= I2C_MAX_FAST_MODE_FREQ)
	574	+ return &fast_mode_spec;
	575	+ else
	576	+ return &fast_mode_plus_spec;
	577	+}
	578	+
	579	+static int mtk_i2c_max_step_cnt(unsigned int target_speed)
	580	+{
	581	+ if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
	582	+ return MAX_HS_STEP_CNT_DIV;
	583	+ else
	584	+ return MAX_STEP_CNT_DIV;
	585	+}
	586	+
	587	+/*
	588	+ * Check and Calculate i2c ac-timing
	589	+ *
	590	+ * Hardware design:
	591	+ * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
	592	+ * xxx_cnt_div = spec->min_xxx_ns / sample_ns
	593	+ *
	594	+ * Sample_ns is rounded down for xxx_cnt_div would be greater
	595	+ * than the smallest spec.
	596	+ * The sda_timing is chosen as the middle value between
	597	+ * the largest and smallest.
	598	+ */
	599	+static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
	600	+ unsigned int clk_src,
	601	+ unsigned int check_speed,
	602	+ unsigned int step_cnt,
	603	+ unsigned int sample_cnt)
	604	+{
	605	+ const struct i2c_spec_values *spec;
	606	+ unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
	607	+ unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
	608	+ unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
	609	+ clk_src);
	610	+
	611	+ if (!i2c->dev_comp->timing_adjust)
	612	+ return 0;
	613	+
	614	+ if (i2c->dev_comp->ltiming_adjust)
	615	+ max_sta_cnt = 0x100;
	616	+
	617	+ spec = mtk_i2c_get_spec(check_speed);
	618	+
	619	+ if (i2c->dev_comp->ltiming_adjust)
	620	+ clk_ns = 1000000000 / clk_src;
	621	+ else
	622	+ clk_ns = sample_ns / 2;
	623	+
	624	+ su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
	625	+ if (su_sta_cnt > max_sta_cnt)
	626	+ return -1;
	627	+
	628	+ low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
	629	+ max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
	630	+ if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
	631	+ if (low_cnt > step_cnt) {
	632	+ high_cnt = 2 * step_cnt - low_cnt;
	633	+ } else {
	634	+ high_cnt = step_cnt;
	635	+ low_cnt = step_cnt;
	636	+ }
	637	+ } else {
	638	+ return -2;
	639	+ }
	640	+
	641	+ sda_max = spec->max_hd_dat_ns / sample_ns;
	642	+ if (sda_max > low_cnt)
	643	+ sda_max = 0;
	644	+
	645	+ sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
	646	+ if (sda_min < low_cnt)
	647	+ sda_min = 0;
	648	+
	649	+ if (sda_min > sda_max)
	650	+ return -3;
	651	+
	652	+ if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
	653	+ if (i2c->dev_comp->ltiming_adjust) {
	654	+ i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE \|
	655	+ (sample_cnt << 12) \| (high_cnt << 8);
	656	+ i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
	657	+ i2c->ac_timing.ltiming \|= (sample_cnt << 12) \|
	658	+ (low_cnt << 9);
	659	+ i2c->ac_timing.ext &= ~GENMASK(7, 1);
	660	+ i2c->ac_timing.ext \|= (su_sta_cnt << 1) \| (1 << 0);
	661	+ } else {
	662	+ i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) \|
	663	+ (high_cnt << 6) \| low_cnt;
	664	+ i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) \|
	665	+ su_sta_cnt;
	666	+ }
	667	+ i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
	668	+ i2c->ac_timing.sda_timing \|= (1 << 12) \|
	669	+ ((sda_max + sda_min) / 2) << 6;
	670	+ } else {
	671	+ if (i2c->dev_comp->ltiming_adjust) {
	672	+ i2c->ac_timing.htiming = (sample_cnt << 8) \| (high_cnt);
	673	+ i2c->ac_timing.ltiming = (sample_cnt << 6) \| (low_cnt);
	674	+ i2c->ac_timing.ext = (su_sta_cnt << 8) \| (1 << 0);
	675	+ } else {
	676	+ i2c->ac_timing.scl_hl_ratio = (1 << 12) \|
	677	+ (high_cnt << 6) \| low_cnt;
	678	+ i2c->ac_timing.sta_stop = (su_sta_cnt << 8) \|
	679	+ su_sta_cnt;
	680	+ }
	681	+
	682	+ i2c->ac_timing.sda_timing = (1 << 12) \|
	683	+ (sda_max + sda_min) / 2;
	684	+ }
	685	+
	686	+ return 0;
310	687	}
311	688
312	689	/*
..	..	@@ -333,15 +710,12 @@
333	710	unsigned int opt_div;
334	711	unsigned int best_mul;
335	712	unsigned int cnt_mul;
	713	+ int ret = -EINVAL;
336	714
337		- if (target_speed > MAX_HS_MODE_SPEED)
338		- target_speed = MAX_HS_MODE_SPEED;
	715	+ if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
	716	+ target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
339	717
340		- if (target_speed > MAX_FS_MODE_SPEED)
341		- max_step_cnt = MAX_HS_STEP_CNT_DIV;
342		- else
343		- max_step_cnt = MAX_STEP_CNT_DIV;
344		-
	718	+ max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
345	719	base_step_cnt = max_step_cnt;
346	720	/* Find the best combination */
347	721	opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
..	..	@@ -360,6 +734,11 @@
360	734	continue;
361	735
362	736	if (cnt_mul < best_mul) {
	737	+ ret = mtk_i2c_check_ac_timing(i2c, clk_src,
	738	+ target_speed, step_cnt - 1, sample_cnt - 1);
	739	+ if (ret)
	740	+ continue;
	741	+
363	742	best_mul = cnt_mul;
364	743	base_sample_cnt = sample_cnt;
365	744	base_step_cnt = step_cnt;
..	..	@@ -367,6 +746,9 @@
367	746	break;
368	747	}
369	748	}
	749	+
	750	+ if (ret)
	751	+ return -EINVAL;
370	752
371	753	sample_cnt = base_sample_cnt;
372	754	step_cnt = base_step_cnt;
..	..	@@ -390,47 +772,72 @@
390	772	unsigned int clk_src;
391	773	unsigned int step_cnt;
392	774	unsigned int sample_cnt;
	775	+ unsigned int l_step_cnt;
	776	+ unsigned int l_sample_cnt;
393	777	unsigned int target_speed;
	778	+ unsigned int clk_div;
	779	+ unsigned int max_clk_div;
394	780	int ret;
395	781
396		- clk_src = parent_clk / i2c->clk_src_div;
397	782	target_speed = i2c->speed_hz;
	783	+ parent_clk /= i2c->clk_src_div;
398	784
399		- if (target_speed > MAX_FS_MODE_SPEED) {
400		- /* Set master code speed register */
401		- ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
402		- &step_cnt, &sample_cnt);
403		- if (ret < 0)
404		- return ret;
	785	+ if (i2c->dev_comp->timing_adjust)
	786	+ max_clk_div = MAX_CLOCK_DIV;
	787	+ else
	788	+ max_clk_div = 1;
405	789
406		- i2c->timing_reg = (sample_cnt << 8) \| step_cnt;
	790	+ for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
	791	+ clk_src = parent_clk / clk_div;
407	792
408		- /* Set the high speed mode register */
409		- ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
410		- &step_cnt, &sample_cnt);
411		- if (ret < 0)
412		- return ret;
	793	+ if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
	794	+ /* Set master code speed register */
	795	+ ret = mtk_i2c_calculate_speed(i2c, clk_src,
	796	+ I2C_MAX_FAST_MODE_FREQ,
	797	+ &l_step_cnt,
	798	+ &l_sample_cnt);
	799	+ if (ret < 0)
	800	+ continue;
413	801
414		- i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE \|
415		- (sample_cnt << 12) \| (step_cnt << 8);
416		- } else {
417		- ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
418		- &step_cnt, &sample_cnt);
419		- if (ret < 0)
420		- return ret;
	802	+ i2c->timing_reg = (l_sample_cnt << 8) \| l_step_cnt;
421	803
422		- i2c->timing_reg = (sample_cnt << 8) \| step_cnt;
	804	+ /* Set the high speed mode register */
	805	+ ret = mtk_i2c_calculate_speed(i2c, clk_src,
	806	+ target_speed, &step_cnt,
	807	+ &sample_cnt);
	808	+ if (ret < 0)
	809	+ continue;
423	810
424		- /* Disable the high speed transaction */
425		- i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
	811	+ i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE \|
	812	+ (sample_cnt << 12) \| (step_cnt << 8);
	813	+
	814	+ if (i2c->dev_comp->ltiming_adjust)
	815	+ i2c->ltiming_reg =
	816	+ (l_sample_cnt << 6) \| l_step_cnt \|
	817	+ (sample_cnt << 12) \| (step_cnt << 9);
	818	+ } else {
	819	+ ret = mtk_i2c_calculate_speed(i2c, clk_src,
	820	+ target_speed, &l_step_cnt,
	821	+ &l_sample_cnt);
	822	+ if (ret < 0)
	823	+ continue;
	824	+
	825	+ i2c->timing_reg = (l_sample_cnt << 8) \| l_step_cnt;
	826	+
	827	+ /* Disable the high speed transaction */
	828	+ i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
	829	+
	830	+ if (i2c->dev_comp->ltiming_adjust)
	831	+ i2c->ltiming_reg =
	832	+ (l_sample_cnt << 6) \| l_step_cnt;
	833	+ }
	834	+
	835	+ break;
426	836	}
427	837
428		- return 0;
429		-}
	838	+ i2c->ac_timing.inter_clk_div = clk_div - 1;
430	839
431		-static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
432		-{
433		- return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
	840	+ return 0;
434	841	}
435	842
436	843	static int mtk_i2c_do_transfer(struct mtk_i2c i2c, struct i2c_msg msgs,
..	..	@@ -440,6 +847,7 @@
440	847	u16 start_reg;
441	848	u16 control_reg;
442	849	u16 restart_flag = 0;
	850	+ u16 dma_sync = 0;
443	851	u32 reg_4g_mode;
444	852	u8 *dma_rd_buf = NULL;
445	853	u8 *dma_wr_buf = NULL;
..	..	@@ -454,54 +862,55 @@
454	862
455	863	reinit_completion(&i2c->msg_complete);
456	864
457		- control_reg = readw(i2c->base + OFFSET_CONTROL) &
	865	+ control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
458	866	~(I2C_CONTROL_DIR_CHANGE \| I2C_CONTROL_RS);
459		- if ((i2c->speed_hz > 400000) \|\| (left_num >= 1))
	867	+ if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) \|\| (left_num >= 1))
460	868	control_reg \|= I2C_CONTROL_RS;
461	869
462	870	if (i2c->op == I2C_MASTER_WRRD)
463	871	control_reg \|= I2C_CONTROL_DIR_CHANGE \| I2C_CONTROL_RS;
464	872
465		- writew(control_reg, i2c->base + OFFSET_CONTROL);
466		-
467		- /* set start condition */
468		- if (i2c->speed_hz <= 100000)
469		- writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
470		- else
471		- writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
	873	+ mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
472	874
473	875	addr_reg = i2c_8bit_addr_from_msg(msgs);
474		- writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
	876	+ mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
475	877
476	878	/* Clear interrupt status */
477		- writew(restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
478		- I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
479		- writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
	879	+ mtk_i2c_writew(i2c, restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
	880	+ I2C_ARB_LOST \| I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
	881	+
	882	+ mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
480	883
481	884	/* Enable interrupt */
482		- writew(restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
483		- I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
	885	+ mtk_i2c_writew(i2c, restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
	886	+ I2C_ARB_LOST \| I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
484	887
485	888	/* Set transfer and transaction len */
486	889	if (i2c->op == I2C_MASTER_WRRD) {
487	890	if (i2c->dev_comp->aux_len_reg) {
488		- writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
489		- writew((msgs + 1)->len, i2c->base +
490		- OFFSET_TRANSFER_LEN_AUX);
	891	+ mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
	892	+ mtk_i2c_writew(i2c, (msgs + 1)->len,
	893	+ OFFSET_TRANSFER_LEN_AUX);
491	894	} else {
492		- writew(msgs->len \| ((msgs + 1)->len) << 8,
493		- i2c->base + OFFSET_TRANSFER_LEN);
	895	+ mtk_i2c_writew(i2c, msgs->len \| ((msgs + 1)->len) << 8,
	896	+ OFFSET_TRANSFER_LEN);
494	897	}
495		- writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
	898	+ mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
496	899	} else {
497		- writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
498		- writew(num, i2c->base + OFFSET_TRANSAC_LEN);
	900	+ mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
	901	+ mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
	902	+ }
	903	+
	904	+ if (i2c->dev_comp->apdma_sync) {
	905	+ dma_sync = I2C_DMA_SKIP_CONFIG \| I2C_DMA_ASYNC_MODE;
	906	+ if (i2c->op == I2C_MASTER_WRRD)
	907	+ dma_sync \|= I2C_DMA_DIR_CHANGE;
499	908	}
500	909
501	910	/* Prepare buffer data to start transfer */
502	911	if (i2c->op == I2C_MASTER_RD) {
503	912	writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
504		- writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
	913	+ writel(I2C_DMA_CON_RX \| dma_sync, i2c->pdmabase + OFFSET_CON);
505	914
506	915	dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
507	916	if (!dma_rd_buf)
..	..	@@ -515,8 +924,8 @@
515	924	return -ENOMEM;
516	925	}
517	926
518		- if (i2c->dev_comp->support_33bits) {
519		- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
	927	+ if (i2c->dev_comp->max_dma_support > 32) {
	928	+ reg_4g_mode = upper_32_bits(rpaddr);
520	929	writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
521	930	}
522	931
..	..	@@ -524,7 +933,7 @@
524	933	writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
525	934	} else if (i2c->op == I2C_MASTER_WR) {
526	935	writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
527		- writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
	936	+ writel(I2C_DMA_CON_TX \| dma_sync, i2c->pdmabase + OFFSET_CON);
528	937
529	938	dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
530	939	if (!dma_wr_buf)
..	..	@@ -538,8 +947,8 @@
538	947	return -ENOMEM;
539	948	}
540	949
541		- if (i2c->dev_comp->support_33bits) {
542		- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
	950	+ if (i2c->dev_comp->max_dma_support > 32) {
	951	+ reg_4g_mode = upper_32_bits(wpaddr);
543	952	writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
544	953	}
545	954
..	..	@@ -547,7 +956,7 @@
547	956	writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
548	957	} else {
549	958	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
550		- writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
	959	+ writel(I2C_DMA_CLR_FLAG \| dma_sync, i2c->pdmabase + OFFSET_CON);
551	960
552	961	dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
553	962	if (!dma_wr_buf)
..	..	@@ -584,11 +993,11 @@
584	993	return -ENOMEM;
585	994	}
586	995
587		- if (i2c->dev_comp->support_33bits) {
588		- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
	996	+ if (i2c->dev_comp->max_dma_support > 32) {
	997	+ reg_4g_mode = upper_32_bits(wpaddr);
589	998	writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
590	999
591		- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
	1000	+ reg_4g_mode = upper_32_bits(rpaddr);
592	1001	writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
593	1002	}
594	1003
..	..	@@ -607,14 +1016,14 @@
607	1016	if (left_num >= 1)
608	1017	start_reg \|= I2C_RS_MUL_CNFG;
609	1018	}
610		- writew(start_reg, i2c->base + OFFSET_START);
	1019	+ mtk_i2c_writew(i2c, start_reg, OFFSET_START);
611	1020
612	1021	ret = wait_for_completion_timeout(&i2c->msg_complete,
613	1022	i2c->adap.timeout);
614	1023
615	1024	/* Clear interrupt mask */
616		- writew(~(restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
617		- I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
	1025	+ mtk_i2c_writew(i2c, ~(restart_flag \| I2C_HS_NACKERR \| I2C_ACKERR \|
	1026	+ I2C_ARB_LOST \| I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
618	1027
619	1028	if (i2c->op == I2C_MASTER_WR) {
620	1029	dma_unmap_single(i2c->dev, wpaddr,
..	..	@@ -641,8 +1050,6 @@
641	1050	mtk_i2c_init_hw(i2c);
642	1051	return -ETIMEDOUT;
643	1052	}
644		-
645		- completion_done(&i2c->msg_complete);
646	1053
647	1054	if (i2c->irq_stat & (I2C_HS_NACKERR \| I2C_ACKERR)) {
648	1055	dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
..	..	@@ -674,7 +1081,8 @@
674	1081	}
675	1082	}
676	1083
677		- if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
	1084	+ if (i2c->auto_restart && num >= 2 &&
	1085	+ i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
678	1086	/* ignore the first restart irq after the master code,
679	1087	* otherwise the first transfer will be discarded.
680	1088	*/
..	..	@@ -726,8 +1134,8 @@
726	1134	if (i2c->auto_restart)
727	1135	restart_flag = I2C_RS_TRANSFER;
728	1136
729		- intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
730		- writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
	1137	+ intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
	1138	+ mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
731	1139
732	1140	/*
733	1141	* when occurs ack error, i2c controller generate two interrupts
..	..	@@ -739,8 +1147,8 @@
739	1147	if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
740	1148	i2c->ignore_restart_irq = false;
741	1149	i2c->irq_stat = 0;
742		- writew(I2C_RS_MUL_CNFG \| I2C_RS_MUL_TRIG \| I2C_TRANSAC_START,
743		- i2c->base + OFFSET_START);
	1150	+ mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG \| I2C_RS_MUL_TRIG \|
	1151	+ I2C_TRANSAC_START, OFFSET_START);
744	1152	} else {
745	1153	if (i2c->irq_stat & (I2C_TRANSAC_COMP \| restart_flag))
746	1154	complete(&i2c->msg_complete);
..	..	@@ -751,7 +1159,11 @@
751	1159
752	1160	static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
753	1161	{
754		- return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	1162	+ if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
	1163	+ return I2C_FUNC_I2C \|
	1164	+ (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
	1165	+ else
	1166	+ return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
755	1167	}
756	1168
757	1169	static const struct i2c_algorithm mtk_i2c_algorithm = {
..	..	@@ -765,7 +1177,7 @@
765	1177
766	1178	ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
767	1179	if (ret < 0)
768		- i2c->speed_hz = I2C_DEFAULT_SPEED;
	1180	+ i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
769	1181
770	1182	ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
771	1183	if (ret < 0)
..	..	@@ -823,9 +1235,6 @@
823	1235	if (ret)
824	1236	return -EINVAL;
825	1237
826		- if (i2c->dev_comp->timing_adjust)
827		- i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
828		-
829	1238	if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
830	1239	return -EINVAL;
831	1240
..	..	@@ -840,6 +1249,10 @@
840	1249	dev_err(&pdev->dev, "cannot get dma clock\n");
841	1250	return PTR_ERR(i2c->clk_dma);
842	1251	}
	1252	+
	1253	+ i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
	1254	+ if (IS_ERR(i2c->clk_arb))
	1255	+ i2c->clk_arb = NULL;
843	1256
844	1257	clk = i2c->clk_main;
845	1258	if (i2c->have_pmic) {
..	..	@@ -859,8 +1272,9 @@
859	1272	return -EINVAL;
860	1273	}
861	1274
862		- if (i2c->dev_comp->support_33bits) {
863		- ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
	1275	+ if (i2c->dev_comp->max_dma_support > 32) {
	1276	+ ret = dma_set_mask(&pdev->dev,
	1277	+ DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
864	1278	if (ret) {
865	1279	dev_err(&pdev->dev, "dma_set_mask return error.\n");
866	1280	return ret;
..	..	@@ -876,7 +1290,8 @@
876	1290	mtk_i2c_clock_disable(i2c);
877	1291
878	1292	ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
879		- IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
	1293	+ IRQF_NO_SUSPEND \| IRQF_TRIGGER_NONE,
	1294	+ I2C_DRV_NAME, i2c);
880	1295	if (ret < 0) {
881	1296	dev_err(&pdev->dev,
882	1297	"Request I2C IRQ %d fail\n", irq);
..	..	@@ -903,7 +1318,16 @@
903	1318	}
904	1319
905	1320	#ifdef CONFIG_PM_SLEEP
906		-static int mtk_i2c_resume(struct device *dev)
	1321	+static int mtk_i2c_suspend_noirq(struct device *dev)
	1322	+{
	1323	+ struct mtk_i2c *i2c = dev_get_drvdata(dev);
	1324	+
	1325	+ i2c_mark_adapter_suspended(&i2c->adap);
	1326	+
	1327	+ return 0;
	1328	+}
	1329	+
	1330	+static int mtk_i2c_resume_noirq(struct device *dev)
907	1331	{
908	1332	int ret;
909	1333	struct mtk_i2c *i2c = dev_get_drvdata(dev);
..	..	@@ -918,12 +1342,15 @@
918	1342
919	1343	mtk_i2c_clock_disable(i2c);
920	1344
	1345	+ i2c_mark_adapter_resumed(&i2c->adap);
	1346	+
921	1347	return 0;
922	1348	}
923	1349	#endif
924	1350
925	1351	static const struct dev_pm_ops mtk_i2c_pm = {
926		- SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
	1352	+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
	1353	+ mtk_i2c_resume_noirq)
927	1354	};
928	1355
929	1356	static struct platform_driver mtk_i2c_driver = {