.. | .. |
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33 | 33 | baytrail, |
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34 | 34 | cherrytrail, |
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35 | 35 | haswell, |
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| 36 | + elkhartlake, |
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36 | 37 | }; |
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37 | 38 | |
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38 | 39 | struct dw_scl_sda_cfg { |
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.. | .. |
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45 | 46 | |
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46 | 47 | struct dw_pci_controller { |
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47 | 48 | u32 bus_num; |
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48 | | - u32 bus_cfg; |
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49 | | - u32 tx_fifo_depth; |
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50 | | - u32 rx_fifo_depth; |
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51 | | - u32 clk_khz; |
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52 | | - u32 functionality; |
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53 | 49 | u32 flags; |
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54 | 50 | struct dw_scl_sda_cfg *scl_sda_cfg; |
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55 | 51 | int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c); |
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| 52 | + u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev); |
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56 | 53 | }; |
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57 | | - |
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58 | | -#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \ |
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59 | | - DW_IC_CON_SLAVE_DISABLE | \ |
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60 | | - DW_IC_CON_RESTART_EN) |
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61 | 54 | |
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62 | 55 | /* Merrifield HCNT/LCNT/SDA hold time */ |
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63 | 56 | static struct dw_scl_sda_cfg mrfld_config = { |
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.. | .. |
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85 | 78 | .sda_hold = 0x9, |
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86 | 79 | }; |
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87 | 80 | |
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| 81 | +static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev) |
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| 82 | +{ |
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| 83 | + return 25000; |
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| 84 | +} |
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| 85 | + |
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88 | 86 | static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) |
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89 | 87 | { |
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| 88 | + struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev); |
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| 89 | + |
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90 | 90 | switch (pdev->device) { |
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91 | 91 | case 0x0817: |
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92 | | - c->bus_cfg &= ~DW_IC_CON_SPEED_MASK; |
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93 | | - c->bus_cfg |= DW_IC_CON_SPEED_STD; |
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94 | | - /* fall through */ |
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| 92 | + dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; |
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| 93 | + fallthrough; |
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95 | 94 | case 0x0818: |
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96 | 95 | case 0x0819: |
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97 | 96 | c->bus_num = pdev->device - 0x817 + 3; |
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.. | .. |
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108 | 107 | static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) |
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109 | 108 | { |
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110 | 109 | /* |
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111 | | - * On Intel Merrifield the user visible i2c busses are enumerated |
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| 110 | + * On Intel Merrifield the user visible i2c buses are enumerated |
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112 | 111 | * [1..7]. So, we add 1 to shift the default range. Besides that the |
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113 | 112 | * first PCI slot provides 4 functions, that's why we have to add 0 to |
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114 | 113 | * the first slot and 4 to the next one. |
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.. | .. |
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124 | 123 | return -ENODEV; |
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125 | 124 | } |
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126 | 125 | |
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| 126 | +static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev) |
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| 127 | +{ |
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| 128 | + return 100000; |
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| 129 | +} |
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| 130 | + |
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127 | 131 | static struct dw_pci_controller dw_pci_controllers[] = { |
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128 | 132 | [medfield] = { |
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129 | 133 | .bus_num = -1, |
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130 | | - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
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131 | | - .tx_fifo_depth = 32, |
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132 | | - .rx_fifo_depth = 32, |
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133 | | - .functionality = I2C_FUNC_10BIT_ADDR, |
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134 | | - .clk_khz = 25000, |
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135 | 134 | .setup = mfld_setup, |
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| 135 | + .get_clk_rate_khz = mfld_get_clk_rate_khz, |
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136 | 136 | }, |
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137 | 137 | [merrifield] = { |
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138 | 138 | .bus_num = -1, |
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139 | | - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
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140 | | - .tx_fifo_depth = 64, |
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141 | | - .rx_fifo_depth = 64, |
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142 | | - .functionality = I2C_FUNC_10BIT_ADDR, |
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143 | 139 | .scl_sda_cfg = &mrfld_config, |
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144 | 140 | .setup = mrfld_setup, |
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145 | 141 | }, |
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146 | 142 | [baytrail] = { |
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147 | 143 | .bus_num = -1, |
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148 | | - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
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149 | | - .tx_fifo_depth = 32, |
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150 | | - .rx_fifo_depth = 32, |
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151 | | - .functionality = I2C_FUNC_10BIT_ADDR, |
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152 | 144 | .scl_sda_cfg = &byt_config, |
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153 | 145 | }, |
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154 | 146 | [haswell] = { |
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155 | 147 | .bus_num = -1, |
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156 | | - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
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157 | | - .tx_fifo_depth = 32, |
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158 | | - .rx_fifo_depth = 32, |
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159 | | - .functionality = I2C_FUNC_10BIT_ADDR, |
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160 | 148 | .scl_sda_cfg = &hsw_config, |
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161 | 149 | }, |
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162 | 150 | [cherrytrail] = { |
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163 | 151 | .bus_num = -1, |
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164 | | - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, |
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165 | | - .tx_fifo_depth = 32, |
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166 | | - .rx_fifo_depth = 32, |
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167 | | - .functionality = I2C_FUNC_10BIT_ADDR, |
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168 | | - .flags = MODEL_CHERRYTRAIL, |
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169 | 152 | .scl_sda_cfg = &byt_config, |
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| 153 | + }, |
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| 154 | + [elkhartlake] = { |
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| 155 | + .bus_num = -1, |
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| 156 | + .get_clk_rate_khz = ehl_get_clk_rate_khz, |
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170 | 157 | }, |
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171 | 158 | }; |
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172 | 159 | |
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173 | 160 | #ifdef CONFIG_PM |
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174 | 161 | static int i2c_dw_pci_suspend(struct device *dev) |
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175 | 162 | { |
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176 | | - struct pci_dev *pdev = to_pci_dev(dev); |
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177 | | - struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); |
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| 163 | + struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); |
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178 | 164 | |
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| 165 | + i_dev->suspended = true; |
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179 | 166 | i_dev->disable(i_dev); |
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180 | 167 | |
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181 | 168 | return 0; |
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.. | .. |
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183 | 170 | |
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184 | 171 | static int i2c_dw_pci_resume(struct device *dev) |
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185 | 172 | { |
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186 | | - struct pci_dev *pdev = to_pci_dev(dev); |
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187 | | - struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); |
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| 173 | + struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); |
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| 174 | + int ret; |
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188 | 175 | |
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189 | | - return i_dev->init(i_dev); |
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| 176 | + ret = i_dev->init(i_dev); |
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| 177 | + i_dev->suspended = false; |
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| 178 | + |
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| 179 | + return ret; |
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190 | 180 | } |
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191 | 181 | #endif |
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192 | 182 | |
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193 | 183 | static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend, |
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194 | 184 | i2c_dw_pci_resume, NULL); |
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195 | | - |
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196 | | -static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev) |
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197 | | -{ |
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198 | | - return dev->controller->clk_khz; |
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199 | | -} |
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200 | 185 | |
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201 | 186 | static int i2c_dw_pci_probe(struct pci_dev *pdev, |
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202 | 187 | const struct pci_device_id *id) |
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.. | .. |
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222 | 207 | return r; |
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223 | 208 | } |
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224 | 209 | |
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| 210 | + pci_set_master(pdev); |
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| 211 | + |
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225 | 212 | r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); |
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226 | 213 | if (r) { |
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227 | 214 | dev_err(&pdev->dev, "I/O memory remapping failed\n"); |
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.. | .. |
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232 | 219 | if (!dev) |
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233 | 220 | return -ENOMEM; |
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234 | 221 | |
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235 | | - dev->clk = NULL; |
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236 | | - dev->controller = controller; |
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237 | | - dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; |
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| 222 | + r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
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| 223 | + if (r < 0) |
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| 224 | + return r; |
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| 225 | + |
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| 226 | + dev->get_clk_rate_khz = controller->get_clk_rate_khz; |
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| 227 | + dev->timings.bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; |
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238 | 228 | dev->base = pcim_iomap_table(pdev)[0]; |
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239 | 229 | dev->dev = &pdev->dev; |
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240 | | - dev->irq = pdev->irq; |
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| 230 | + dev->irq = pci_irq_vector(pdev, 0); |
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241 | 231 | dev->flags |= controller->flags; |
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| 232 | + |
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| 233 | + pci_set_drvdata(pdev, dev); |
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242 | 234 | |
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243 | 235 | if (controller->setup) { |
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244 | 236 | r = controller->setup(pdev, controller); |
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245 | | - if (r) |
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| 237 | + if (r) { |
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| 238 | + pci_free_irq_vectors(pdev); |
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246 | 239 | return r; |
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| 240 | + } |
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247 | 241 | } |
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248 | 242 | |
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249 | | - dev->functionality = controller->functionality | |
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250 | | - DW_IC_DEFAULT_FUNCTIONALITY; |
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| 243 | + i2c_dw_adjust_bus_speed(dev); |
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251 | 244 | |
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252 | | - dev->master_cfg = controller->bus_cfg; |
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| 245 | + if (has_acpi_companion(&pdev->dev)) |
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| 246 | + i2c_dw_acpi_configure(&pdev->dev); |
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| 247 | + |
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| 248 | + r = i2c_dw_validate_speed(dev); |
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| 249 | + if (r) { |
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| 250 | + pci_free_irq_vectors(pdev); |
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| 251 | + return r; |
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| 252 | + } |
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| 253 | + |
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| 254 | + i2c_dw_configure(dev); |
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| 255 | + |
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253 | 256 | if (controller->scl_sda_cfg) { |
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254 | 257 | cfg = controller->scl_sda_cfg; |
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255 | 258 | dev->ss_hcnt = cfg->ss_hcnt; |
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.. | .. |
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259 | 262 | dev->sda_hold_time = cfg->sda_hold; |
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260 | 263 | } |
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261 | 264 | |
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262 | | - pci_set_drvdata(pdev, dev); |
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263 | | - |
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264 | | - dev->tx_fifo_depth = controller->tx_fifo_depth; |
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265 | | - dev->rx_fifo_depth = controller->rx_fifo_depth; |
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266 | | - |
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267 | 265 | adap = &dev->adapter; |
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268 | 266 | adap->owner = THIS_MODULE; |
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269 | 267 | adap->class = 0; |
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.. | .. |
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271 | 269 | adap->nr = controller->bus_num; |
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272 | 270 | |
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273 | 271 | r = i2c_dw_probe(dev); |
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274 | | - if (r) |
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| 272 | + if (r) { |
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| 273 | + pci_free_irq_vectors(pdev); |
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275 | 274 | return r; |
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| 275 | + } |
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276 | 276 | |
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277 | 277 | pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); |
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278 | 278 | pm_runtime_use_autosuspend(&pdev->dev); |
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.. | .. |
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291 | 291 | pm_runtime_get_noresume(&pdev->dev); |
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292 | 292 | |
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293 | 293 | i2c_del_adapter(&dev->adapter); |
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| 294 | + devm_free_irq(&pdev->dev, dev->irq, dev); |
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| 295 | + pci_free_irq_vectors(pdev); |
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294 | 296 | } |
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295 | 297 | |
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296 | 298 | /* work with hotplug and coldplug */ |
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.. | .. |
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326 | 328 | { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail }, |
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327 | 329 | { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail }, |
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328 | 330 | { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail }, |
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| 331 | + /* Elkhart Lake (PSE I2C) */ |
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| 332 | + { PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake }, |
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| 333 | + { PCI_VDEVICE(INTEL, 0x4bba), elkhartlake }, |
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| 334 | + { PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake }, |
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| 335 | + { PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake }, |
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| 336 | + { PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake }, |
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| 337 | + { PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake }, |
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| 338 | + { PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake }, |
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| 339 | + { PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake }, |
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329 | 340 | { 0,} |
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330 | 341 | }; |
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331 | 342 | MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids); |
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