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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/i2c/busses/i2c-axxia.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * This driver implements I2C master functionality using the LSI API2C
34  * controller.
....@@ -5,13 +6,10 @@
56  * NOTE: The controller has a limitation in that it can only do transfers of
67  * maximum 255 bytes at a time. If a larger transfer is attempted, error code
78  * (-EINVAL) is returned.
8
- *
9
- * This software is licensed under the terms of the GNU General Public
10
- * License version 2, as published by the Free Software Foundation, and
11
- * may be copied, distributed, and modified under those terms.
129  */
1310 #include <linux/clk.h>
1411 #include <linux/clkdev.h>
12
+#include <linux/delay.h>
1513 #include <linux/err.h>
1614 #include <linux/i2c.h>
1715 #include <linux/init.h>
....@@ -25,6 +23,7 @@
2523 #define I2C_XFER_TIMEOUT    (msecs_to_jiffies(250))
2624 #define I2C_STOP_TIMEOUT    (msecs_to_jiffies(100))
2725 #define FIFO_SIZE           8
26
+#define SEQ_LEN             2
2827 
2928 #define GLOBAL_CONTROL		0x00
3029 #define   GLOBAL_MST_EN         BIT(0)
....@@ -51,6 +50,7 @@
5150 #define   CMD_BUSY		(1<<3)
5251 #define   CMD_MANUAL		(0x00 | CMD_BUSY)
5352 #define   CMD_AUTO		(0x01 | CMD_BUSY)
53
+#define   CMD_SEQUENCE		(0x02 | CMD_BUSY)
5454 #define MST_RX_XFER		0x2c
5555 #define MST_TX_XFER		0x30
5656 #define MST_ADDR_1		0x34
....@@ -77,6 +77,40 @@
7777 				 MST_STATUS_IP)
7878 #define MST_TX_BYTES_XFRD	0x50
7979 #define MST_RX_BYTES_XFRD	0x54
80
+#define SLV_ADDR_DEC_CTL	0x58
81
+#define   SLV_ADDR_DEC_GCE	BIT(0)  /* ACK to General Call Address from own master (loopback) */
82
+#define   SLV_ADDR_DEC_OGCE	BIT(1)  /* ACK to General Call Address from external masters */
83
+#define   SLV_ADDR_DEC_SA1E	BIT(2)  /* ACK to addr_1 enabled */
84
+#define   SLV_ADDR_DEC_SA1M	BIT(3)  /* 10-bit addressing for addr_1 enabled */
85
+#define   SLV_ADDR_DEC_SA2E	BIT(4)  /* ACK to addr_2 enabled */
86
+#define   SLV_ADDR_DEC_SA2M	BIT(5)  /* 10-bit addressing for addr_2 enabled */
87
+#define SLV_ADDR_1		0x5c
88
+#define SLV_ADDR_2		0x60
89
+#define SLV_RX_CTL		0x64
90
+#define   SLV_RX_ACSA1		BIT(0)  /* Generate ACK for writes to addr_1 */
91
+#define   SLV_RX_ACSA2		BIT(1)  /* Generate ACK for writes to addr_2 */
92
+#define   SLV_RX_ACGCA		BIT(2)  /* ACK data phase transfers to General Call Address */
93
+#define SLV_DATA		0x68
94
+#define SLV_RX_FIFO		0x6c
95
+#define   SLV_FIFO_DV1		BIT(0)  /* Data Valid for addr_1 */
96
+#define   SLV_FIFO_DV2		BIT(1)  /* Data Valid for addr_2 */
97
+#define   SLV_FIFO_AS		BIT(2)  /* (N)ACK Sent */
98
+#define   SLV_FIFO_TNAK		BIT(3)  /* Timeout NACK */
99
+#define   SLV_FIFO_STRC		BIT(4)  /* First byte after start condition received */
100
+#define   SLV_FIFO_RSC		BIT(5)  /* Repeated Start Condition */
101
+#define   SLV_FIFO_STPC		BIT(6)  /* Stop Condition */
102
+#define   SLV_FIFO_DV		(SLV_FIFO_DV1 | SLV_FIFO_DV2)
103
+#define SLV_INT_ENABLE		0x70
104
+#define SLV_INT_STATUS		0x74
105
+#define   SLV_STATUS_RFH	BIT(0)  /* FIFO service */
106
+#define   SLV_STATUS_WTC	BIT(1)  /* Write transfer complete */
107
+#define   SLV_STATUS_SRS1	BIT(2)  /* Slave read from addr 1 */
108
+#define   SLV_STATUS_SRRS1	BIT(3)  /* Repeated start from addr 1 */
109
+#define   SLV_STATUS_SRND1	BIT(4)  /* Read request not following start condition */
110
+#define   SLV_STATUS_SRC1	BIT(5)  /* Read canceled */
111
+#define   SLV_STATUS_SRAT1	BIT(6)  /* Slave Read timed out */
112
+#define   SLV_STATUS_SRDRE1	BIT(7)  /* Data written after timed out */
113
+#define SLV_READ_DUMMY		0x78
80114 #define SCL_HIGH_PERIOD		0x80
81115 #define SCL_LOW_PERIOD		0x84
82116 #define SPIKE_FLTR_LEN		0x88
....@@ -87,24 +121,32 @@
87121  * axxia_i2c_dev - I2C device context
88122  * @base: pointer to register struct
89123  * @msg: pointer to current message
90
- * @msg_xfrd: number of bytes transferred in msg
124
+ * @msg_r: pointer to current read message (sequence transfer)
125
+ * @msg_xfrd: number of bytes transferred in tx_fifo
126
+ * @msg_xfrd_r: number of bytes transferred in rx_fifo
91127  * @msg_err: error code for completed message
92128  * @msg_complete: xfer completion object
93129  * @dev: device reference
94130  * @adapter: core i2c abstraction
95131  * @i2c_clk: clock reference for i2c input clock
96132  * @bus_clk_rate: current i2c bus clock rate
133
+ * @last: a flag indicating is this is last message in transfer
97134  */
98135 struct axxia_i2c_dev {
99136 	void __iomem *base;
100137 	struct i2c_msg *msg;
138
+	struct i2c_msg *msg_r;
101139 	size_t msg_xfrd;
140
+	size_t msg_xfrd_r;
102141 	int msg_err;
103142 	struct completion msg_complete;
104143 	struct device *dev;
105144 	struct i2c_adapter adapter;
106145 	struct clk *i2c_clk;
107146 	u32 bus_clk_rate;
147
+	bool last;
148
+	struct i2c_client *slave;
149
+	int irq;
108150 };
109151 
110152 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
....@@ -157,7 +199,7 @@
157199 	/* Enable Master Mode */
158200 	writel(0x1, idev->base + GLOBAL_CONTROL);
159201 
160
-	if (idev->bus_clk_rate <= 100000) {
202
+	if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
161203 		/* Standard mode SCL 50/50, tSU:DAT = 250 ns */
162204 		t_high = divisor * 1 / 2;
163205 		t_low = divisor * 1 / 2;
....@@ -227,14 +269,14 @@
227269  */
228270 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
229271 {
230
-	struct i2c_msg *msg = idev->msg;
272
+	struct i2c_msg *msg = idev->msg_r;
231273 	size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
232
-	int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd);
274
+	int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
233275 
234276 	while (bytes_to_transfer-- > 0) {
235277 		int c = readl(idev->base + MST_DATA);
236278 
237
-		if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) {
279
+		if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
238280 			/*
239281 			 * Check length byte for SMBus block read
240282 			 */
....@@ -247,7 +289,7 @@
247289 			msg->len = 1 + c;
248290 			writel(msg->len, idev->base + MST_RX_XFER);
249291 		}
250
-		msg->buf[idev->msg_xfrd++] = c;
292
+		msg->buf[idev->msg_xfrd_r++] = c;
251293 	}
252294 
253295 	return 0;
....@@ -270,13 +312,65 @@
270312 	return ret;
271313 }
272314 
315
+static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
316
+{
317
+	u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
318
+	u8 val;
319
+
320
+	dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
321
+
322
+	if (fifo_status & SLV_FIFO_DV1) {
323
+		if (fifo_status & SLV_FIFO_STRC)
324
+			i2c_slave_event(idev->slave,
325
+					I2C_SLAVE_WRITE_REQUESTED, &val);
326
+
327
+		val = readl(idev->base + SLV_DATA);
328
+		i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
329
+	}
330
+	if (fifo_status & SLV_FIFO_STPC) {
331
+		readl(idev->base + SLV_DATA); /* dummy read */
332
+		i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
333
+	}
334
+	if (fifo_status & SLV_FIFO_RSC)
335
+		readl(idev->base + SLV_DATA); /* dummy read */
336
+}
337
+
338
+static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
339
+{
340
+	u32 status = readl(idev->base + SLV_INT_STATUS);
341
+	u8 val;
342
+
343
+	dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
344
+
345
+	if (status & SLV_STATUS_RFH)
346
+		axxia_i2c_slv_fifo_event(idev);
347
+	if (status & SLV_STATUS_SRS1) {
348
+		i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
349
+		writel(val, idev->base + SLV_DATA);
350
+	}
351
+	if (status & SLV_STATUS_SRND1) {
352
+		i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
353
+		writel(val, idev->base + SLV_DATA);
354
+	}
355
+	if (status & SLV_STATUS_SRC1)
356
+		i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
357
+
358
+	writel(INT_SLV, idev->base + INTERRUPT_STATUS);
359
+	return IRQ_HANDLED;
360
+}
361
+
273362 static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
274363 {
275364 	struct axxia_i2c_dev *idev = _dev;
365
+	irqreturn_t ret = IRQ_NONE;
276366 	u32 status;
277367 
278
-	if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))
279
-		return IRQ_NONE;
368
+	status = readl(idev->base + INTERRUPT_STATUS);
369
+
370
+	if (status & INT_SLV)
371
+		ret = axxia_i2c_slv_isr(idev);
372
+	if (!(status & INT_MST))
373
+		return ret;
280374 
281375 	/* Read interrupt status bits */
282376 	status = readl(idev->base + MST_INT_STATUS);
....@@ -287,7 +381,7 @@
287381 	}
288382 
289383 	/* RX FIFO needs service? */
290
-	if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL))
384
+	if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
291385 		axxia_i2c_empty_rx_fifo(idev);
292386 
293387 	/* TX FIFO needs service? */
....@@ -317,10 +411,12 @@
317411 		/* Stop completed */
318412 		i2c_int_disable(idev, ~MST_STATUS_TSS);
319413 		complete(&idev->msg_complete);
320
-	} else if (status & MST_STATUS_SNS) {
414
+	} else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
321415 		/* Transfer done */
322
-		i2c_int_disable(idev, ~MST_STATUS_TSS);
323
-		if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len)
416
+		int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
417
+
418
+		i2c_int_disable(idev, mask);
419
+		if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
324420 			axxia_i2c_empty_rx_fifo(idev);
325421 		complete(&idev->msg_complete);
326422 	} else if (status & MST_STATUS_TSS) {
....@@ -337,17 +433,9 @@
337433 	return IRQ_HANDLED;
338434 }
339435 
340
-static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
436
+static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
341437 {
342
-	u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
343
-	u32 rx_xfer, tx_xfer;
344438 	u32 addr_1, addr_2;
345
-	unsigned long time_left;
346
-	unsigned int wt_value;
347
-
348
-	idev->msg = msg;
349
-	idev->msg_xfrd = 0;
350
-	reinit_completion(&idev->msg_complete);
351439 
352440 	if (i2c_m_ten(msg)) {
353441 		/* 10-bit address
....@@ -367,6 +455,89 @@
367455 		addr_2 = 0;
368456 	}
369457 
458
+	writel(addr_1, idev->base + MST_ADDR_1);
459
+	writel(addr_2, idev->base + MST_ADDR_2);
460
+}
461
+
462
+/* The NAK interrupt will be sent _before_ issuing STOP command
463
+ * so the controller might still be busy processing it. No
464
+ * interrupt will be sent at the end so we have to poll for it
465
+ */
466
+static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
467
+{
468
+	unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
469
+
470
+	do {
471
+		if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
472
+			return 0;
473
+		usleep_range(1, 100);
474
+	} while (time_before(jiffies, timeout));
475
+
476
+	return -ETIMEDOUT;
477
+}
478
+
479
+static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
480
+{
481
+	u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
482
+	u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
483
+	unsigned long time_left;
484
+
485
+	axxia_i2c_set_addr(idev, &msgs[0]);
486
+
487
+	writel(msgs[0].len, idev->base + MST_TX_XFER);
488
+	writel(rlen, idev->base + MST_RX_XFER);
489
+
490
+	idev->msg = &msgs[0];
491
+	idev->msg_r = &msgs[1];
492
+	idev->msg_xfrd = 0;
493
+	idev->msg_xfrd_r = 0;
494
+	idev->last = true;
495
+	axxia_i2c_fill_tx_fifo(idev);
496
+
497
+	writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
498
+
499
+	reinit_completion(&idev->msg_complete);
500
+	i2c_int_enable(idev, int_mask);
501
+
502
+	time_left = wait_for_completion_timeout(&idev->msg_complete,
503
+						I2C_XFER_TIMEOUT);
504
+
505
+	if (idev->msg_err == -ENXIO) {
506
+		if (axxia_i2c_handle_seq_nak(idev))
507
+			axxia_i2c_init(idev);
508
+	} else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
509
+		dev_warn(idev->dev, "busy after xfer\n");
510
+	}
511
+
512
+	if (time_left == 0) {
513
+		idev->msg_err = -ETIMEDOUT;
514
+		i2c_recover_bus(&idev->adapter);
515
+		axxia_i2c_init(idev);
516
+	}
517
+
518
+	if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
519
+		axxia_i2c_init(idev);
520
+
521
+	return idev->msg_err;
522
+}
523
+
524
+static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
525
+			      bool last)
526
+{
527
+	u32 int_mask = MST_STATUS_ERR;
528
+	u32 rx_xfer, tx_xfer;
529
+	unsigned long time_left;
530
+	unsigned int wt_value;
531
+
532
+	idev->msg = msg;
533
+	idev->msg_r = msg;
534
+	idev->msg_xfrd = 0;
535
+	idev->msg_xfrd_r = 0;
536
+	idev->last = last;
537
+	reinit_completion(&idev->msg_complete);
538
+
539
+	axxia_i2c_set_addr(idev, msg);
540
+
370541 	if (i2c_m_rd(msg)) {
371542 		/* I2C read transfer */
372543 		rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
....@@ -379,8 +550,6 @@
379550 
380551 	writel(rx_xfer, idev->base + MST_RX_XFER);
381552 	writel(tx_xfer, idev->base + MST_TX_XFER);
382
-	writel(addr_1, idev->base + MST_ADDR_1);
383
-	writel(addr_2, idev->base + MST_ADDR_2);
384553 
385554 	if (i2c_m_rd(msg))
386555 		int_mask |= MST_STATUS_RFL;
....@@ -394,8 +563,13 @@
394563 	if (idev->msg_err)
395564 		goto out;
396565 
397
-	/* Start manual mode */
398
-	writel(CMD_MANUAL, idev->base + MST_COMMAND);
566
+	if (!last) {
567
+		writel(CMD_MANUAL, idev->base + MST_COMMAND);
568
+		int_mask |= MST_STATUS_SNS;
569
+	} else {
570
+		writel(CMD_AUTO, idev->base + MST_COMMAND);
571
+		int_mask |= MST_STATUS_SS;
572
+	}
399573 
400574 	writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
401575 
....@@ -423,26 +597,16 @@
423597 	return idev->msg_err;
424598 }
425599 
426
-static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
600
+/* This function checks if the msgs[] array contains messages compatible with
601
+ * Sequence mode of operation. This mode assumes there will be exactly one
602
+ * write of non-zero length followed by exactly one read of non-zero length,
603
+ * both targeted at the same client device.
604
+ */
605
+static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
427606 {
428
-	u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC | MST_STATUS_TSS;
429
-	unsigned long time_left;
430
-
431
-	reinit_completion(&idev->msg_complete);
432
-
433
-	/* Issue stop */
434
-	writel(0xb, idev->base + MST_COMMAND);
435
-	i2c_int_enable(idev, int_mask);
436
-	time_left = wait_for_completion_timeout(&idev->msg_complete,
437
-					      I2C_STOP_TIMEOUT);
438
-	i2c_int_disable(idev, int_mask);
439
-	if (time_left == 0)
440
-		return -ETIMEDOUT;
441
-
442
-	if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
443
-		dev_warn(idev->dev, "busy after stop\n");
444
-
445
-	return 0;
607
+	return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
608
+	       msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
609
+	       msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
446610 }
447611 
448612 static int
....@@ -453,12 +617,16 @@
453617 	int ret = 0;
454618 
455619 	idev->msg_err = 0;
620
+
621
+	if (axxia_i2c_sequence_ok(msgs, num)) {
622
+		ret = axxia_i2c_xfer_seq(idev, msgs);
623
+		return ret ? : SEQ_LEN;
624
+	}
625
+
456626 	i2c_int_enable(idev, MST_STATUS_TSS);
457627 
458628 	for (i = 0; ret == 0 && i < num; ++i)
459
-		ret = axxia_i2c_xfer_msg(idev, &msgs[i]);
460
-
461
-	axxia_i2c_stop(idev);
629
+		ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
462630 
463631 	return ret ? : i;
464632 }
....@@ -503,9 +671,58 @@
503671 	return caps;
504672 }
505673 
674
+static int axxia_i2c_reg_slave(struct i2c_client *slave)
675
+{
676
+	struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
677
+	u32 slv_int_mask = SLV_STATUS_RFH;
678
+	u32 dec_ctl;
679
+
680
+	if (idev->slave)
681
+		return -EBUSY;
682
+
683
+	idev->slave = slave;
684
+
685
+	/* Enable slave mode as well */
686
+	writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
687
+	writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
688
+
689
+	/* Set slave address */
690
+	dec_ctl = SLV_ADDR_DEC_SA1E;
691
+	if (slave->flags & I2C_CLIENT_TEN)
692
+		dec_ctl |= SLV_ADDR_DEC_SA1M;
693
+
694
+	writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
695
+	writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
696
+	writel(slave->addr, idev->base + SLV_ADDR_1);
697
+
698
+	/* Enable interrupts */
699
+	slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1;
700
+	slv_int_mask |= SLV_STATUS_SRC1;
701
+	writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
702
+
703
+	return 0;
704
+}
705
+
706
+static int axxia_i2c_unreg_slave(struct i2c_client *slave)
707
+{
708
+	struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
709
+
710
+	/* Disable slave mode */
711
+	writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
712
+	writel(INT_MST, idev->base + INTERRUPT_ENABLE);
713
+
714
+	synchronize_irq(idev->irq);
715
+
716
+	idev->slave = NULL;
717
+
718
+	return 0;
719
+}
720
+
506721 static const struct i2c_algorithm axxia_i2c_algo = {
507722 	.master_xfer = axxia_i2c_xfer,
508723 	.functionality = axxia_i2c_func,
724
+	.reg_slave = axxia_i2c_reg_slave,
725
+	.unreg_slave = axxia_i2c_unreg_slave,
509726 };
510727 
511728 static const struct i2c_adapter_quirks axxia_i2c_quirks = {
....@@ -517,25 +734,20 @@
517734 {
518735 	struct device_node *np = pdev->dev.of_node;
519736 	struct axxia_i2c_dev *idev = NULL;
520
-	struct resource *res;
521737 	void __iomem *base;
522
-	int irq;
523738 	int ret = 0;
524739 
525740 	idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
526741 	if (!idev)
527742 		return -ENOMEM;
528743 
529
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
530
-	base = devm_ioremap_resource(&pdev->dev, res);
744
+	base = devm_platform_ioremap_resource(pdev, 0);
531745 	if (IS_ERR(base))
532746 		return PTR_ERR(base);
533747 
534
-	irq = platform_get_irq(pdev, 0);
535
-	if (irq < 0) {
536
-		dev_err(&pdev->dev, "missing interrupt resource\n");
537
-		return irq;
538
-	}
748
+	idev->irq = platform_get_irq(pdev, 0);
749
+	if (idev->irq < 0)
750
+		return idev->irq;
539751 
540752 	idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
541753 	if (IS_ERR(idev->i2c_clk)) {
....@@ -549,7 +761,7 @@
549761 
550762 	of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
551763 	if (idev->bus_clk_rate == 0)
552
-		idev->bus_clk_rate = 100000;	/* default clock rate */
764
+		idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;	/* default clock rate */
553765 
554766 	ret = clk_prepare_enable(idev->i2c_clk);
555767 	if (ret) {
....@@ -563,10 +775,10 @@
563775 		goto error_disable_clk;
564776 	}
565777 
566
-	ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0,
778
+	ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
567779 			       pdev->name, idev);
568780 	if (ret) {
569
-		dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq);
781
+		dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
570782 		goto error_disable_clk;
571783 	}
572784