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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/i2c/busses/i2c-aspeed.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *  Aspeed 24XX/25XX I2C Controller.
34  *
45  *  Copyright (C) 2012-2017 ASPEED Technology Inc.
56  *  Copyright 2017 IBM Corporation
67  *  Copyright 2017 Google, Inc.
7
- *
8
- *  This program is free software; you can redistribute it and/or modify
9
- *  it under the terms of the GNU General Public License version 2 as
10
- *  published by the Free Software Foundation.
118  */
129 
1310 #include <linux/clk.h>
....@@ -72,6 +69,7 @@
7269  * These share bit definitions, so use the same values for the enable &
7370  * status bits.
7471  */
72
+#define ASPEED_I2CD_INTR_RECV_MASK			0xf000ffff
7573 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT			BIT(14)
7674 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE		BIT(13)
7775 #define ASPEED_I2CD_INTR_SLAVE_MATCH			BIT(7)
....@@ -82,6 +80,11 @@
8280 #define ASPEED_I2CD_INTR_RX_DONE			BIT(2)
8381 #define ASPEED_I2CD_INTR_TX_NAK				BIT(1)
8482 #define ASPEED_I2CD_INTR_TX_ACK				BIT(0)
83
+#define ASPEED_I2CD_INTR_MASTER_ERRORS					       \
84
+		(ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |			       \
85
+		 ASPEED_I2CD_INTR_SCL_TIMEOUT |				       \
86
+		 ASPEED_I2CD_INTR_ABNORMAL |				       \
87
+		 ASPEED_I2CD_INTR_ARBIT_LOSS)
8588 #define ASPEED_I2CD_INTR_ALL						       \
8689 		(ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |			       \
8790 		 ASPEED_I2CD_INTR_BUS_RECOVER_DONE |			       \
....@@ -106,12 +109,19 @@
106109 #define ASPEED_I2CD_S_TX_CMD				BIT(2)
107110 #define ASPEED_I2CD_M_TX_CMD				BIT(1)
108111 #define ASPEED_I2CD_M_START_CMD				BIT(0)
112
+#define ASPEED_I2CD_MASTER_CMDS_MASK					       \
113
+		(ASPEED_I2CD_M_STOP_CMD |				       \
114
+		 ASPEED_I2CD_M_S_RX_CMD_LAST |				       \
115
+		 ASPEED_I2CD_M_RX_CMD |					       \
116
+		 ASPEED_I2CD_M_TX_CMD |					       \
117
+		 ASPEED_I2CD_M_START_CMD)
109118 
110119 /* 0x18 : I2CD Slave Device Address Register   */
111120 #define ASPEED_I2CD_DEV_ADDR_MASK			GENMASK(6, 0)
112121 
113122 enum aspeed_i2c_master_state {
114123 	ASPEED_I2C_MASTER_INACTIVE,
124
+	ASPEED_I2C_MASTER_PENDING,
115125 	ASPEED_I2C_MASTER_START,
116126 	ASPEED_I2C_MASTER_TX_FIRST,
117127 	ASPEED_I2C_MASTER_TX,
....@@ -121,12 +131,13 @@
121131 };
122132 
123133 enum aspeed_i2c_slave_state {
124
-	ASPEED_I2C_SLAVE_STOP,
134
+	ASPEED_I2C_SLAVE_INACTIVE,
125135 	ASPEED_I2C_SLAVE_START,
126136 	ASPEED_I2C_SLAVE_READ_REQUESTED,
127137 	ASPEED_I2C_SLAVE_READ_PROCESSED,
128138 	ASPEED_I2C_SLAVE_WRITE_REQUESTED,
129139 	ASPEED_I2C_SLAVE_WRITE_RECEIVED,
140
+	ASPEED_I2C_SLAVE_STOP,
130141 };
131142 
132143 struct aspeed_i2c_bus {
....@@ -151,6 +162,8 @@
151162 	int				cmd_err;
152163 	/* Protected only by i2c_lock_bus */
153164 	int				master_xfer_result;
165
+	/* Multi-master */
166
+	bool				multi_master;
154167 #if IS_ENABLED(CONFIG_I2C_SLAVE)
155168 	struct i2c_client		*slave;
156169 	enum aspeed_i2c_slave_state	slave_state;
....@@ -228,32 +241,26 @@
228241 }
229242 
230243 #if IS_ENABLED(CONFIG_I2C_SLAVE)
231
-static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus)
244
+static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
232245 {
233
-	u32 command, irq_status, status_ack = 0;
246
+	u32 command, irq_handled = 0;
234247 	struct i2c_client *slave = bus->slave;
235
-	bool irq_handled = true;
236248 	u8 value;
237249 
238
-	if (!slave) {
239
-		irq_handled = false;
240
-		goto out;
241
-	}
250
+	if (!slave)
251
+		return 0;
242252 
243253 	command = readl(bus->base + ASPEED_I2C_CMD_REG);
244
-	irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
245254 
246255 	/* Slave was requested, restart state machine. */
247256 	if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
248
-		status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH;
257
+		irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
249258 		bus->slave_state = ASPEED_I2C_SLAVE_START;
250259 	}
251260 
252261 	/* Slave is not currently active, irq was for someone else. */
253
-	if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
254
-		irq_handled = false;
255
-		goto out;
256
-	}
262
+	if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
263
+		return irq_handled;
257264 
258265 	dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
259266 		irq_status, command);
....@@ -270,34 +277,36 @@
270277 				bus->slave_state =
271278 						ASPEED_I2C_SLAVE_WRITE_REQUESTED;
272279 		}
273
-		status_ack |= ASPEED_I2CD_INTR_RX_DONE;
280
+		irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
274281 	}
275282 
276283 	/* Slave was asked to stop. */
277284 	if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
278
-		status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
285
+		irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
279286 		bus->slave_state = ASPEED_I2C_SLAVE_STOP;
280287 	}
281
-	if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
282
-		status_ack |= ASPEED_I2CD_INTR_TX_NAK;
288
+	if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
289
+	    bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
290
+		irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
283291 		bus->slave_state = ASPEED_I2C_SLAVE_STOP;
284292 	}
285293 
286294 	switch (bus->slave_state) {
287295 	case ASPEED_I2C_SLAVE_READ_REQUESTED:
288
-		if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
296
+		if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
289297 			dev_err(bus->dev, "Unexpected ACK on read request.\n");
290298 		bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
291
-
292299 		i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
293300 		writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
294301 		writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
295302 		break;
296303 	case ASPEED_I2C_SLAVE_READ_PROCESSED:
297
-		status_ack |= ASPEED_I2CD_INTR_TX_ACK;
298
-		if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
304
+		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
299305 			dev_err(bus->dev,
300306 				"Expected ACK after processed read.\n");
307
+			break;
308
+		}
309
+		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
301310 		i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
302311 		writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
303312 		writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
....@@ -311,20 +320,18 @@
311320 		break;
312321 	case ASPEED_I2C_SLAVE_STOP:
313322 		i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
323
+		bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
324
+		break;
325
+	case ASPEED_I2C_SLAVE_START:
326
+		/* Slave was just started. Waiting for the next event. */;
314327 		break;
315328 	default:
316
-		dev_err(bus->dev, "unhandled slave_state: %d\n",
329
+		dev_err(bus->dev, "unknown slave_state: %d\n",
317330 			bus->slave_state);
331
+		bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
318332 		break;
319333 	}
320334 
321
-	if (status_ack != irq_status)
322
-		dev_err(bus->dev,
323
-			"irq handled != irq. expected %x, but was %x\n",
324
-			irq_status, status_ack);
325
-	writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG);
326
-
327
-out:
328335 	return irq_handled;
329336 }
330337 #endif /* CONFIG_I2C_SLAVE */
....@@ -335,6 +342,18 @@
335342 	u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
336343 	struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
337344 	u8 slave_addr = i2c_8bit_addr_from_msg(msg);
345
+
346
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
347
+	/*
348
+	 * If it's requested in the middle of a slave session, set the master
349
+	 * state to 'pending' then H/W will continue handling this master
350
+	 * command when the bus comes back to the idle state.
351
+	 */
352
+	if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {
353
+		bus->master_state = ASPEED_I2C_MASTER_PENDING;
354
+		return;
355
+	}
356
+#endif /* CONFIG_I2C_SLAVE */
338357 
339358 	bus->master_state = ASPEED_I2C_MASTER_START;
340359 	bus->buf_index = 0;
....@@ -381,20 +400,16 @@
381400 	return 0;
382401 }
383402 
384
-static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
403
+static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
385404 {
386
-	u32 irq_status, status_ack = 0, command = 0;
405
+	u32 irq_handled = 0, command = 0;
387406 	struct i2c_msg *msg;
388407 	u8 recv_byte;
389408 	int ret;
390409 
391
-	irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
392
-	/* Ack all interrupt bits. */
393
-	writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG);
394
-
395410 	if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
396411 		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
397
-		status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
412
+		irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
398413 		goto out_complete;
399414 	}
400415 
....@@ -404,19 +419,29 @@
404419 	 * INACTIVE state.
405420 	 */
406421 	ret = aspeed_i2c_is_irq_error(irq_status);
407
-	if (ret < 0) {
422
+	if (ret) {
408423 		dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
409424 			irq_status);
410
-		bus->cmd_err = ret;
411
-		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
412
-		goto out_complete;
425
+		irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
426
+		if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
427
+			bus->cmd_err = ret;
428
+			bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
429
+			goto out_complete;
430
+		}
413431 	}
432
+
433
+	/* Master is not currently active, irq was for someone else. */
434
+	if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
435
+	    bus->master_state == ASPEED_I2C_MASTER_PENDING)
436
+		goto out_no_complete;
414437 
415438 	/* We are in an invalid state; reset bus to a known state. */
416439 	if (!bus->msgs) {
417
-		dev_err(bus->dev, "bus in unknown state\n");
440
+		dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
441
+			irq_status);
418442 		bus->cmd_err = -EIO;
419
-		if (bus->master_state != ASPEED_I2C_MASTER_STOP)
443
+		if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
444
+		    bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
420445 			aspeed_i2c_do_stop(bus);
421446 		goto out_no_complete;
422447 	}
....@@ -428,14 +453,37 @@
428453 	 * then update the state and handle the new state below.
429454 	 */
430455 	if (bus->master_state == ASPEED_I2C_MASTER_START) {
456
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
457
+		/*
458
+		 * If a peer master starts a xfer immediately after it queues a
459
+		 * master command, clear the queued master command and change
460
+		 * its state to 'pending'. To simplify handling of pending
461
+		 * cases, it uses S/W solution instead of H/W command queue
462
+		 * handling.
463
+		 */
464
+		if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
465
+			writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
466
+				~ASPEED_I2CD_MASTER_CMDS_MASK,
467
+			       bus->base + ASPEED_I2C_CMD_REG);
468
+			bus->master_state = ASPEED_I2C_MASTER_PENDING;
469
+			dev_dbg(bus->dev,
470
+				"master goes pending due to a slave start\n");
471
+			goto out_no_complete;
472
+		}
473
+#endif /* CONFIG_I2C_SLAVE */
431474 		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
475
+			if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
476
+				bus->cmd_err = -ENXIO;
477
+				bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
478
+				goto out_complete;
479
+			}
432480 			pr_devel("no slave present at %02x\n", msg->addr);
433
-			status_ack |= ASPEED_I2CD_INTR_TX_NAK;
481
+			irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
434482 			bus->cmd_err = -ENXIO;
435483 			aspeed_i2c_do_stop(bus);
436484 			goto out_no_complete;
437485 		}
438
-		status_ack |= ASPEED_I2CD_INTR_TX_ACK;
486
+		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
439487 		if (msg->len == 0) { /* SMBUS_QUICK */
440488 			aspeed_i2c_do_stop(bus);
441489 			goto out_no_complete;
....@@ -450,14 +498,14 @@
450498 	case ASPEED_I2C_MASTER_TX:
451499 		if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
452500 			dev_dbg(bus->dev, "slave NACKed TX\n");
453
-			status_ack |= ASPEED_I2CD_INTR_TX_NAK;
501
+			irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
454502 			goto error_and_stop;
455503 		} else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
456504 			dev_err(bus->dev, "slave failed to ACK TX\n");
457505 			goto error_and_stop;
458506 		}
459
-		status_ack |= ASPEED_I2CD_INTR_TX_ACK;
460
-		/* fallthrough intended */
507
+		irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
508
+		fallthrough;
461509 	case ASPEED_I2C_MASTER_TX_FIRST:
462510 		if (bus->buf_index < msg->len) {
463511 			bus->master_state = ASPEED_I2C_MASTER_TX;
....@@ -473,13 +521,13 @@
473521 		/* RX may not have completed yet (only address cycle) */
474522 		if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
475523 			goto out_no_complete;
476
-		/* fallthrough intended */
524
+		fallthrough;
477525 	case ASPEED_I2C_MASTER_RX:
478526 		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
479527 			dev_err(bus->dev, "master failed to RX\n");
480528 			goto error_and_stop;
481529 		}
482
-		status_ack |= ASPEED_I2CD_INTR_RX_DONE;
530
+		irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
483531 
484532 		recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
485533 		msg->buf[bus->buf_index++] = recv_byte;
....@@ -507,11 +555,13 @@
507555 		goto out_no_complete;
508556 	case ASPEED_I2C_MASTER_STOP:
509557 		if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
510
-			dev_err(bus->dev, "master failed to STOP\n");
558
+			dev_err(bus->dev,
559
+				"master failed to STOP. irq_status:0x%x\n",
560
+				irq_status);
511561 			bus->cmd_err = -EIO;
512562 			/* Do not STOP as we have already tried. */
513563 		} else {
514
-			status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP;
564
+			irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
515565 		}
516566 
517567 		bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
....@@ -541,35 +591,70 @@
541591 		bus->master_xfer_result = bus->msgs_index + 1;
542592 	complete(&bus->cmd_complete);
543593 out_no_complete:
544
-	if (irq_status != status_ack)
545
-		dev_err(bus->dev,
546
-			"irq handled != irq. expected 0x%08x, but was 0x%08x\n",
547
-			irq_status, status_ack);
548
-	return !!irq_status;
594
+	return irq_handled;
549595 }
550596 
551597 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
552598 {
553599 	struct aspeed_i2c_bus *bus = dev_id;
554
-	bool ret;
600
+	u32 irq_received, irq_remaining, irq_handled;
555601 
556602 	spin_lock(&bus->lock);
603
+	irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
604
+	/* Ack all interrupts except for Rx done */
605
+	writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
606
+	       bus->base + ASPEED_I2C_INTR_STS_REG);
607
+	readl(bus->base + ASPEED_I2C_INTR_STS_REG);
608
+	irq_received &= ASPEED_I2CD_INTR_RECV_MASK;
609
+	irq_remaining = irq_received;
557610 
558611 #if IS_ENABLED(CONFIG_I2C_SLAVE)
559
-	if (IS_ENABLED(CONFIG_I2C_SLAVE) && aspeed_i2c_slave_irq(bus)) {
560
-		dev_dbg(bus->dev, "irq handled by slave.\n");
561
-		ret = true;
562
-		goto out;
612
+	/*
613
+	 * In most cases, interrupt bits will be set one by one, although
614
+	 * multiple interrupt bits could be set at the same time. It's also
615
+	 * possible that master interrupt bits could be set along with slave
616
+	 * interrupt bits. Each case needs to be handled using corresponding
617
+	 * handlers depending on the current state.
618
+	 */
619
+	if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
620
+	    bus->master_state != ASPEED_I2C_MASTER_PENDING) {
621
+		irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
622
+		irq_remaining &= ~irq_handled;
623
+		if (irq_remaining)
624
+			irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
625
+	} else {
626
+		irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
627
+		irq_remaining &= ~irq_handled;
628
+		if (irq_remaining)
629
+			irq_handled |= aspeed_i2c_master_irq(bus,
630
+							     irq_remaining);
563631 	}
632
+
633
+	/*
634
+	 * Start a pending master command at here if a slave operation is
635
+	 * completed.
636
+	 */
637
+	if (bus->master_state == ASPEED_I2C_MASTER_PENDING &&
638
+	    bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
639
+		aspeed_i2c_do_start(bus);
640
+#else
641
+	irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
564642 #endif /* CONFIG_I2C_SLAVE */
565643 
566
-	ret = aspeed_i2c_master_irq(bus);
644
+	irq_remaining &= ~irq_handled;
645
+	if (irq_remaining)
646
+		dev_err(bus->dev,
647
+			"irq handled != irq. expected 0x%08x, but was 0x%08x\n",
648
+			irq_received, irq_handled);
567649 
568
-#if IS_ENABLED(CONFIG_I2C_SLAVE)
569
-out:
570
-#endif
650
+	/* Ack Rx done */
651
+	if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
652
+		writel(ASPEED_I2CD_INTR_RX_DONE,
653
+		       bus->base + ASPEED_I2C_INTR_STS_REG);
654
+		readl(bus->base + ASPEED_I2C_INTR_STS_REG);
655
+	}
571656 	spin_unlock(&bus->lock);
572
-	return ret ? IRQ_HANDLED : IRQ_NONE;
657
+	return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
573658 }
574659 
575660 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
....@@ -577,15 +662,16 @@
577662 {
578663 	struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
579664 	unsigned long time_left, flags;
580
-	int ret = 0;
581665 
582666 	spin_lock_irqsave(&bus->lock, flags);
583667 	bus->cmd_err = 0;
584668 
585
-	/* If bus is busy, attempt recovery. We assume a single master
586
-	 * environment.
587
-	 */
588
-	if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
669
+	/* If bus is busy in a single master environment, attempt recovery. */
670
+	if (!bus->multi_master &&
671
+	    (readl(bus->base + ASPEED_I2C_CMD_REG) &
672
+	     ASPEED_I2CD_BUS_BUSY_STS)) {
673
+		int ret;
674
+
589675 		spin_unlock_irqrestore(&bus->lock, flags);
590676 		ret = aspeed_i2c_recover_bus(bus);
591677 		if (ret)
....@@ -605,10 +691,32 @@
605691 	time_left = wait_for_completion_timeout(&bus->cmd_complete,
606692 						bus->adap.timeout);
607693 
608
-	if (time_left == 0)
694
+	if (time_left == 0) {
695
+		/*
696
+		 * In a multi-master setup, if a timeout occurs, attempt
697
+		 * recovery. But if the bus is idle, we still need to reset the
698
+		 * i2c controller to clear the remaining interrupts.
699
+		 */
700
+		if (bus->multi_master &&
701
+		    (readl(bus->base + ASPEED_I2C_CMD_REG) &
702
+		     ASPEED_I2CD_BUS_BUSY_STS))
703
+			aspeed_i2c_recover_bus(bus);
704
+		else
705
+			aspeed_i2c_reset(bus);
706
+
707
+		/*
708
+		 * If timed out and the state is still pending, drop the pending
709
+		 * master command.
710
+		 */
711
+		spin_lock_irqsave(&bus->lock, flags);
712
+		if (bus->master_state == ASPEED_I2C_MASTER_PENDING)
713
+			bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
714
+		spin_unlock_irqrestore(&bus->lock, flags);
715
+
609716 		return -ETIMEDOUT;
610
-	else
611
-		return bus->master_xfer_result;
717
+	}
718
+
719
+	return bus->master_xfer_result;
612720 }
613721 
614722 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
....@@ -648,7 +756,7 @@
648756 	__aspeed_i2c_reg_slave(bus, client->addr);
649757 
650758 	bus->slave = client;
651
-	bus->slave_state = ASPEED_I2C_SLAVE_STOP;
759
+	bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
652760 	spin_unlock_irqrestore(&bus->lock, flags);
653761 
654762 	return 0;
....@@ -803,7 +911,9 @@
803911 	if (ret < 0)
804912 		return ret;
805913 
806
-	if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
914
+	if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
915
+		bus->multi_master = true;
916
+	else
807917 		fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
808918 
809919 	/* Enable Master Mode */
....@@ -850,6 +960,10 @@
850960 		.compatible = "aspeed,ast2500-i2c-bus",
851961 		.data = aspeed_i2c_25xx_get_clk_reg_val,
852962 	},
963
+	{
964
+		.compatible = "aspeed,ast2600-i2c-bus",
965
+		.data = aspeed_i2c_25xx_get_clk_reg_val,
966
+	},
853967 	{ },
854968 };
855969 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
....@@ -891,7 +1005,7 @@
8911005 	if (ret < 0) {
8921006 		dev_err(&pdev->dev,
8931007 			"Could not read bus-frequency property\n");
894
-		bus->bus_frequency = 100000;
1008
+		bus->bus_frequency = I2C_MAX_STANDARD_MODE_FREQ;
8951009 	}
8961010 
8971011 	match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
....@@ -906,7 +1020,6 @@
9061020 	init_completion(&bus->cmd_complete);
9071021 	bus->adap.owner = THIS_MODULE;
9081022 	bus->adap.retries = 0;
909
-	bus->adap.timeout = 5 * HZ;
9101023 	bus->adap.algo = &aspeed_i2c_algo;
9111024 	bus->adap.dev.parent = &pdev->dev;
9121025 	bus->adap.dev.of_node = pdev->dev.of_node;