forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/gpu/drm/i915/gvt/mmio_context.c
....@@ -34,122 +34,113 @@
3434  */
3535 
3636 #include "i915_drv.h"
37
+#include "gt/intel_context.h"
38
+#include "gt/intel_ring.h"
3739 #include "gvt.h"
3840 #include "trace.h"
39
-
40
-/**
41
- * Defined in Intel Open Source PRM.
42
- * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
43
- */
44
-#define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i)*4)
45
-#define TRNULLDETCT		_MMIO(0x4de8)
46
-#define TRINVTILEDETCT		_MMIO(0x4dec)
47
-#define TRVADR			_MMIO(0x4df0)
48
-#define TRTTE			_MMIO(0x4df4)
49
-#define RING_EXCC(base)		_MMIO((base) + 0x28)
50
-#define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
51
-#define VF_GUARDBAND		_MMIO(0x83a4)
5241 
5342 #define GEN9_MOCS_SIZE		64
5443 
5544 /* Raw offset is appened to each line for convenience. */
5645 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
57
-	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
58
-	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
59
-	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
60
-	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
61
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
62
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
63
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
64
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
65
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
66
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
67
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
68
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
69
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
70
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
71
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
72
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
73
-	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
74
-	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
75
-	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
76
-	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
77
-	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
78
-	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
46
+	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
47
+	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
48
+	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
49
+	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
50
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
51
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
52
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
53
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
54
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
55
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
56
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
57
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
58
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
59
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
60
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
61
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
62
+	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
63
+	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
64
+	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
65
+	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
66
+	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
67
+	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
7968 
80
-	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
81
-	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
82
-	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
83
-	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
84
-	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
85
-	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
69
+	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
70
+	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
71
+	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
72
+	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
73
+	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
74
+	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
8675 };
8776 
8877 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
89
-	{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
90
-	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
91
-	{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
92
-	{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
93
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
94
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
95
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
96
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
97
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
98
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
99
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
100
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
101
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
102
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
103
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
104
-	{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
105
-	{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
106
-	{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
107
-	{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
108
-	{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
109
-	{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
110
-	{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
78
+	{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
79
+	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
80
+	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
81
+	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
82
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
83
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
84
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
85
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
86
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
87
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
88
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
89
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
90
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
91
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
92
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
93
+	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
94
+	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
95
+	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
96
+	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
97
+	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
98
+	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
99
+	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
111100 
112
-	{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
113
-	{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
114
-	{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
115
-	{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
116
-	{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
117
-	{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
118
-	{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
119
-	{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
120
-	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
121
-	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
122
-	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
123
-	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
124
-	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
125
-	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
126
-	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
127
-	{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
128
-	{RCS, TRVADR, 0, false}, /* 0x4df0 */
129
-	{RCS, TRTTE, 0, false}, /* 0x4df4 */
101
+	{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
102
+	{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
103
+	{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
104
+	{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
105
+	{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
106
+	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
107
+	{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
108
+	{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
109
+	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
110
+	{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
111
+	{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
112
+	{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
113
+	{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
114
+	{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
115
+	{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
116
+	{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
117
+	{RCS0, TRVADR, 0, true}, /* 0x4df0 */
118
+	{RCS0, TRTTE, 0, true}, /* 0x4df4 */
119
+	{RCS0, _MMIO(0x4dfc), 0, true},
130120 
131
-	{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
132
-	{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
133
-	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
134
-	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
135
-	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
121
+	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
122
+	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
123
+	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
124
+	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
125
+	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
136126 
137
-	{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
127
+	{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
138128 
139
-	{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
129
+	{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
140130 
141
-	{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
142
-	{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
143
-	{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
144
-	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
131
+	{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
132
+	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
133
+	{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
134
+	{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
145135 
146
-	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
147
-	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
136
+	{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
137
+	{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
138
+	{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
148139 
149
-	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
150
-	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
151
-	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
152
-	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
140
+	{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
141
+	{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
142
+	{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
143
+	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
153144 };
154145 
155146 static struct {
....@@ -158,23 +149,35 @@
158149 	u32 l3cc_table[GEN9_MOCS_SIZE / 2];
159150 } gen9_render_mocs;
160151 
161
-static void load_render_mocs(struct drm_i915_private *dev_priv)
152
+static u32 gen9_mocs_mmio_offset_list[] = {
153
+	[RCS0]  = 0xc800,
154
+	[VCS0]  = 0xc900,
155
+	[VCS1]  = 0xca00,
156
+	[BCS0]  = 0xcc00,
157
+	[VECS0] = 0xcb00,
158
+};
159
+
160
+static void load_render_mocs(const struct intel_engine_cs *engine)
162161 {
162
+	struct intel_gvt *gvt = engine->i915->gvt;
163
+	struct intel_uncore *uncore = engine->uncore;
164
+	u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;
165
+	u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;
163166 	i915_reg_t offset;
164
-	u32 regs[] = {
165
-		[RCS] = 0xc800,
166
-		[VCS] = 0xc900,
167
-		[VCS2] = 0xca00,
168
-		[BCS] = 0xcc00,
169
-		[VECS] = 0xcb00,
170
-	};
171167 	int ring_id, i;
172168 
173
-	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
169
+	/* Platform doesn't have mocs mmios. */
170
+	if (!regs)
171
+		return;
172
+
173
+	for (ring_id = 0; ring_id < cnt; ring_id++) {
174
+		if (!HAS_ENGINE(engine->gt, ring_id))
175
+			continue;
176
+
174177 		offset.reg = regs[ring_id];
175178 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
176179 			gen9_render_mocs.control_table[ring_id][i] =
177
-				I915_READ_FW(offset);
180
+				intel_uncore_read_fw(uncore, offset);
178181 			offset.reg += 4;
179182 		}
180183 	}
....@@ -182,7 +185,7 @@
182185 	offset.reg = 0xb020;
183186 	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
184187 		gen9_render_mocs.l3cc_table[i] =
185
-			I915_READ_FW(offset);
188
+			intel_uncore_read_fw(uncore, offset);
186189 		offset.reg += 4;
187190 	}
188191 	gen9_render_mocs.initialized = true;
....@@ -213,13 +216,11 @@
213216 	*cs++ = MI_LOAD_REGISTER_IMM(count);
214217 	for (mmio = gvt->engine_mmio_list.mmio;
215218 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
216
-		if (mmio->ring_id != ring_id ||
217
-		    !mmio->in_context)
219
+		if (mmio->id != ring_id || !mmio->in_context)
218220 			continue;
219221 
220222 		*cs++ = i915_mmio_reg_offset(mmio->reg);
221
-		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
222
-				(mmio->mask << 16);
223
+		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);
223224 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
224225 			      *(cs-2), *(cs-1), vgpu->id, ring_id);
225226 	}
....@@ -312,7 +313,7 @@
312313 		goto out;
313314 
314315 	/* no MOCS register in context except render engine */
315
-	if (req->engine->id != RCS)
316
+	if (req->engine->id != RCS0)
316317 		goto out;
317318 
318319 	ret = restore_render_mocs_control_for_inhibit(vgpu, req);
....@@ -335,97 +336,102 @@
335336 	return ret;
336337 }
337338 
338
-static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
339
+static u32 gen8_tlb_mmio_offset_list[] = {
340
+	[RCS0]  = 0x4260,
341
+	[VCS0]  = 0x4264,
342
+	[VCS1]  = 0x4268,
343
+	[BCS0]  = 0x426c,
344
+	[VECS0] = 0x4270,
345
+};
346
+
347
+static void handle_tlb_pending_event(struct intel_vgpu *vgpu,
348
+				     const struct intel_engine_cs *engine)
339349 {
340
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
350
+	struct intel_uncore *uncore = engine->uncore;
341351 	struct intel_vgpu_submission *s = &vgpu->submission;
352
+	u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;
353
+	u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;
342354 	enum forcewake_domains fw;
343355 	i915_reg_t reg;
344
-	u32 regs[] = {
345
-		[RCS] = 0x4260,
346
-		[VCS] = 0x4264,
347
-		[VCS2] = 0x4268,
348
-		[BCS] = 0x426c,
349
-		[VECS] = 0x4270,
350
-	};
351356 
352
-	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
357
+	if (!regs)
353358 		return;
354359 
355
-	if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
360
+	if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt))
356361 		return;
357362 
358
-	reg = _MMIO(regs[ring_id]);
363
+	if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending))
364
+		return;
365
+
366
+	reg = _MMIO(regs[engine->id]);
359367 
360368 	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
361369 	 * we need to put a forcewake when invalidating RCS TLB caches,
362370 	 * otherwise device can go to RC6 state and interrupt invalidation
363371 	 * process
364372 	 */
365
-	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
373
+	fw = intel_uncore_forcewake_for_reg(uncore, reg,
366374 					    FW_REG_READ | FW_REG_WRITE);
367
-	if (ring_id == RCS && (IS_SKYLAKE(dev_priv) ||
368
-			IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)))
375
+	if (engine->id == RCS0 && INTEL_GEN(engine->i915) >= 9)
369376 		fw |= FORCEWAKE_RENDER;
370377 
371
-	intel_uncore_forcewake_get(dev_priv, fw);
378
+	intel_uncore_forcewake_get(uncore, fw);
372379 
373
-	I915_WRITE_FW(reg, 0x1);
380
+	intel_uncore_write_fw(uncore, reg, 0x1);
374381 
375
-	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
376
-		gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
382
+	if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50))
383
+		gvt_vgpu_err("timeout in invalidate ring %s tlb\n",
384
+			     engine->name);
377385 	else
378386 		vgpu_vreg_t(vgpu, reg) = 0;
379387 
380
-	intel_uncore_forcewake_put(dev_priv, fw);
388
+	intel_uncore_forcewake_put(uncore, fw);
381389 
382
-	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
390
+	gvt_dbg_core("invalidate TLB for ring %s\n", engine->name);
383391 }
384392 
385393 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
386
-			int ring_id)
394
+			const struct intel_engine_cs *engine)
387395 {
388
-	struct drm_i915_private *dev_priv;
396
+	u32 regs[] = {
397
+		[RCS0]  = 0xc800,
398
+		[VCS0]  = 0xc900,
399
+		[VCS1]  = 0xca00,
400
+		[BCS0]  = 0xcc00,
401
+		[VECS0] = 0xcb00,
402
+	};
403
+	struct intel_uncore *uncore = engine->uncore;
389404 	i915_reg_t offset, l3_offset;
390405 	u32 old_v, new_v;
391
-
392
-	u32 regs[] = {
393
-		[RCS] = 0xc800,
394
-		[VCS] = 0xc900,
395
-		[VCS2] = 0xca00,
396
-		[BCS] = 0xcc00,
397
-		[VECS] = 0xcb00,
398
-	};
399406 	int i;
400407 
401
-	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
402
-	if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
408
+	if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs)))
403409 		return;
404410 
405
-	if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && ring_id == RCS)
411
+	if (engine->id == RCS0 && IS_GEN(engine->i915, 9))
406412 		return;
407413 
408414 	if (!pre && !gen9_render_mocs.initialized)
409
-		load_render_mocs(dev_priv);
415
+		load_render_mocs(engine);
410416 
411
-	offset.reg = regs[ring_id];
417
+	offset.reg = regs[engine->id];
412418 	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
413419 		if (pre)
414420 			old_v = vgpu_vreg_t(pre, offset);
415421 		else
416
-			old_v = gen9_render_mocs.control_table[ring_id][i];
422
+			old_v = gen9_render_mocs.control_table[engine->id][i];
417423 		if (next)
418424 			new_v = vgpu_vreg_t(next, offset);
419425 		else
420
-			new_v = gen9_render_mocs.control_table[ring_id][i];
426
+			new_v = gen9_render_mocs.control_table[engine->id][i];
421427 
422428 		if (old_v != new_v)
423
-			I915_WRITE_FW(offset, new_v);
429
+			intel_uncore_write_fw(uncore, offset, new_v);
424430 
425431 		offset.reg += 4;
426432 	}
427433 
428
-	if (ring_id == RCS) {
434
+	if (engine->id == RCS0) {
429435 		l3_offset.reg = 0xb020;
430436 		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
431437 			if (pre)
....@@ -438,7 +444,7 @@
438444 				new_v = gen9_render_mocs.l3cc_table[i];
439445 
440446 			if (old_v != new_v)
441
-				I915_WRITE_FW(l3_offset, new_v);
447
+				intel_uncore_write_fw(uncore, l3_offset, new_v);
442448 
443449 			l3_offset.reg += 4;
444450 		}
....@@ -460,41 +466,40 @@
460466 /* Switch ring mmio values (context). */
461467 static void switch_mmio(struct intel_vgpu *pre,
462468 			struct intel_vgpu *next,
463
-			int ring_id)
469
+			const struct intel_engine_cs *engine)
464470 {
465
-	struct drm_i915_private *dev_priv;
471
+	struct intel_uncore *uncore = engine->uncore;
466472 	struct intel_vgpu_submission *s;
467473 	struct engine_mmio *mmio;
468474 	u32 old_v, new_v;
469475 
470
-	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
471
-	if (IS_SKYLAKE(dev_priv)
472
-		|| IS_KABYLAKE(dev_priv)
473
-		|| IS_BROXTON(dev_priv))
474
-		switch_mocs(pre, next, ring_id);
476
+	if (INTEL_GEN(engine->i915) >= 9)
477
+		switch_mocs(pre, next, engine);
475478 
476
-	for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
479
+	for (mmio = engine->i915->gvt->engine_mmio_list.mmio;
477480 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
478
-		if (mmio->ring_id != ring_id)
481
+		if (mmio->id != engine->id)
479482 			continue;
480483 		/*
481484 		 * No need to do save or restore of the mmio which is in context
482
-		 * state image on kabylake, it's initialized by lri command and
485
+		 * state image on gen9, it's initialized by lri command and
483486 		 * save or restore with context together.
484487 		 */
485
-		if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv))
486
-			&& mmio->in_context)
488
+		if (IS_GEN(engine->i915, 9) && mmio->in_context)
487489 			continue;
488490 
489491 		// save
490492 		if (pre) {
491
-			vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
493
+			vgpu_vreg_t(pre, mmio->reg) =
494
+				intel_uncore_read_fw(uncore, mmio->reg);
492495 			if (mmio->mask)
493496 				vgpu_vreg_t(pre, mmio->reg) &=
494
-						~(mmio->mask << 16);
497
+					~(mmio->mask << 16);
495498 			old_v = vgpu_vreg_t(pre, mmio->reg);
496
-		} else
497
-			old_v = mmio->value = I915_READ_FW(mmio->reg);
499
+		} else {
500
+			old_v = mmio->value =
501
+				intel_uncore_read_fw(uncore, mmio->reg);
502
+		}
498503 
499504 		// restore
500505 		if (next) {
....@@ -505,12 +510,12 @@
505510 			 * itself.
506511 			 */
507512 			if (mmio->in_context &&
508
-			    !is_inhibit_context(&s->shadow_ctx->__engine[ring_id]))
513
+			    !is_inhibit_context(s->shadow[engine->id]))
509514 				continue;
510515 
511516 			if (mmio->mask)
512517 				new_v = vgpu_vreg_t(next, mmio->reg) |
513
-							(mmio->mask << 16);
518
+					(mmio->mask << 16);
514519 			else
515520 				new_v = vgpu_vreg_t(next, mmio->reg);
516521 		} else {
....@@ -522,7 +527,7 @@
522527 				new_v = mmio->value;
523528 		}
524529 
525
-		I915_WRITE_FW(mmio->reg, new_v);
530
+		intel_uncore_write_fw(uncore, mmio->reg, new_v);
526531 
527532 		trace_render_mmio(pre ? pre->id : 0,
528533 				  next ? next->id : 0,
....@@ -532,39 +537,37 @@
532537 	}
533538 
534539 	if (next)
535
-		handle_tlb_pending_event(next, ring_id);
540
+		handle_tlb_pending_event(next, engine);
536541 }
537542 
538543 /**
539544  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
540545  * @pre: the last vGPU that own the engine
541546  * @next: the vGPU to switch to
542
- * @ring_id: specify the engine
547
+ * @engine: the engine
543548  *
544549  * If pre is null indicates that host own the engine. If next is null
545550  * indicates that we are switching to host workload.
546551  */
547552 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
548
-			   struct intel_vgpu *next, int ring_id)
553
+			   struct intel_vgpu *next,
554
+			   const struct intel_engine_cs *engine)
549555 {
550
-	struct drm_i915_private *dev_priv;
551
-
552
-	if (WARN_ON(!pre && !next))
556
+	if (WARN(!pre && !next, "switch ring %s from host to HOST\n",
557
+		 engine->name))
553558 		return;
554559 
555
-	gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
560
+	gvt_dbg_render("switch ring %s from %s to %s\n", engine->name,
556561 		       pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
557
-
558
-	dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
559562 
560563 	/**
561564 	 * We are using raw mmio access wrapper to improve the
562565 	 * performace for batch mmio read/write, so we need
563566 	 * handle forcewake mannually.
564567 	 */
565
-	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
566
-	switch_mmio(pre, next, ring_id);
567
-	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
568
+	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
569
+	switch_mmio(pre, next, engine);
570
+	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
568571 }
569572 
570573 /**
....@@ -576,18 +579,23 @@
576579 {
577580 	struct engine_mmio *mmio;
578581 
579
-	if (IS_SKYLAKE(gvt->dev_priv) ||
580
-		IS_KABYLAKE(gvt->dev_priv) ||
581
-		IS_BROXTON(gvt->dev_priv))
582
+	if (INTEL_GEN(gvt->gt->i915) >= 9) {
582583 		gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
583
-	else
584
+		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
585
+		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
586
+		gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list;
587
+		gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list);
588
+	} else {
584589 		gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
590
+		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
591
+		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
592
+	}
585593 
586594 	for (mmio = gvt->engine_mmio_list.mmio;
587595 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
588596 		if (mmio->in_context) {
589
-			gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
590
-			intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
597
+			gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++;
598
+			intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg);
591599 		}
592600 	}
593601 }