~hc/RK356X_SDK_RELEASE.git

..	..	@@ -22,86 +22,264 @@
22	22	#include <linux/edac.h>
23	23	#include <linux/module.h>
24	24	#include <linux/platform_device.h>
	25	+#include <linux/interrupt.h>
	26	+#include <linux/of.h>
	27	+#include <linux/of_device.h>
25	28
26	29	#include "edac_module.h"
27	30
28	31	/* Number of cs_rows needed per memory controller */
29		-#define SYNPS_EDAC_NR_CSROWS 1
	32	+#define SYNPS_EDAC_NR_CSROWS 1
30	33
31	34	/* Number of channels per memory controller */
32		-#define SYNPS_EDAC_NR_CHANS 1
	35	+#define SYNPS_EDAC_NR_CHANS 1
33	36
34	37	/* Granularity of reported error in bytes */
35		-#define SYNPS_EDAC_ERR_GRAIN 1
	38	+#define SYNPS_EDAC_ERR_GRAIN 1
36	39
37		-#define SYNPS_EDAC_MSG_SIZE 256
	40	+#define SYNPS_EDAC_MSG_SIZE 256
38	41
39		-#define SYNPS_EDAC_MOD_STRING "synps_edac"
40		-#define SYNPS_EDAC_MOD_VER "1"
	42	+#define SYNPS_EDAC_MOD_STRING "synps_edac"
	43	+#define SYNPS_EDAC_MOD_VER "1"
41	44
42	45	/* Synopsys DDR memory controller registers that are relevant to ECC */
43		-#define CTRL_OFST 0x0
44		-#define T_ZQ_OFST 0xA4
	46	+#define CTRL_OFST 0x0
	47	+#define T_ZQ_OFST 0xA4
45	48
46	49	/* ECC control register */
47		-#define ECC_CTRL_OFST 0xC4
	50	+#define ECC_CTRL_OFST 0xC4
48	51	/* ECC log register */
49		-#define CE_LOG_OFST 0xC8
	52	+#define CE_LOG_OFST 0xC8
50	53	/* ECC address register */
51		-#define CE_ADDR_OFST 0xCC
	54	+#define CE_ADDR_OFST 0xCC
52	55	/* ECC data[31:0] register */
53		-#define CE_DATA_31_0_OFST 0xD0
	56	+#define CE_DATA_31_0_OFST 0xD0
54	57
55	58	/* Uncorrectable error info registers */
56		-#define UE_LOG_OFST 0xDC
57		-#define UE_ADDR_OFST 0xE0
58		-#define UE_DATA_31_0_OFST 0xE4
	59	+#define UE_LOG_OFST 0xDC
	60	+#define UE_ADDR_OFST 0xE0
	61	+#define UE_DATA_31_0_OFST 0xE4
59	62
60		-#define STAT_OFST 0xF0
61		-#define SCRUB_OFST 0xF4
	63	+#define STAT_OFST 0xF0
	64	+#define SCRUB_OFST 0xF4
62	65
63	66	/* Control register bit field definitions */
64		-#define CTRL_BW_MASK 0xC
65		-#define CTRL_BW_SHIFT 2
	67	+#define CTRL_BW_MASK 0xC
	68	+#define CTRL_BW_SHIFT 2
66	69
67		-#define DDRCTL_WDTH_16 1
68		-#define DDRCTL_WDTH_32 0
	70	+#define DDRCTL_WDTH_16 1
	71	+#define DDRCTL_WDTH_32 0
69	72
70	73	/* ZQ register bit field definitions */
71		-#define T_ZQ_DDRMODE_MASK 0x2
	74	+#define T_ZQ_DDRMODE_MASK 0x2
72	75
73	76	/* ECC control register bit field definitions */
74		-#define ECC_CTRL_CLR_CE_ERR 0x2
75		-#define ECC_CTRL_CLR_UE_ERR 0x1
	77	+#define ECC_CTRL_CLR_CE_ERR 0x2
	78	+#define ECC_CTRL_CLR_UE_ERR 0x1
76	79
77	80	/* ECC correctable/uncorrectable error log register definitions */
78		-#define LOG_VALID 0x1
79		-#define CE_LOG_BITPOS_MASK 0xFE
80		-#define CE_LOG_BITPOS_SHIFT 1
	81	+#define LOG_VALID 0x1
	82	+#define CE_LOG_BITPOS_MASK 0xFE
	83	+#define CE_LOG_BITPOS_SHIFT 1
81	84
82	85	/* ECC correctable/uncorrectable error address register definitions */
83		-#define ADDR_COL_MASK 0xFFF
84		-#define ADDR_ROW_MASK 0xFFFF000
85		-#define ADDR_ROW_SHIFT 12
86		-#define ADDR_BANK_MASK 0x70000000
87		-#define ADDR_BANK_SHIFT 28
	86	+#define ADDR_COL_MASK 0xFFF
	87	+#define ADDR_ROW_MASK 0xFFFF000
	88	+#define ADDR_ROW_SHIFT 12
	89	+#define ADDR_BANK_MASK 0x70000000
	90	+#define ADDR_BANK_SHIFT 28
88	91
89	92	/* ECC statistic register definitions */
90		-#define STAT_UECNT_MASK 0xFF
91		-#define STAT_CECNT_MASK 0xFF00
92		-#define STAT_CECNT_SHIFT 8
	93	+#define STAT_UECNT_MASK 0xFF
	94	+#define STAT_CECNT_MASK 0xFF00
	95	+#define STAT_CECNT_SHIFT 8
93	96
94	97	/* ECC scrub register definitions */
95		-#define SCRUB_MODE_MASK 0x7
96		-#define SCRUB_MODE_SECDED 0x4
	98	+#define SCRUB_MODE_MASK 0x7
	99	+#define SCRUB_MODE_SECDED 0x4
	100	+
	101	+/* DDR ECC Quirks */
	102	+#define DDR_ECC_INTR_SUPPORT BIT(0)
	103	+#define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
	104	+
	105	+/* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
	106	+/* ECC Configuration Registers */
	107	+#define ECC_CFG0_OFST 0x70
	108	+#define ECC_CFG1_OFST 0x74
	109	+
	110	+/* ECC Status Register */
	111	+#define ECC_STAT_OFST 0x78
	112	+
	113	+/* ECC Clear Register */
	114	+#define ECC_CLR_OFST 0x7C
	115	+
	116	+/* ECC Error count Register */
	117	+#define ECC_ERRCNT_OFST 0x80
	118	+
	119	+/* ECC Corrected Error Address Register */
	120	+#define ECC_CEADDR0_OFST 0x84
	121	+#define ECC_CEADDR1_OFST 0x88
	122	+
	123	+/* ECC Syndrome Registers */
	124	+#define ECC_CSYND0_OFST 0x8C
	125	+#define ECC_CSYND1_OFST 0x90
	126	+#define ECC_CSYND2_OFST 0x94
	127	+
	128	+/* ECC Bit Mask0 Address Register */
	129	+#define ECC_BITMASK0_OFST 0x98
	130	+#define ECC_BITMASK1_OFST 0x9C
	131	+#define ECC_BITMASK2_OFST 0xA0
	132	+
	133	+/* ECC UnCorrected Error Address Register */
	134	+#define ECC_UEADDR0_OFST 0xA4
	135	+#define ECC_UEADDR1_OFST 0xA8
	136	+
	137	+/* ECC Syndrome Registers */
	138	+#define ECC_UESYND0_OFST 0xAC
	139	+#define ECC_UESYND1_OFST 0xB0
	140	+#define ECC_UESYND2_OFST 0xB4
	141	+
	142	+/* ECC Poison Address Reg */
	143	+#define ECC_POISON0_OFST 0xB8
	144	+#define ECC_POISON1_OFST 0xBC
	145	+
	146	+#define ECC_ADDRMAP0_OFFSET 0x200
	147	+
	148	+/* Control register bitfield definitions */
	149	+#define ECC_CTRL_BUSWIDTH_MASK 0x3000
	150	+#define ECC_CTRL_BUSWIDTH_SHIFT 12
	151	+#define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
	152	+#define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
	153	+
	154	+/* DDR Control Register width definitions */
	155	+#define DDRCTL_EWDTH_16 2
	156	+#define DDRCTL_EWDTH_32 1
	157	+#define DDRCTL_EWDTH_64 0
	158	+
	159	+/* ECC status register definitions */
	160	+#define ECC_STAT_UECNT_MASK 0xF0000
	161	+#define ECC_STAT_UECNT_SHIFT 16
	162	+#define ECC_STAT_CECNT_MASK 0xF00
	163	+#define ECC_STAT_CECNT_SHIFT 8
	164	+#define ECC_STAT_BITNUM_MASK 0x7F
	165	+
	166	+/* ECC error count register definitions */
	167	+#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000
	168	+#define ECC_ERRCNT_UECNT_SHIFT 16
	169	+#define ECC_ERRCNT_CECNT_MASK 0xFFFF
	170	+
	171	+/* DDR QOS Interrupt register definitions */
	172	+#define DDR_QOS_IRQ_STAT_OFST 0x20200
	173	+#define DDR_QOSUE_MASK 0x4
	174	+#define DDR_QOSCE_MASK 0x2
	175	+#define ECC_CE_UE_INTR_MASK 0x6
	176	+#define DDR_QOS_IRQ_EN_OFST 0x20208
	177	+#define DDR_QOS_IRQ_DB_OFST 0x2020C
	178	+
	179	+/* ECC Corrected Error Register Mask and Shifts*/
	180	+#define ECC_CEADDR0_RW_MASK 0x3FFFF
	181	+#define ECC_CEADDR0_RNK_MASK BIT(24)
	182	+#define ECC_CEADDR1_BNKGRP_MASK 0x3000000
	183	+#define ECC_CEADDR1_BNKNR_MASK 0x70000
	184	+#define ECC_CEADDR1_BLKNR_MASK 0xFFF
	185	+#define ECC_CEADDR1_BNKGRP_SHIFT 24
	186	+#define ECC_CEADDR1_BNKNR_SHIFT 16
	187	+
	188	+/* ECC Poison register shifts */
	189	+#define ECC_POISON0_RANK_SHIFT 24
	190	+#define ECC_POISON0_RANK_MASK BIT(24)
	191	+#define ECC_POISON0_COLUMN_SHIFT 0
	192	+#define ECC_POISON0_COLUMN_MASK 0xFFF
	193	+#define ECC_POISON1_BG_SHIFT 28
	194	+#define ECC_POISON1_BG_MASK 0x30000000
	195	+#define ECC_POISON1_BANKNR_SHIFT 24
	196	+#define ECC_POISON1_BANKNR_MASK 0x7000000
	197	+#define ECC_POISON1_ROW_SHIFT 0
	198	+#define ECC_POISON1_ROW_MASK 0x3FFFF
	199	+
	200	+/* DDR Memory type defines */
	201	+#define MEM_TYPE_DDR3 0x1
	202	+#define MEM_TYPE_LPDDR3 0x8
	203	+#define MEM_TYPE_DDR2 0x4
	204	+#define MEM_TYPE_DDR4 0x10
	205	+#define MEM_TYPE_LPDDR4 0x20
	206	+
	207	+/* DDRC Software control register */
	208	+#define DDRC_SWCTL 0x320
	209	+
	210	+/* DDRC ECC CE & UE poison mask */
	211	+#define ECC_CEPOISON_MASK 0x3
	212	+#define ECC_UEPOISON_MASK 0x1
	213	+
	214	+/* DDRC Device config masks */
	215	+#define DDRC_MSTR_CFG_MASK 0xC0000000
	216	+#define DDRC_MSTR_CFG_SHIFT 30
	217	+#define DDRC_MSTR_CFG_X4_MASK 0x0
	218	+#define DDRC_MSTR_CFG_X8_MASK 0x1
	219	+#define DDRC_MSTR_CFG_X16_MASK 0x2
	220	+#define DDRC_MSTR_CFG_X32_MASK 0x3
	221	+
	222	+#define DDR_MAX_ROW_SHIFT 18
	223	+#define DDR_MAX_COL_SHIFT 14
	224	+#define DDR_MAX_BANK_SHIFT 3
	225	+#define DDR_MAX_BANKGRP_SHIFT 2
	226	+
	227	+#define ROW_MAX_VAL_MASK 0xF
	228	+#define COL_MAX_VAL_MASK 0xF
	229	+#define BANK_MAX_VAL_MASK 0x1F
	230	+#define BANKGRP_MAX_VAL_MASK 0x1F
	231	+#define RANK_MAX_VAL_MASK 0x1F
	232	+
	233	+#define ROW_B0_BASE 6
	234	+#define ROW_B1_BASE 7
	235	+#define ROW_B2_BASE 8
	236	+#define ROW_B3_BASE 9
	237	+#define ROW_B4_BASE 10
	238	+#define ROW_B5_BASE 11
	239	+#define ROW_B6_BASE 12
	240	+#define ROW_B7_BASE 13
	241	+#define ROW_B8_BASE 14
	242	+#define ROW_B9_BASE 15
	243	+#define ROW_B10_BASE 16
	244	+#define ROW_B11_BASE 17
	245	+#define ROW_B12_BASE 18
	246	+#define ROW_B13_BASE 19
	247	+#define ROW_B14_BASE 20
	248	+#define ROW_B15_BASE 21
	249	+#define ROW_B16_BASE 22
	250	+#define ROW_B17_BASE 23
	251	+
	252	+#define COL_B2_BASE 2
	253	+#define COL_B3_BASE 3
	254	+#define COL_B4_BASE 4
	255	+#define COL_B5_BASE 5
	256	+#define COL_B6_BASE 6
	257	+#define COL_B7_BASE 7
	258	+#define COL_B8_BASE 8
	259	+#define COL_B9_BASE 9
	260	+#define COL_B10_BASE 10
	261	+#define COL_B11_BASE 11
	262	+#define COL_B12_BASE 12
	263	+#define COL_B13_BASE 13
	264	+
	265	+#define BANK_B0_BASE 2
	266	+#define BANK_B1_BASE 3
	267	+#define BANK_B2_BASE 4
	268	+
	269	+#define BANKGRP_B0_BASE 2
	270	+#define BANKGRP_B1_BASE 3
	271	+
	272	+#define RANK_B0_BASE 6
97	273
98	274	/**
99		- * struct ecc_error_info - ECC error log information
100		- * @row: Row number
101		- * @col: Column number
102		- * @bank: Bank number
103		- * @bitpos: Bit position
104		- * @data: Data causing the error
	275	+ * struct ecc_error_info - ECC error log information.
	276	+ * @row: Row number.
	277	+ * @col: Column number.
	278	+ * @bank: Bank number.
	279	+ * @bitpos: Bit position.
	280	+ * @data: Data causing the error.
	281	+ * @bankgrpnr: Bank group number.
	282	+ * @blknr: Block number.
105	283	*/
106	284	struct ecc_error_info {
107	285	u32 row;
..	..	@@ -109,14 +287,16 @@
109	287	u32 bank;
110	288	u32 bitpos;
111	289	u32 data;
	290	+ u32 bankgrpnr;
	291	+ u32 blknr;
112	292	};
113	293
114	294	/**
115		- * struct synps_ecc_status - ECC status information to report
116		- * @ce_cnt: Correctable error count
117		- * @ue_cnt: Uncorrectable error count
118		- * @ceinfo: Correctable error log information
119		- * @ueinfo: Uncorrectable error log information
	295	+ * struct synps_ecc_status - ECC status information to report.
	296	+ * @ce_cnt: Correctable error count.
	297	+ * @ue_cnt: Uncorrectable error count.
	298	+ * @ceinfo: Correctable error log information.
	299	+ * @ueinfo: Uncorrectable error log information.
120	300	*/
121	301	struct synps_ecc_status {
122	302	u32 ce_cnt;
..	..	@@ -126,34 +306,67 @@
126	306	};
127	307
128	308	/**
129		- * struct synps_edac_priv - DDR memory controller private instance data
130		- * @baseaddr: Base address of the DDR controller
131		- * @message: Buffer for framing the event specific info
132		- * @stat: ECC status information
133		- * @ce_cnt: Correctable Error count
134		- * @ue_cnt: Uncorrectable Error count
	309	+ * struct synps_edac_priv - DDR memory controller private instance data.
	310	+ * @baseaddr: Base address of the DDR controller.
	311	+ * @message: Buffer for framing the event specific info.
	312	+ * @stat: ECC status information.
	313	+ * @p_data: Platform data.
	314	+ * @ce_cnt: Correctable Error count.
	315	+ * @ue_cnt: Uncorrectable Error count.
	316	+ * @poison_addr: Data poison address.
	317	+ * @row_shift: Bit shifts for row bit.
	318	+ * @col_shift: Bit shifts for column bit.
	319	+ * @bank_shift: Bit shifts for bank bit.
	320	+ * @bankgrp_shift: Bit shifts for bank group bit.
	321	+ * @rank_shift: Bit shifts for rank bit.
135	322	*/
136	323	struct synps_edac_priv {
137	324	void __iomem *baseaddr;
138	325	char message[SYNPS_EDAC_MSG_SIZE];
139	326	struct synps_ecc_status stat;
	327	+ const struct synps_platform_data *p_data;
140	328	u32 ce_cnt;
141	329	u32 ue_cnt;
	330	+#ifdef CONFIG_EDAC_DEBUG
	331	+ ulong poison_addr;
	332	+ u32 row_shift[18];
	333	+ u32 col_shift[14];
	334	+ u32 bank_shift[3];
	335	+ u32 bankgrp_shift[2];
	336	+ u32 rank_shift[1];
	337	+#endif
142	338	};
143	339
144	340	/**
145		- * synps_edac_geterror_info - Get the current ecc error info
146		- * @base: Pointer to the base address of the ddr memory controller
147		- * @p: Pointer to the synopsys ecc status structure
148		- *
149		- * Determines there is any ecc error or not
150		- *
151		- * Return: one if there is no error otherwise returns zero
	341	+ * struct synps_platform_data - synps platform data structure.
	342	+ * @get_error_info: Get EDAC error info.
	343	+ * @get_mtype: Get mtype.
	344	+ * @get_dtype: Get dtype.
	345	+ * @get_ecc_state: Get ECC state.
	346	+ * @quirks: To differentiate IPs.
152	347	*/
153		-static int synps_edac_geterror_info(void __iomem *base,
154		- struct synps_ecc_status *p)
	348	+struct synps_platform_data {
	349	+ int (get_error_info)(struct synps_edac_priv priv);
	350	+ enum mem_type (get_mtype)(const void __iomem base);
	351	+ enum dev_type (get_dtype)(const void __iomem base);
	352	+ bool (get_ecc_state)(void __iomem base);
	353	+ int quirks;
	354	+};
	355	+
	356	+/**
	357	+ * zynq_get_error_info - Get the current ECC error info.
	358	+ * @priv: DDR memory controller private instance data.
	359	+ *
	360	+ * Return: one if there is no error, otherwise zero.
	361	+ */
	362	+static int zynq_get_error_info(struct synps_edac_priv *priv)
155	363	{
	364	+ struct synps_ecc_status *p;
156	365	u32 regval, clearval = 0;
	366	+ void __iomem *base;
	367	+
	368	+ base = priv->baseaddr;
	369	+ p = &priv->stat;
157	370
158	371	regval = readl(base + STAT_OFST);
159	372	if (!regval)
..	..	@@ -172,7 +385,7 @@
172	385	p->ceinfo.col = regval & ADDR_COL_MASK;
173	386	p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
174	387	p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
175		- edac_dbg(3, "ce bit position: %d data: %d\n", p->ceinfo.bitpos,
	388	+ edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
176	389	p->ceinfo.data);
177	390	clearval = ECC_CTRL_CLR_CE_ERR;
178	391
..	..	@@ -196,23 +409,93 @@
196	409	}
197	410
198	411	/**
199		- * synps_edac_handle_error - Handle controller error types CE and UE
200		- * @mci: Pointer to the edac memory controller instance
201		- * @p: Pointer to the synopsys ecc status structure
	412	+ * zynqmp_get_error_info - Get the current ECC error info.
	413	+ * @priv: DDR memory controller private instance data.
202	414	*
203		- * Handles the controller ECC correctable and un correctable error.
	415	+ * Return: one if there is no error otherwise returns zero.
204	416	*/
205		-static void synps_edac_handle_error(struct mem_ctl_info *mci,
206		- struct synps_ecc_status *p)
	417	+static int zynqmp_get_error_info(struct synps_edac_priv *priv)
	418	+{
	419	+ struct synps_ecc_status *p;
	420	+ u32 regval, clearval = 0;
	421	+ void __iomem *base;
	422	+
	423	+ base = priv->baseaddr;
	424	+ p = &priv->stat;
	425	+
	426	+ regval = readl(base + ECC_ERRCNT_OFST);
	427	+ p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
	428	+ p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
	429	+ if (!p->ce_cnt)
	430	+ goto ue_err;
	431	+
	432	+ regval = readl(base + ECC_STAT_OFST);
	433	+ if (!regval)
	434	+ return 1;
	435	+
	436	+ p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
	437	+
	438	+ regval = readl(base + ECC_CEADDR0_OFST);
	439	+ p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
	440	+ regval = readl(base + ECC_CEADDR1_OFST);
	441	+ p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
	442	+ ECC_CEADDR1_BNKNR_SHIFT;
	443	+ p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
	444	+ ECC_CEADDR1_BNKGRP_SHIFT;
	445	+ p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
	446	+ p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
	447	+ edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
	448	+ readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
	449	+ readl(base + ECC_CSYND2_OFST));
	450	+ue_err:
	451	+ if (!p->ue_cnt)
	452	+ goto out;
	453	+
	454	+ regval = readl(base + ECC_UEADDR0_OFST);
	455	+ p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
	456	+ regval = readl(base + ECC_UEADDR1_OFST);
	457	+ p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
	458	+ ECC_CEADDR1_BNKGRP_SHIFT;
	459	+ p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
	460	+ ECC_CEADDR1_BNKNR_SHIFT;
	461	+ p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
	462	+ p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
	463	+out:
	464	+ clearval = ECC_CTRL_CLR_CE_ERR \| ECC_CTRL_CLR_CE_ERRCNT;
	465	+ clearval \|= ECC_CTRL_CLR_UE_ERR \| ECC_CTRL_CLR_UE_ERRCNT;
	466	+ writel(clearval, base + ECC_CLR_OFST);
	467	+ writel(0x0, base + ECC_CLR_OFST);
	468	+
	469	+ return 0;
	470	+}
	471	+
	472	+/**
	473	+ * handle_error - Handle Correctable and Uncorrectable errors.
	474	+ * @mci: EDAC memory controller instance.
	475	+ * @p: Synopsys ECC status structure.
	476	+ *
	477	+ * Handles ECC correctable and uncorrectable errors.
	478	+ */
	479	+static void handle_error(struct mem_ctl_info mci, struct synps_ecc_status p)
207	480	{
208	481	struct synps_edac_priv *priv = mci->pvt_info;
209	482	struct ecc_error_info *pinf;
210	483
211	484	if (p->ce_cnt) {
212	485	pinf = &p->ceinfo;
213		- snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
214		- "DDR ECC error type :%s Row %d Bank %d Col %d ",
215		- "CE", pinf->row, pinf->bank, pinf->col);
	486	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
	487	+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
	488	+ "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
	489	+ "CE", pinf->row, pinf->bank,
	490	+ pinf->bankgrpnr, pinf->blknr,
	491	+ pinf->bitpos, pinf->data);
	492	+ } else {
	493	+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
	494	+ "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
	495	+ "CE", pinf->row, pinf->bank, pinf->col,
	496	+ pinf->bitpos, pinf->data);
	497	+ }
	498	+
216	499	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
217	500	p->ce_cnt, 0, 0, 0, 0, 0, -1,
218	501	priv->message, "");
..	..	@@ -220,9 +503,17 @@
220	503
221	504	if (p->ue_cnt) {
222	505	pinf = &p->ueinfo;
223		- snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
224		- "DDR ECC error type :%s Row %d Bank %d Col %d ",
225		- "UE", pinf->row, pinf->bank, pinf->col);
	506	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
	507	+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
	508	+ "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
	509	+ "UE", pinf->row, pinf->bank,
	510	+ pinf->bankgrpnr, pinf->blknr);
	511	+ } else {
	512	+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
	513	+ "DDR ECC error type :%s Row %d Bank %d Col %d ",
	514	+ "UE", pinf->row, pinf->bank, pinf->col);
	515	+ }
	516	+
226	517	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
227	518	p->ue_cnt, 0, 0, 0, 0, 0, -1,
228	519	priv->message, "");
..	..	@@ -232,38 +523,78 @@
232	523	}
233	524
234	525	/**
235		- * synps_edac_check - Check controller for ECC errors
236		- * @mci: Pointer to the edac memory controller instance
	526	+ * intr_handler - Interrupt Handler for ECC interrupts.
	527	+ * @irq: IRQ number.
	528	+ * @dev_id: Device ID.
237	529	*
238		- * Used to check and post ECC errors. Called by the polling thread
	530	+ * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
239	531	*/
240		-static void synps_edac_check(struct mem_ctl_info *mci)
	532	+static irqreturn_t intr_handler(int irq, void *dev_id)
241	533	{
242		- struct synps_edac_priv *priv = mci->pvt_info;
	534	+ const struct synps_platform_data *p_data;
	535	+ struct mem_ctl_info *mci = dev_id;
	536	+ struct synps_edac_priv *priv;
	537	+ int status, regval;
	538	+
	539	+ priv = mci->pvt_info;
	540	+ p_data = priv->p_data;
	541	+
	542	+ regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
	543	+ regval &= (DDR_QOSCE_MASK \| DDR_QOSUE_MASK);
	544	+ if (!(regval & ECC_CE_UE_INTR_MASK))
	545	+ return IRQ_NONE;
	546	+
	547	+ status = p_data->get_error_info(priv);
	548	+ if (status)
	549	+ return IRQ_NONE;
	550	+
	551	+ priv->ce_cnt += priv->stat.ce_cnt;
	552	+ priv->ue_cnt += priv->stat.ue_cnt;
	553	+ handle_error(mci, &priv->stat);
	554	+
	555	+ edac_dbg(3, "Total error count CE %d UE %d\n",
	556	+ priv->ce_cnt, priv->ue_cnt);
	557	+ writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
	558	+ return IRQ_HANDLED;
	559	+}
	560	+
	561	+/**
	562	+ * check_errors - Check controller for ECC errors.
	563	+ * @mci: EDAC memory controller instance.
	564	+ *
	565	+ * Check and post ECC errors. Called by the polling thread.
	566	+ */
	567	+static void check_errors(struct mem_ctl_info *mci)
	568	+{
	569	+ const struct synps_platform_data *p_data;
	570	+ struct synps_edac_priv *priv;
243	571	int status;
244	572
245		- status = synps_edac_geterror_info(priv->baseaddr, &priv->stat);
	573	+ priv = mci->pvt_info;
	574	+ p_data = priv->p_data;
	575	+
	576	+ status = p_data->get_error_info(priv);
246	577	if (status)
247	578	return;
248	579
249	580	priv->ce_cnt += priv->stat.ce_cnt;
250	581	priv->ue_cnt += priv->stat.ue_cnt;
251		- synps_edac_handle_error(mci, &priv->stat);
	582	+ handle_error(mci, &priv->stat);
252	583
253		- edac_dbg(3, "Total error count ce %d ue %d\n",
	584	+ edac_dbg(3, "Total error count CE %d UE %d\n",
254	585	priv->ce_cnt, priv->ue_cnt);
255	586	}
256	587
257	588	/**
258		- * synps_edac_get_dtype - Return the controller memory width
259		- * @base: Pointer to the ddr memory controller base address
	589	+ * zynq_get_dtype - Return the controller memory width.
	590	+ * @base: DDR memory controller base address.
260	591	*
261	592	* Get the EDAC device type width appropriate for the current controller
262	593	* configuration.
263	594	*
264	595	* Return: a device type width enumeration.
265	596	*/
266		-static enum dev_type synps_edac_get_dtype(const void __iomem *base)
	597	+static enum dev_type zynq_get_dtype(const void __iomem *base)
267	598	{
268	599	enum dev_type dt;
269	600	u32 width;
..	..	@@ -286,36 +617,93 @@
286	617	}
287	618
288	619	/**
289		- * synps_edac_get_eccstate - Return the controller ecc enable/disable status
290		- * @base: Pointer to the ddr memory controller base address
	620	+ * zynqmp_get_dtype - Return the controller memory width.
	621	+ * @base: DDR memory controller base address.
291	622	*
292		- * Get the ECC enable/disable status for the controller
	623	+ * Get the EDAC device type width appropriate for the current controller
	624	+ * configuration.
293	625	*
294		- * Return: a ecc status boolean i.e true/false - enabled/disabled.
	626	+ * Return: a device type width enumeration.
295	627	*/
296		-static bool synps_edac_get_eccstate(void __iomem *base)
	628	+static enum dev_type zynqmp_get_dtype(const void __iomem *base)
297	629	{
298	630	enum dev_type dt;
299		- u32 ecctype;
300		- bool state = false;
	631	+ u32 width;
301	632
302		- dt = synps_edac_get_dtype(base);
303		- if (dt == DEV_UNKNOWN)
304		- return state;
	633	+ width = readl(base + CTRL_OFST);
	634	+ width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
	635	+ switch (width) {
	636	+ case DDRCTL_EWDTH_16:
	637	+ dt = DEV_X2;
	638	+ break;
	639	+ case DDRCTL_EWDTH_32:
	640	+ dt = DEV_X4;
	641	+ break;
	642	+ case DDRCTL_EWDTH_64:
	643	+ dt = DEV_X8;
	644	+ break;
	645	+ default:
	646	+ dt = DEV_UNKNOWN;
	647	+ }
305	648
306		- ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
307		- if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
308		- state = true;
309		-
310		- return state;
	649	+ return dt;
311	650	}
312	651
313	652	/**
314		- * synps_edac_get_memsize - reads the size of the attached memory device
	653	+ * zynq_get_ecc_state - Return the controller ECC enable/disable status.
	654	+ * @base: DDR memory controller base address.
315	655	*
316		- * Return: the memory size in bytes
	656	+ * Get the ECC enable/disable status of the controller.
	657	+ *
	658	+ * Return: true if enabled, otherwise false.
317	659	*/
318		-static u32 synps_edac_get_memsize(void)
	660	+static bool zynq_get_ecc_state(void __iomem *base)
	661	+{
	662	+ enum dev_type dt;
	663	+ u32 ecctype;
	664	+
	665	+ dt = zynq_get_dtype(base);
	666	+ if (dt == DEV_UNKNOWN)
	667	+ return false;
	668	+
	669	+ ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
	670	+ if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
	671	+ return true;
	672	+
	673	+ return false;
	674	+}
	675	+
	676	+/**
	677	+ * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
	678	+ * @base: DDR memory controller base address.
	679	+ *
	680	+ * Get the ECC enable/disable status for the controller.
	681	+ *
	682	+ * Return: a ECC status boolean i.e true/false - enabled/disabled.
	683	+ */
	684	+static bool zynqmp_get_ecc_state(void __iomem *base)
	685	+{
	686	+ enum dev_type dt;
	687	+ u32 ecctype;
	688	+
	689	+ dt = zynqmp_get_dtype(base);
	690	+ if (dt == DEV_UNKNOWN)
	691	+ return false;
	692	+
	693	+ ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
	694	+ if ((ecctype == SCRUB_MODE_SECDED) &&
	695	+ ((dt == DEV_X2) \|\| (dt == DEV_X4) \|\| (dt == DEV_X8)))
	696	+ return true;
	697	+
	698	+ return false;
	699	+}
	700	+
	701	+/**
	702	+ * get_memsize - Read the size of the attached memory device.
	703	+ *
	704	+ * Return: the memory size in bytes.
	705	+ */
	706	+static u32 get_memsize(void)
319	707	{
320	708	struct sysinfo inf;
321	709
..	..	@@ -325,15 +713,15 @@
325	713	}
326	714
327	715	/**
328		- * synps_edac_get_mtype - Returns controller memory type
329		- * @base: pointer to the synopsys ecc status structure
	716	+ * zynq_get_mtype - Return the controller memory type.
	717	+ * @base: Synopsys ECC status structure.
330	718	*
331	719	* Get the EDAC memory type appropriate for the current controller
332	720	* configuration.
333	721	*
334	722	* Return: a memory type enumeration.
335	723	*/
336		-static enum mem_type synps_edac_get_mtype(const void __iomem *base)
	724	+static enum mem_type zynq_get_mtype(const void __iomem *base)
337	725	{
338	726	enum mem_type mt;
339	727	u32 memtype;
..	..	@@ -349,54 +737,77 @@
349	737	}
350	738
351	739	/**
352		- * synps_edac_init_csrows - Initialize the cs row data
353		- * @mci: Pointer to the edac memory controller instance
	740	+ * zynqmp_get_mtype - Returns controller memory type.
	741	+ * @base: Synopsys ECC status structure.
354	742	*
355		- * Initializes the chip select rows associated with the EDAC memory
356		- * controller instance
	743	+ * Get the EDAC memory type appropriate for the current controller
	744	+ * configuration.
357	745	*
358		- * Return: Unconditionally 0.
	746	+ * Return: a memory type enumeration.
359	747	*/
360		-static int synps_edac_init_csrows(struct mem_ctl_info *mci)
	748	+static enum mem_type zynqmp_get_mtype(const void __iomem *base)
361	749	{
362		- struct csrow_info *csi;
363		- struct dimm_info *dimm;
364		- struct synps_edac_priv *priv = mci->pvt_info;
365		- u32 size;
366		- int row, j;
	750	+ enum mem_type mt;
	751	+ u32 memtype;
367	752
368		- for (row = 0; row < mci->nr_csrows; row++) {
369		- csi = mci->csrows[row];
370		- size = synps_edac_get_memsize();
	753	+ memtype = readl(base + CTRL_OFST);
371	754
372		- for (j = 0; j < csi->nr_channels; j++) {
373		- dimm = csi->channels[j]->dimm;
374		- dimm->edac_mode = EDAC_SECDED;
375		- dimm->mtype = synps_edac_get_mtype(priv->baseaddr);
376		- dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
377		- dimm->grain = SYNPS_EDAC_ERR_GRAIN;
378		- dimm->dtype = synps_edac_get_dtype(priv->baseaddr);
379		- }
380		- }
	755	+ if ((memtype & MEM_TYPE_DDR3) \|\| (memtype & MEM_TYPE_LPDDR3))
	756	+ mt = MEM_DDR3;
	757	+ else if (memtype & MEM_TYPE_DDR2)
	758	+ mt = MEM_RDDR2;
	759	+ else if ((memtype & MEM_TYPE_LPDDR4) \|\| (memtype & MEM_TYPE_DDR4))
	760	+ mt = MEM_DDR4;
	761	+ else
	762	+ mt = MEM_EMPTY;
381	763
382		- return 0;
	764	+ return mt;
383	765	}
384	766
385	767	/**
386		- * synps_edac_mc_init - Initialize driver instance
387		- * @mci: Pointer to the edac memory controller instance
388		- * @pdev: Pointer to the platform_device struct
	768	+ * init_csrows - Initialize the csrow data.
	769	+ * @mci: EDAC memory controller instance.
389	770	*
390		- * Performs initialization of the EDAC memory controller instance and
	771	+ * Initialize the chip select rows associated with the EDAC memory
	772	+ * controller instance.
	773	+ */
	774	+static void init_csrows(struct mem_ctl_info *mci)
	775	+{
	776	+ struct synps_edac_priv *priv = mci->pvt_info;
	777	+ const struct synps_platform_data *p_data;
	778	+ struct csrow_info *csi;
	779	+ struct dimm_info *dimm;
	780	+ u32 size, row;
	781	+ int j;
	782	+
	783	+ p_data = priv->p_data;
	784	+
	785	+ for (row = 0; row < mci->nr_csrows; row++) {
	786	+ csi = mci->csrows[row];
	787	+ size = get_memsize();
	788	+
	789	+ for (j = 0; j < csi->nr_channels; j++) {
	790	+ dimm = csi->channels[j]->dimm;
	791	+ dimm->edac_mode = EDAC_SECDED;
	792	+ dimm->mtype = p_data->get_mtype(priv->baseaddr);
	793	+ dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
	794	+ dimm->grain = SYNPS_EDAC_ERR_GRAIN;
	795	+ dimm->dtype = p_data->get_dtype(priv->baseaddr);
	796	+ }
	797	+ }
	798	+}
	799	+
	800	+/**
	801	+ * mc_init - Initialize one driver instance.
	802	+ * @mci: EDAC memory controller instance.
	803	+ * @pdev: platform device.
	804	+ *
	805	+ * Perform initialization of the EDAC memory controller instance and
391	806	* related driver-private data associated with the memory controller the
392	807	* instance is bound to.
393		- *
394		- * Return: Always zero.
395	808	*/
396		-static int synps_edac_mc_init(struct mem_ctl_info *mci,
397		- struct platform_device *pdev)
	809	+static void mc_init(struct mem_ctl_info mci, struct platform_device pdev)
398	810	{
399		- int status;
400	811	struct synps_edac_priv *priv;
401	812
402	813	mci->pdev = &pdev->dev;
..	..	@@ -414,39 +825,491 @@
414	825	mci->dev_name = SYNPS_EDAC_MOD_STRING;
415	826	mci->mod_name = SYNPS_EDAC_MOD_VER;
416	827
417		- edac_op_state = EDAC_OPSTATE_POLL;
418		- mci->edac_check = synps_edac_check;
	828	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
	829	+ edac_op_state = EDAC_OPSTATE_INT;
	830	+ } else {
	831	+ edac_op_state = EDAC_OPSTATE_POLL;
	832	+ mci->edac_check = check_errors;
	833	+ }
	834	+
419	835	mci->ctl_page_to_phys = NULL;
420	836
421		- status = synps_edac_init_csrows(mci);
	837	+ init_csrows(mci);
	838	+}
422	839
423		- return status;
	840	+static void enable_intr(struct synps_edac_priv *priv)
	841	+{
	842	+ /* Enable UE/CE Interrupts */
	843	+ writel(DDR_QOSUE_MASK \| DDR_QOSCE_MASK,
	844	+ priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
	845	+}
	846	+
	847	+static void disable_intr(struct synps_edac_priv *priv)
	848	+{
	849	+ /* Disable UE/CE Interrupts */
	850	+ writel(DDR_QOSUE_MASK \| DDR_QOSCE_MASK,
	851	+ priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
	852	+}
	853	+
	854	+static int setup_irq(struct mem_ctl_info *mci,
	855	+ struct platform_device *pdev)
	856	+{
	857	+ struct synps_edac_priv *priv = mci->pvt_info;
	858	+ int ret, irq;
	859	+
	860	+ irq = platform_get_irq(pdev, 0);
	861	+ if (irq < 0) {
	862	+ edac_printk(KERN_ERR, EDAC_MC,
	863	+ "No IRQ %d in DT\n", irq);
	864	+ return irq;
	865	+ }
	866	+
	867	+ ret = devm_request_irq(&pdev->dev, irq, intr_handler,
	868	+ 0, dev_name(&pdev->dev), mci);
	869	+ if (ret < 0) {
	870	+ edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
	871	+ return ret;
	872	+ }
	873	+
	874	+ enable_intr(priv);
	875	+
	876	+ return 0;
	877	+}
	878	+
	879	+static const struct synps_platform_data zynq_edac_def = {
	880	+ .get_error_info = zynq_get_error_info,
	881	+ .get_mtype = zynq_get_mtype,
	882	+ .get_dtype = zynq_get_dtype,
	883	+ .get_ecc_state = zynq_get_ecc_state,
	884	+ .quirks = 0,
	885	+};
	886	+
	887	+static const struct synps_platform_data zynqmp_edac_def = {
	888	+ .get_error_info = zynqmp_get_error_info,
	889	+ .get_mtype = zynqmp_get_mtype,
	890	+ .get_dtype = zynqmp_get_dtype,
	891	+ .get_ecc_state = zynqmp_get_ecc_state,
	892	+ .quirks = (DDR_ECC_INTR_SUPPORT
	893	+#ifdef CONFIG_EDAC_DEBUG
	894	+ \| DDR_ECC_DATA_POISON_SUPPORT
	895	+#endif
	896	+ ),
	897	+};
	898	+
	899	+static const struct of_device_id synps_edac_match[] = {
	900	+ {
	901	+ .compatible = "xlnx,zynq-ddrc-a05",
	902	+ .data = (void *)&zynq_edac_def
	903	+ },
	904	+ {
	905	+ .compatible = "xlnx,zynqmp-ddrc-2.40a",
	906	+ .data = (void *)&zynqmp_edac_def
	907	+ },
	908	+ {
	909	+ /* end of table */
	910	+ }
	911	+};
	912	+
	913	+MODULE_DEVICE_TABLE(of, synps_edac_match);
	914	+
	915	+#ifdef CONFIG_EDAC_DEBUG
	916	+#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
	917	+
	918	+/**
	919	+ * ddr_poison_setup - Update poison registers.
	920	+ * @priv: DDR memory controller private instance data.
	921	+ *
	922	+ * Update poison registers as per DDR mapping.
	923	+ * Return: none.
	924	+ */
	925	+static void ddr_poison_setup(struct synps_edac_priv *priv)
	926	+{
	927	+ int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
	928	+ int index;
	929	+ ulong hif_addr = 0;
	930	+
	931	+ hif_addr = priv->poison_addr >> 3;
	932	+
	933	+ for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
	934	+ if (priv->row_shift[index])
	935	+ row \|= (((hif_addr >> priv->row_shift[index]) &
	936	+ BIT(0)) << index);
	937	+ else
	938	+ break;
	939	+ }
	940	+
	941	+ for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
	942	+ if (priv->col_shift[index] \|\| index < 3)
	943	+ col \|= (((hif_addr >> priv->col_shift[index]) &
	944	+ BIT(0)) << index);
	945	+ else
	946	+ break;
	947	+ }
	948	+
	949	+ for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
	950	+ if (priv->bank_shift[index])
	951	+ bank \|= (((hif_addr >> priv->bank_shift[index]) &
	952	+ BIT(0)) << index);
	953	+ else
	954	+ break;
	955	+ }
	956	+
	957	+ for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
	958	+ if (priv->bankgrp_shift[index])
	959	+ bankgrp \|= (((hif_addr >> priv->bankgrp_shift[index])
	960	+ & BIT(0)) << index);
	961	+ else
	962	+ break;
	963	+ }
	964	+
	965	+ if (priv->rank_shift[0])
	966	+ rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
	967	+
	968	+ regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
	969	+ regval \|= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
	970	+ writel(regval, priv->baseaddr + ECC_POISON0_OFST);
	971	+
	972	+ regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
	973	+ regval \|= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
	974	+ regval \|= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
	975	+ writel(regval, priv->baseaddr + ECC_POISON1_OFST);
	976	+}
	977	+
	978	+static ssize_t inject_data_error_show(struct device *dev,
	979	+ struct device_attribute *mattr,
	980	+ char *data)
	981	+{
	982	+ struct mem_ctl_info *mci = to_mci(dev);
	983	+ struct synps_edac_priv *priv = mci->pvt_info;
	984	+
	985	+ return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
	986	+ "Error injection Address: 0x%lx\n\r",
	987	+ readl(priv->baseaddr + ECC_POISON0_OFST),
	988	+ readl(priv->baseaddr + ECC_POISON1_OFST),
	989	+ priv->poison_addr);
	990	+}
	991	+
	992	+static ssize_t inject_data_error_store(struct device *dev,
	993	+ struct device_attribute *mattr,
	994	+ const char *data, size_t count)
	995	+{
	996	+ struct mem_ctl_info *mci = to_mci(dev);
	997	+ struct synps_edac_priv *priv = mci->pvt_info;
	998	+
	999	+ if (kstrtoul(data, 0, &priv->poison_addr))
	1000	+ return -EINVAL;
	1001	+
	1002	+ ddr_poison_setup(priv);
	1003	+
	1004	+ return count;
	1005	+}
	1006	+
	1007	+static ssize_t inject_data_poison_show(struct device *dev,
	1008	+ struct device_attribute *mattr,
	1009	+ char *data)
	1010	+{
	1011	+ struct mem_ctl_info *mci = to_mci(dev);
	1012	+ struct synps_edac_priv *priv = mci->pvt_info;
	1013	+
	1014	+ return sprintf(data, "Data Poisoning: %s\n\r",
	1015	+ (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
	1016	+ ? ("Correctable Error") : ("UnCorrectable Error"));
	1017	+}
	1018	+
	1019	+static ssize_t inject_data_poison_store(struct device *dev,
	1020	+ struct device_attribute *mattr,
	1021	+ const char *data, size_t count)
	1022	+{
	1023	+ struct mem_ctl_info *mci = to_mci(dev);
	1024	+ struct synps_edac_priv *priv = mci->pvt_info;
	1025	+
	1026	+ writel(0, priv->baseaddr + DDRC_SWCTL);
	1027	+ if (strncmp(data, "CE", 2) == 0)
	1028	+ writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
	1029	+ else
	1030	+ writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
	1031	+ writel(1, priv->baseaddr + DDRC_SWCTL);
	1032	+
	1033	+ return count;
	1034	+}
	1035	+
	1036	+static DEVICE_ATTR_RW(inject_data_error);
	1037	+static DEVICE_ATTR_RW(inject_data_poison);
	1038	+
	1039	+static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
	1040	+{
	1041	+ int rc;
	1042	+
	1043	+ rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
	1044	+ if (rc < 0)
	1045	+ return rc;
	1046	+ rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
	1047	+ if (rc < 0)
	1048	+ return rc;
	1049	+ return 0;
	1050	+}
	1051	+
	1052	+static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
	1053	+{
	1054	+ device_remove_file(&mci->dev, &dev_attr_inject_data_error);
	1055	+ device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
	1056	+}
	1057	+
	1058	+static void setup_row_address_map(struct synps_edac_priv priv, u32 addrmap)
	1059	+{
	1060	+ u32 addrmap_row_b2_10;
	1061	+ int index;
	1062	+
	1063	+ priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
	1064	+ priv->row_shift[1] = ((addrmap[5] >> 8) &
	1065	+ ROW_MAX_VAL_MASK) + ROW_B1_BASE;
	1066	+
	1067	+ addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
	1068	+ if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
	1069	+ for (index = 2; index < 11; index++)
	1070	+ priv->row_shift[index] = addrmap_row_b2_10 +
	1071	+ index + ROW_B0_BASE;
	1072	+
	1073	+ } else {
	1074	+ priv->row_shift[2] = (addrmap[9] &
	1075	+ ROW_MAX_VAL_MASK) + ROW_B2_BASE;
	1076	+ priv->row_shift[3] = ((addrmap[9] >> 8) &
	1077	+ ROW_MAX_VAL_MASK) + ROW_B3_BASE;
	1078	+ priv->row_shift[4] = ((addrmap[9] >> 16) &
	1079	+ ROW_MAX_VAL_MASK) + ROW_B4_BASE;
	1080	+ priv->row_shift[5] = ((addrmap[9] >> 24) &
	1081	+ ROW_MAX_VAL_MASK) + ROW_B5_BASE;
	1082	+ priv->row_shift[6] = (addrmap[10] &
	1083	+ ROW_MAX_VAL_MASK) + ROW_B6_BASE;
	1084	+ priv->row_shift[7] = ((addrmap[10] >> 8) &
	1085	+ ROW_MAX_VAL_MASK) + ROW_B7_BASE;
	1086	+ priv->row_shift[8] = ((addrmap[10] >> 16) &
	1087	+ ROW_MAX_VAL_MASK) + ROW_B8_BASE;
	1088	+ priv->row_shift[9] = ((addrmap[10] >> 24) &
	1089	+ ROW_MAX_VAL_MASK) + ROW_B9_BASE;
	1090	+ priv->row_shift[10] = (addrmap[11] &
	1091	+ ROW_MAX_VAL_MASK) + ROW_B10_BASE;
	1092	+ }
	1093	+
	1094	+ priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
	1095	+ ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
	1096	+ ROW_MAX_VAL_MASK) + ROW_B11_BASE);
	1097	+ priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
	1098	+ ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
	1099	+ ROW_MAX_VAL_MASK) + ROW_B12_BASE);
	1100	+ priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
	1101	+ ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
	1102	+ ROW_MAX_VAL_MASK) + ROW_B13_BASE);
	1103	+ priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
	1104	+ ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
	1105	+ ROW_MAX_VAL_MASK) + ROW_B14_BASE);
	1106	+ priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
	1107	+ ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
	1108	+ ROW_MAX_VAL_MASK) + ROW_B15_BASE);
	1109	+ priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
	1110	+ ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
	1111	+ ROW_MAX_VAL_MASK) + ROW_B16_BASE);
	1112	+ priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
	1113	+ ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
	1114	+ ROW_MAX_VAL_MASK) + ROW_B17_BASE);
	1115	+}
	1116	+
	1117	+static void setup_column_address_map(struct synps_edac_priv priv, u32 addrmap)
	1118	+{
	1119	+ u32 width, memtype;
	1120	+ int index;
	1121	+
	1122	+ memtype = readl(priv->baseaddr + CTRL_OFST);
	1123	+ width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
	1124	+
	1125	+ priv->col_shift[0] = 0;
	1126	+ priv->col_shift[1] = 1;
	1127	+ priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
	1128	+ priv->col_shift[3] = ((addrmap[2] >> 8) &
	1129	+ COL_MAX_VAL_MASK) + COL_B3_BASE;
	1130	+ priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
	1131	+ COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
	1132	+ COL_MAX_VAL_MASK) + COL_B4_BASE);
	1133	+ priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
	1134	+ COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
	1135	+ COL_MAX_VAL_MASK) + COL_B5_BASE);
	1136	+ priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
	1137	+ COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
	1138	+ COL_MAX_VAL_MASK) + COL_B6_BASE);
	1139	+ priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
	1140	+ COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
	1141	+ COL_MAX_VAL_MASK) + COL_B7_BASE);
	1142	+ priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
	1143	+ COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
	1144	+ COL_MAX_VAL_MASK) + COL_B8_BASE);
	1145	+ priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
	1146	+ COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
	1147	+ COL_MAX_VAL_MASK) + COL_B9_BASE);
	1148	+ if (width == DDRCTL_EWDTH_64) {
	1149	+ if (memtype & MEM_TYPE_LPDDR3) {
	1150	+ priv->col_shift[10] = ((addrmap[4] &
	1151	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1152	+ ((addrmap[4] & COL_MAX_VAL_MASK) +
	1153	+ COL_B10_BASE);
	1154	+ priv->col_shift[11] = (((addrmap[4] >> 8) &
	1155	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1156	+ (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
	1157	+ COL_B11_BASE);
	1158	+ } else {
	1159	+ priv->col_shift[11] = ((addrmap[4] &
	1160	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1161	+ ((addrmap[4] & COL_MAX_VAL_MASK) +
	1162	+ COL_B10_BASE);
	1163	+ priv->col_shift[13] = (((addrmap[4] >> 8) &
	1164	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1165	+ (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
	1166	+ COL_B11_BASE);
	1167	+ }
	1168	+ } else if (width == DDRCTL_EWDTH_32) {
	1169	+ if (memtype & MEM_TYPE_LPDDR3) {
	1170	+ priv->col_shift[10] = (((addrmap[3] >> 24) &
	1171	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1172	+ (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
	1173	+ COL_B9_BASE);
	1174	+ priv->col_shift[11] = ((addrmap[4] &
	1175	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1176	+ ((addrmap[4] & COL_MAX_VAL_MASK) +
	1177	+ COL_B10_BASE);
	1178	+ } else {
	1179	+ priv->col_shift[11] = (((addrmap[3] >> 24) &
	1180	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1181	+ (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
	1182	+ COL_B9_BASE);
	1183	+ priv->col_shift[13] = ((addrmap[4] &
	1184	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1185	+ ((addrmap[4] & COL_MAX_VAL_MASK) +
	1186	+ COL_B10_BASE);
	1187	+ }
	1188	+ } else {
	1189	+ if (memtype & MEM_TYPE_LPDDR3) {
	1190	+ priv->col_shift[10] = (((addrmap[3] >> 16) &
	1191	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1192	+ (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
	1193	+ COL_B8_BASE);
	1194	+ priv->col_shift[11] = (((addrmap[3] >> 24) &
	1195	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1196	+ (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
	1197	+ COL_B9_BASE);
	1198	+ priv->col_shift[13] = ((addrmap[4] &
	1199	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1200	+ ((addrmap[4] & COL_MAX_VAL_MASK) +
	1201	+ COL_B10_BASE);
	1202	+ } else {
	1203	+ priv->col_shift[11] = (((addrmap[3] >> 16) &
	1204	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1205	+ (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
	1206	+ COL_B8_BASE);
	1207	+ priv->col_shift[13] = (((addrmap[3] >> 24) &
	1208	+ COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
	1209	+ (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
	1210	+ COL_B9_BASE);
	1211	+ }
	1212	+ }
	1213	+
	1214	+ if (width) {
	1215	+ for (index = 9; index > width; index--) {
	1216	+ priv->col_shift[index] = priv->col_shift[index - width];
	1217	+ priv->col_shift[index - width] = 0;
	1218	+ }
	1219	+ }
	1220	+
	1221	+}
	1222	+
	1223	+static void setup_bank_address_map(struct synps_edac_priv priv, u32 addrmap)
	1224	+{
	1225	+ priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
	1226	+ priv->bank_shift[1] = ((addrmap[1] >> 8) &
	1227	+ BANK_MAX_VAL_MASK) + BANK_B1_BASE;
	1228	+ priv->bank_shift[2] = (((addrmap[1] >> 16) &
	1229	+ BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
	1230	+ (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
	1231	+ BANK_B2_BASE);
	1232	+
	1233	+}
	1234	+
	1235	+static void setup_bg_address_map(struct synps_edac_priv priv, u32 addrmap)
	1236	+{
	1237	+ priv->bankgrp_shift[0] = (addrmap[8] &
	1238	+ BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
	1239	+ priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
	1240	+ BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
	1241	+ & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
	1242	+
	1243	+}
	1244	+
	1245	+static void setup_rank_address_map(struct synps_edac_priv priv, u32 addrmap)
	1246	+{
	1247	+ priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
	1248	+ RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
	1249	+ RANK_MAX_VAL_MASK) + RANK_B0_BASE);
424	1250	}
425	1251
426	1252	/**
427		- * synps_edac_mc_probe - Check controller and bind driver
428		- * @pdev: Pointer to the platform_device struct
	1253	+ * setup_address_map - Set Address Map by querying ADDRMAP registers.
	1254	+ * @priv: DDR memory controller private instance data.
429	1255	*
430		- * Probes a specific controller instance for binding with the driver.
	1256	+ * Set Address Map by querying ADDRMAP registers.
	1257	+ *
	1258	+ * Return: none.
	1259	+ */
	1260	+static void setup_address_map(struct synps_edac_priv *priv)
	1261	+{
	1262	+ u32 addrmap[12];
	1263	+ int index;
	1264	+
	1265	+ for (index = 0; index < 12; index++) {
	1266	+ u32 addrmap_offset;
	1267	+
	1268	+ addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
	1269	+ addrmap[index] = readl(priv->baseaddr + addrmap_offset);
	1270	+ }
	1271	+
	1272	+ setup_row_address_map(priv, addrmap);
	1273	+
	1274	+ setup_column_address_map(priv, addrmap);
	1275	+
	1276	+ setup_bank_address_map(priv, addrmap);
	1277	+
	1278	+ setup_bg_address_map(priv, addrmap);
	1279	+
	1280	+ setup_rank_address_map(priv, addrmap);
	1281	+}
	1282	+#endif /* CONFIG_EDAC_DEBUG */
	1283	+
	1284	+/**
	1285	+ * mc_probe - Check controller and bind driver.
	1286	+ * @pdev: platform device.
	1287	+ *
	1288	+ * Probe a specific controller instance for binding with the driver.
431	1289	*
432	1290	* Return: 0 if the controller instance was successfully bound to the
433	1291	* driver; otherwise, < 0 on error.
434	1292	*/
435		-static int synps_edac_mc_probe(struct platform_device *pdev)
	1293	+static int mc_probe(struct platform_device *pdev)
436	1294	{
437		- struct mem_ctl_info *mci;
	1295	+ const struct synps_platform_data *p_data;
438	1296	struct edac_mc_layer layers[2];
439	1297	struct synps_edac_priv *priv;
440		- int rc;
441		- struct resource *res;
	1298	+ struct mem_ctl_info *mci;
442	1299	void __iomem *baseaddr;
	1300	+ struct resource *res;
	1301	+ int rc;
443	1302
444	1303	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
445	1304	baseaddr = devm_ioremap_resource(&pdev->dev, res);
446	1305	if (IS_ERR(baseaddr))
447	1306	return PTR_ERR(baseaddr);
448	1307
449		- if (!synps_edac_get_eccstate(baseaddr)) {
	1308	+ p_data = of_device_get_match_data(&pdev->dev);
	1309	+ if (!p_data)
	1310	+ return -ENODEV;
	1311	+
	1312	+ if (!p_data->get_ecc_state(baseaddr)) {
450	1313	edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
451	1314	return -ENXIO;
452	1315	}
..	..	@@ -468,11 +1331,14 @@
468	1331
469	1332	priv = mci->pvt_info;
470	1333	priv->baseaddr = baseaddr;
471		- rc = synps_edac_mc_init(mci, pdev);
472		- if (rc) {
473		- edac_printk(KERN_ERR, EDAC_MC,
474		- "Failed to initialize instance\n");
475		- goto free_edac_mc;
	1334	+ priv->p_data = p_data;
	1335	+
	1336	+ mc_init(mci, pdev);
	1337	+
	1338	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
	1339	+ rc = setup_irq(mci, pdev);
	1340	+ if (rc)
	1341	+ goto free_edac_mc;
476	1342	}
477	1343
478	1344	rc = edac_mc_add_mc(mci);
..	..	@@ -482,11 +1348,26 @@
482	1348	goto free_edac_mc;
483	1349	}
484	1350
	1351	+#ifdef CONFIG_EDAC_DEBUG
	1352	+ if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
	1353	+ if (edac_create_sysfs_attributes(mci)) {
	1354	+ edac_printk(KERN_ERR, EDAC_MC,
	1355	+ "Failed to create sysfs entries\n");
	1356	+ goto free_edac_mc;
	1357	+ }
	1358	+ }
	1359	+
	1360	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
	1361	+ setup_address_map(priv);
	1362	+#endif
	1363	+
485	1364	/*
486	1365	* Start capturing the correctable and uncorrectable errors. A write of
487	1366	* 0 starts the counters.
488	1367	*/
489		- writel(0x0, baseaddr + ECC_CTRL_OFST);
	1368	+ if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
	1369	+ writel(0x0, baseaddr + ECC_CTRL_OFST);
	1370	+
490	1371	return rc;
491	1372
492	1373	free_edac_mc:
..	..	@@ -496,14 +1377,23 @@
496	1377	}
497	1378
498	1379	/**
499		- * synps_edac_mc_remove - Unbind driver from controller
500		- * @pdev: Pointer to the platform_device struct
	1380	+ * mc_remove - Unbind driver from controller.
	1381	+ * @pdev: Platform device.
501	1382	*
502	1383	* Return: Unconditionally 0
503	1384	*/
504		-static int synps_edac_mc_remove(struct platform_device *pdev)
	1385	+static int mc_remove(struct platform_device *pdev)
505	1386	{
506	1387	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	1388	+ struct synps_edac_priv *priv = mci->pvt_info;
	1389	+
	1390	+ if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
	1391	+ disable_intr(priv);
	1392	+
	1393	+#ifdef CONFIG_EDAC_DEBUG
	1394	+ if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
	1395	+ edac_remove_sysfs_attributes(mci);
	1396	+#endif
507	1397
508	1398	edac_mc_del_mc(&pdev->dev);
509	1399	edac_mc_free(mci);
..	..	@@ -511,20 +1401,13 @@
511	1401	return 0;
512	1402	}
513	1403
514		-static const struct of_device_id synps_edac_match[] = {
515		- { .compatible = "xlnx,zynq-ddrc-a05", },
516		- { /* end of table */ }
517		-};
518		-
519		-MODULE_DEVICE_TABLE(of, synps_edac_match);
520		-
521	1404	static struct platform_driver synps_edac_mc_driver = {
522	1405	.driver = {
523	1406	.name = "synopsys-edac",
524	1407	.of_match_table = synps_edac_match,
525	1408	},
526		- .probe = synps_edac_mc_probe,
527		- .remove = synps_edac_mc_remove,
	1409	+ .probe = mc_probe,
	1410	+ .remove = mc_remove,
528	1411	};
529	1412
530	1413	module_platform_driver(synps_edac_mc_driver);