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| 1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | 2 | /* |
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| 3 | + * Copyright (C) 2020-2022 MaxLinear, Inc. |
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| 3 | 4 | * Copyright (C) 2020 Intel Corporation. |
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| 4 | | - * Zhu YiXin <yixin.zhu@intel.com> |
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| 5 | | - * Rahul Tanwar <rahul.tanwar@intel.com> |
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| 5 | + * Zhu Yixin <yzhu@maxlinear.com> |
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| 6 | + * Rahul Tanwar <rtanwar@maxlinear.com> |
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| 6 | 7 | */ |
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| 7 | 8 | |
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| 8 | 9 | #include <linux/clk-provider.h> |
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| .. | .. |
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| 40 | 41 | { |
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| 41 | 42 | struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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| 42 | 43 | unsigned int div, mult, frac; |
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| 43 | | - unsigned long flags; |
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| 44 | 44 | |
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| 45 | | - spin_lock_irqsave(&pll->lock, flags); |
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| 46 | 45 | mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); |
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| 47 | 46 | div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); |
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| 48 | 47 | frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); |
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| 49 | | - spin_unlock_irqrestore(&pll->lock, flags); |
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| 50 | 48 | |
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| 51 | 49 | if (pll->type == TYPE_LJPLL) |
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| 52 | 50 | div *= 4; |
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| .. | .. |
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| 57 | 55 | static int lgm_pll_is_enabled(struct clk_hw *hw) |
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| 58 | 56 | { |
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| 59 | 57 | struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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| 60 | | - unsigned long flags; |
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| 61 | 58 | unsigned int ret; |
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| 62 | 59 | |
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| 63 | | - spin_lock_irqsave(&pll->lock, flags); |
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| 64 | 60 | ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); |
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| 65 | | - spin_unlock_irqrestore(&pll->lock, flags); |
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| 66 | 61 | |
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| 67 | 62 | return ret; |
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| 68 | 63 | } |
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| .. | .. |
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| 70 | 65 | static int lgm_pll_enable(struct clk_hw *hw) |
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| 71 | 66 | { |
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| 72 | 67 | struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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| 73 | | - unsigned long flags; |
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| 74 | 68 | u32 val; |
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| 75 | 69 | int ret; |
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| 76 | 70 | |
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| 77 | | - spin_lock_irqsave(&pll->lock, flags); |
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| 78 | 71 | lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); |
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| 79 | | - ret = readl_poll_timeout_atomic(pll->membase + pll->reg, |
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| 80 | | - val, (val & 0x1), 1, 100); |
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| 81 | | - spin_unlock_irqrestore(&pll->lock, flags); |
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| 72 | + ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg, |
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| 73 | + val, (val & 0x1), 1, 100); |
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| 74 | + |
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| 82 | 75 | |
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| 83 | 76 | return ret; |
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| 84 | 77 | } |
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| .. | .. |
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| 86 | 79 | static void lgm_pll_disable(struct clk_hw *hw) |
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| 87 | 80 | { |
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| 88 | 81 | struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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| 89 | | - unsigned long flags; |
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| 90 | 82 | |
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| 91 | | - spin_lock_irqsave(&pll->lock, flags); |
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| 92 | 83 | lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0); |
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| 93 | | - spin_unlock_irqrestore(&pll->lock, flags); |
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| 94 | 84 | } |
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| 95 | 85 | |
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| 96 | 86 | static const struct clk_ops lgm_pll_ops = { |
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| .. | .. |
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| 121 | 111 | return ERR_PTR(-ENOMEM); |
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| 122 | 112 | |
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| 123 | 113 | pll->membase = ctx->membase; |
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| 124 | | - pll->lock = ctx->lock; |
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| 125 | 114 | pll->reg = list->reg; |
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| 126 | 115 | pll->flags = list->flags; |
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| 127 | 116 | pll->type = list->type; |
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