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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/tegra/clk.h
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 	/*
23  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #ifndef __TEGRA_CLK_H
....@@ -20,6 +9,65 @@
209 #include <linux/clk-provider.h>
2110 #include <linux/clkdev.h>
2211 #include <linux/delay.h>
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+
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+#define CLK_OUT_ENB_L			0x010
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+#define CLK_OUT_ENB_H			0x014
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+#define CLK_OUT_ENB_U			0x018
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+#define CLK_OUT_ENB_V			0x360
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+#define CLK_OUT_ENB_W			0x364
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+#define CLK_OUT_ENB_X			0x280
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+#define CLK_OUT_ENB_Y			0x298
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+#define CLK_ENB_PLLP_OUT_CPU		BIT(31)
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+#define CLK_OUT_ENB_SET_L		0x320
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+#define CLK_OUT_ENB_CLR_L		0x324
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+#define CLK_OUT_ENB_SET_H		0x328
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+#define CLK_OUT_ENB_CLR_H		0x32c
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+#define CLK_OUT_ENB_SET_U		0x330
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+#define CLK_OUT_ENB_CLR_U		0x334
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+#define CLK_OUT_ENB_SET_V		0x440
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+#define CLK_OUT_ENB_CLR_V		0x444
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+#define CLK_OUT_ENB_SET_W		0x448
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+#define CLK_OUT_ENB_CLR_W		0x44c
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+#define CLK_OUT_ENB_SET_X		0x284
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+#define CLK_OUT_ENB_CLR_X		0x288
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+#define CLK_OUT_ENB_SET_Y		0x29c
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+#define CLK_OUT_ENB_CLR_Y		0x2a0
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+
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+#define RST_DEVICES_L			0x004
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+#define RST_DEVICES_H			0x008
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+#define RST_DEVICES_U			0x00C
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+#define RST_DEVICES_V			0x358
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+#define RST_DEVICES_W			0x35C
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+#define RST_DEVICES_X			0x28C
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+#define RST_DEVICES_Y			0x2a4
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+#define RST_DEVICES_SET_L		0x300
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+#define RST_DEVICES_CLR_L		0x304
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+#define RST_DEVICES_SET_H		0x308
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+#define RST_DEVICES_CLR_H		0x30c
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+#define RST_DEVICES_SET_U		0x310
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+#define RST_DEVICES_CLR_U		0x314
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+#define RST_DEVICES_SET_V		0x430
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+#define RST_DEVICES_CLR_V		0x434
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+#define RST_DEVICES_SET_W		0x438
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+#define RST_DEVICES_CLR_W		0x43c
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+#define RST_DEVICES_SET_X		0x290
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+#define RST_DEVICES_CLR_X		0x294
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+#define RST_DEVICES_SET_Y		0x2a8
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+#define RST_DEVICES_CLR_Y		0x2ac
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+
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+/*
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+ * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
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+ * any accidental write of 1 to these bits can cause PSLVERR.
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+ * So below are the valid mask defines for each CLK_OUT_ENB register used to
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+ * turn ON only the valid clocks.
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+ */
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+#define TEGRA210_CLK_ENB_VLD_MSK_L	0xdcd7dff9
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+#define TEGRA210_CLK_ENB_VLD_MSK_H	0x87d1f3e7
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+#define TEGRA210_CLK_ENB_VLD_MSK_U	0xf3fed3fa
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+#define TEGRA210_CLK_ENB_VLD_MSK_V	0xffc18cfb
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+#define TEGRA210_CLK_ENB_VLD_MSK_W	0x793fb7ff
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+#define TEGRA210_CLK_ENB_VLD_MSK_X	0x3fe66fff
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+#define TEGRA210_CLK_ENB_VLD_MSK_Y	0xfc1fc7ff
2371 
2472 /**
2573  * struct tegra_clk_sync_source - external clock source from codec
....@@ -218,6 +266,10 @@
218266  *				disabled.
219267  * @dyn_ramp:			Callback which can be used to define a custom
220268  *				dynamic ramp function for a given PLL.
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+ * @pre_rate_change:		Callback which is invoked just before changing
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+ *				PLL's rate.
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+ * @post_rate_change:		Callback which is invoked right after changing
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+ *				PLL's rate.
221273  *
222274  * Flags:
223275  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
....@@ -294,6 +346,8 @@
294346 	void	(*set_defaults)(struct tegra_clk_pll *pll);
295347 	int	(*dyn_ramp)(struct tegra_clk_pll *pll,
296348 			struct tegra_clk_pll_freq_table *cfg);
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+	int	(*pre_rate_change)(void);
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+	void	(*post_rate_change)(void);
297351 };
298352 
299353 #define TEGRA_PLL_USE_LOCK BIT(0)
....@@ -680,6 +734,11 @@
680734  * Flags:
681735  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
682736  *     that this is LP cluster clock.
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+ * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
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+ *     super mux parent using PLLP branches. To use PLLP branches to CPU, need
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+ *     to configure additional bit PLLP_OUT_CPU in the clock registers.
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+ * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
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+ *     clocks, it only has a clock-skipper.
683742  */
684743 struct tegra_clk_super_mux {
685744 	struct clk_hw	hw;
....@@ -696,6 +755,8 @@
696755 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
697756 
698757 #define TEGRA_DIVIDER_2 BIT(0)
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+#define TEGRA210_CPU_CLK BIT(1)
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+#define TEGRA20_SUPER_CLK BIT(2)
699760 
700761 extern const struct clk_ops tegra_clk_super_ops;
701762 struct clk *tegra_clk_register_super_mux(const char *name,
....@@ -706,6 +767,12 @@
706767 		const char * const *parent_names, u8 num_parents,
707768 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
708769 		spinlock_t *lock);
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+struct clk *tegra_clk_register_super_cclk(const char *name,
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+		const char * const *parent_names, u8 num_parents,
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+		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
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+		spinlock_t *lock);
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+int tegra_cclk_pre_pllx_rate_change(void);
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+void tegra_cclk_post_pllx_rate_change(void);
709776 
710777 /**
711778  * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
....@@ -802,7 +869,6 @@
802869 			struct tegra_clk *tegra_clks,
803870 			struct tegra_clk_pll_params *pll_params);
804871 
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-void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
806872 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
807873 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
808874 		       unsigned long *input_freqs, unsigned int num,
....@@ -815,7 +881,7 @@
815881 			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
816882 			struct tegra_clk_pll_params *pll_params);
817883 
818
-#ifdef CONFIG_TEGRA_CLK_EMC
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+#ifdef CONFIG_TEGRA124_EMC
819885 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
820886 				   spinlock_t *lock);
821887 #else
....@@ -840,6 +906,10 @@
840906 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
841907 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
842908 		 u8 frac_width, u8 flags);
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+void tegra_clk_osc_resume(void __iomem *clk_base);
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+void tegra_clk_set_pllp_out_cpu(bool enable);
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+void tegra_clk_periph_suspend(void);
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+void tegra_clk_periph_resume(void);
843913 
844914 
845915 /* Combined read fence with delay */
....@@ -849,4 +919,10 @@
849919 		udelay(delay);		\
850920 	} while (0)
851921 
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+bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw);
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+struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
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+
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+struct clk *tegra210_clk_register_emc(struct device_node *np,
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+				      void __iomem *regs);
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+
852928 #endif /* TEGRA_CLK_H */