修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/tegra/clk.c
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@@ -1,23 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/clkdev.h>
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 #include <linux/clk.h>
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 #include <linux/clk-provider.h>
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 #include <linux/delay.h>
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+#include <linux/io.h>
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 #include <linux/of.h>
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 #include <linux/clk/tegra.h>
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 #include <linux/reset-controller.h>
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@@ -26,56 +16,13 @@
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 #include "clk.h"
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-#define CLK_OUT_ENB_L			0x010
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-#define CLK_OUT_ENB_H			0x014
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-#define CLK_OUT_ENB_U			0x018
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-#define CLK_OUT_ENB_V			0x360
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-#define CLK_OUT_ENB_W			0x364
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-#define CLK_OUT_ENB_X			0x280
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-#define CLK_OUT_ENB_Y			0x298
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-#define CLK_OUT_ENB_SET_L		0x320
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-#define CLK_OUT_ENB_CLR_L		0x324
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-#define CLK_OUT_ENB_SET_H		0x328
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-#define CLK_OUT_ENB_CLR_H		0x32c
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-#define CLK_OUT_ENB_SET_U		0x330
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-#define CLK_OUT_ENB_CLR_U		0x334
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-#define CLK_OUT_ENB_SET_V		0x440
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-#define CLK_OUT_ENB_CLR_V		0x444
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-#define CLK_OUT_ENB_SET_W		0x448
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-#define CLK_OUT_ENB_CLR_W		0x44c
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-#define CLK_OUT_ENB_SET_X		0x284
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-#define CLK_OUT_ENB_CLR_X		0x288
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-#define CLK_OUT_ENB_SET_Y		0x29c
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-#define CLK_OUT_ENB_CLR_Y		0x2a0
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-
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-#define RST_DEVICES_L			0x004
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-#define RST_DEVICES_H			0x008
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-#define RST_DEVICES_U			0x00C
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-#define RST_DEVICES_V			0x358
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-#define RST_DEVICES_W			0x35C
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-#define RST_DEVICES_X			0x28C
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-#define RST_DEVICES_Y			0x2a4
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-#define RST_DEVICES_SET_L		0x300
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-#define RST_DEVICES_CLR_L		0x304
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-#define RST_DEVICES_SET_H		0x308
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-#define RST_DEVICES_CLR_H		0x30c
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-#define RST_DEVICES_SET_U		0x310
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-#define RST_DEVICES_CLR_U		0x314
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-#define RST_DEVICES_SET_V		0x430
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-#define RST_DEVICES_CLR_V		0x434
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-#define RST_DEVICES_SET_W		0x438
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-#define RST_DEVICES_CLR_W		0x43c
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-#define RST_DEVICES_SET_X		0x290
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-#define RST_DEVICES_CLR_X		0x294
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-#define RST_DEVICES_SET_Y		0x2a8
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-#define RST_DEVICES_CLR_Y		0x2ac
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-
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 /* Global data of Tegra CPU CAR ops */
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 static struct tegra_cpu_car_ops dummy_car_ops;
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 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
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 int *periph_clk_enb_refcnt;
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 static int periph_banks;
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+static u32 *periph_state_ctx;
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 static struct clk **clks;
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 static int clk_num;
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 static struct clk_onecell_data clk_data;
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@@ -209,6 +156,65 @@
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 	}
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 }
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+void tegra_clk_set_pllp_out_cpu(bool enable)
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+{
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+	u32 val;
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+
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+	val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
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+	if (enable)
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+		val |= CLK_ENB_PLLP_OUT_CPU;
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+	else
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+		val &= ~CLK_ENB_PLLP_OUT_CPU;
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+
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+	writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
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+}
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+
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+void tegra_clk_periph_suspend(void)
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+{
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+	unsigned int i, idx;
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+
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+	idx = 0;
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+	for (i = 0; i < periph_banks; i++, idx++)
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+		periph_state_ctx[idx] =
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+			readl_relaxed(clk_base + periph_regs[i].enb_reg);
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+
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+	for (i = 0; i < periph_banks; i++, idx++)
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+		periph_state_ctx[idx] =
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+			readl_relaxed(clk_base + periph_regs[i].rst_reg);
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+}
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+
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+void tegra_clk_periph_resume(void)
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+{
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+	unsigned int i, idx;
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+
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+	idx = 0;
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+	for (i = 0; i < periph_banks; i++, idx++)
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+		writel_relaxed(periph_state_ctx[idx],
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+			       clk_base + periph_regs[i].enb_reg);
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+	/*
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+	 * All non-boot peripherals will be in reset state on resume.
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+	 * Wait for 5us of reset propagation delay before de-asserting
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+	 * the peripherals based on the saved context.
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+	 */
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+	fence_udelay(5, clk_base);
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+
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+	for (i = 0; i < periph_banks; i++, idx++)
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+		writel_relaxed(periph_state_ctx[idx],
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+			       clk_base + periph_regs[i].rst_reg);
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+
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+	fence_udelay(2, clk_base);
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+}
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+
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+static int tegra_clk_periph_ctx_init(int banks)
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+{
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+	periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx),
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+				   GFP_KERNEL);
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+	if (!periph_state_ctx)
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+		return -ENOMEM;
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+
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+	return 0;
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+}
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+
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 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
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 {
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 	clk_base = regs;
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@@ -225,11 +231,21 @@
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 	periph_banks = banks;
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 	clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
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-	if (!clks)
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+	if (!clks) {
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 		kfree(periph_clk_enb_refcnt);
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+		return NULL;
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+	}
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 	clk_num = num;
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+	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
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+		if (tegra_clk_periph_ctx_init(banks)) {
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+			kfree(periph_clk_enb_refcnt);
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+			kfree(clks);
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+			return NULL;
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+		}
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+	}
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+
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 	return clks;
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 }
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