forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/tegra/clk-tegra-periph.c
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #include <linux/io.h>
....@@ -79,7 +68,6 @@
7968 #define CLK_SOURCE_3D 0x158
8069 #define CLK_SOURCE_2D 0x15c
8170 #define CLK_SOURCE_MPE 0x170
82
-#define CLK_SOURCE_UARTE 0x1c4
8371 #define CLK_SOURCE_VI_SENSOR 0x1a8
8472 #define CLK_SOURCE_VI 0x148
8573 #define CLK_SOURCE_EPP 0x16c
....@@ -117,8 +105,6 @@
117105 #define CLK_SOURCE_ISP 0x144
118106 #define CLK_SOURCE_SOR0 0x414
119107 #define CLK_SOURCE_DPAUX 0x418
120
-#define CLK_SOURCE_SATA_OOB 0x420
121
-#define CLK_SOURCE_SATA 0x424
122108 #define CLK_SOURCE_ENTROPY 0x628
123109 #define CLK_SOURCE_VI_SENSOR2 0x658
124110 #define CLK_SOURCE_HDMI_AUDIO 0x668
....@@ -276,7 +262,6 @@
276262 static DEFINE_SPINLOCK(PLLP_OUTA_lock);
277263 static DEFINE_SPINLOCK(PLLP_OUTB_lock);
278264 static DEFINE_SPINLOCK(PLLP_OUTC_lock);
279
-static DEFINE_SPINLOCK(sor0_lock);
280265 
281266 #define MUX_I2S_SPDIF(_id)						\
282267 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
....@@ -601,11 +586,6 @@
601586 	[0] = 0, [1] = 2, [2] = 3,
602587 };
603588 
604
-static const char *mux_clkm_plldp_sor0lvds[] = {
605
-	"clk_m", "pll_dp", "sor0_lvds",
606
-};
607
-#define mux_clkm_plldp_sor0lvds_idx NULL
608
-
609589 static const char * const mux_dmic1[] = {
610590 	"pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
611591 };
....@@ -745,14 +725,12 @@
745725 	MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
746726 	MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
747727 	MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
748
-	MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
749728 	MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
750729 	MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
751730 	NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
752731 	NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
753732 	NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
754733 	NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
755
-	NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
756734 	UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
757735 	UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
758736 	UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),