修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/tegra/clk-divider.c
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/kernel.h>
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@@ -51,8 +40,13 @@
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 	int div, mul;
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 	u64 rate = parent_rate;
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-	reg = readl_relaxed(divider->reg) >> divider->shift;
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-	div = reg & div_mask(divider);
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+	reg = readl_relaxed(divider->reg);
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+
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+	if ((divider->flags & TEGRA_DIVIDER_UART) &&
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+	    !(reg & PERIPH_CLK_UART_DIV_ENB))
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+		return rate;
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+
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+	div = (reg >> divider->shift) & div_mask(divider);
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 	mul = get_mul(divider);
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 	div += mul;
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@@ -120,10 +114,21 @@
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 	return 0;
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 }
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+static void clk_divider_restore_context(struct clk_hw *hw)
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+{
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+	struct clk_hw *parent = clk_hw_get_parent(hw);
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+	unsigned long parent_rate = clk_hw_get_rate(parent);
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+	unsigned long rate = clk_hw_get_rate(hw);
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+
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+	if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
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+		WARN_ON(1);
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+}
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+
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 const struct clk_ops tegra_clk_frac_div_ops = {
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 	.recalc_rate = clk_frac_div_recalc_rate,
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 	.set_rate = clk_frac_div_set_rate,
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 	.round_rate = clk_frac_div_round_rate,
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+	.restore_context = clk_divider_restore_context,
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 };
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 struct clk *tegra_clk_register_divider(const char *name,
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@@ -133,7 +138,7 @@
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 {
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 	struct tegra_clk_frac_div *divider;
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 	struct clk *clk;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	divider = kzalloc(sizeof(*divider), GFP_KERNEL);
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 	if (!divider) {
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@@ -175,6 +180,7 @@
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 				  void __iomem *reg, spinlock_t *lock)
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 {
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 	return clk_register_divider_table(NULL, name, parent_name,
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-					  CLK_IS_CRITICAL, reg, 16, 1, 0,
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+					  CLK_IS_CRITICAL,
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+					  reg, 16, 1, CLK_DIVIDER_READ_ONLY,
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 					  mc_div_table, lock);
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 }