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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
....@@ -1,20 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
34  *
45  * Based on ccu-sun8i-h3.c, which is:
56  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
6
- *
7
- * This software is licensed under the terms of the GNU General Public
8
- * License version 2, as published by the Free Software Foundation, and
9
- * may be copied, distributed, and modified under those terms.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
157  */
168 
179 #include <linux/clk-provider.h>
10
+#include <linux/io.h>
1811 #include <linux/of_address.h>
1912 
2013 #include "ccu_common.h"
....@@ -242,6 +235,8 @@
242235 		      0x068, BIT(0), 0);
243236 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
244237 		      0x068, BIT(5), 0);
238
+static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
239
+		      0x068, BIT(12), 0);
245240 
246241 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
247242 		      0x06c, BIT(0), 0);
....@@ -313,6 +308,11 @@
313308 				  BIT(31),	/* gate */
314309 				  0);
315310 
311
+static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
312
+					    "pll-audio-2x", "pll-audio" };
313
+static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
314
+			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
315
+
316316 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
317317 		      0x0cc, BIT(8), 0);
318318 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
....@@ -334,7 +334,8 @@
334334 
335335 static const char * const de_parents[] = { "pll-video", "pll-periph0" };
336336 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
337
-				 0x104, 0, 4, 24, 2, BIT(31), 0);
337
+				 0x104, 0, 4, 24, 2, BIT(31),
338
+				 CLK_SET_RATE_PARENT);
338339 
339340 static const char * const tcon_parents[] = { "pll-video" };
340341 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
....@@ -445,17 +446,100 @@
445446 	&mipi_csi_clk.common,
446447 };
447448 
449
+static const struct clk_hw *clk_parent_pll_audio[] = {
450
+	&pll_audio_base_clk.common.hw
451
+};
452
+
453
+static struct ccu_common *sun8i_v3_ccu_clks[] = {
454
+	&pll_cpu_clk.common,
455
+	&pll_audio_base_clk.common,
456
+	&pll_video_clk.common,
457
+	&pll_ve_clk.common,
458
+	&pll_ddr0_clk.common,
459
+	&pll_periph0_clk.common,
460
+	&pll_isp_clk.common,
461
+	&pll_periph1_clk.common,
462
+	&pll_ddr1_clk.common,
463
+	&cpu_clk.common,
464
+	&axi_clk.common,
465
+	&ahb1_clk.common,
466
+	&apb1_clk.common,
467
+	&apb2_clk.common,
468
+	&ahb2_clk.common,
469
+	&bus_ce_clk.common,
470
+	&bus_dma_clk.common,
471
+	&bus_mmc0_clk.common,
472
+	&bus_mmc1_clk.common,
473
+	&bus_mmc2_clk.common,
474
+	&bus_dram_clk.common,
475
+	&bus_emac_clk.common,
476
+	&bus_hstimer_clk.common,
477
+	&bus_spi0_clk.common,
478
+	&bus_otg_clk.common,
479
+	&bus_ehci0_clk.common,
480
+	&bus_ohci0_clk.common,
481
+	&bus_ve_clk.common,
482
+	&bus_tcon0_clk.common,
483
+	&bus_csi_clk.common,
484
+	&bus_de_clk.common,
485
+	&bus_codec_clk.common,
486
+	&bus_pio_clk.common,
487
+	&bus_i2s0_clk.common,
488
+	&bus_i2c0_clk.common,
489
+	&bus_i2c1_clk.common,
490
+	&bus_uart0_clk.common,
491
+	&bus_uart1_clk.common,
492
+	&bus_uart2_clk.common,
493
+	&bus_ephy_clk.common,
494
+	&bus_dbg_clk.common,
495
+	&mmc0_clk.common,
496
+	&mmc0_sample_clk.common,
497
+	&mmc0_output_clk.common,
498
+	&mmc1_clk.common,
499
+	&mmc1_sample_clk.common,
500
+	&mmc1_output_clk.common,
501
+	&mmc2_clk.common,
502
+	&mmc2_sample_clk.common,
503
+	&mmc2_output_clk.common,
504
+	&ce_clk.common,
505
+	&spi0_clk.common,
506
+	&i2s0_clk.common,
507
+	&usb_phy0_clk.common,
508
+	&usb_ohci0_clk.common,
509
+	&dram_clk.common,
510
+	&dram_ve_clk.common,
511
+	&dram_csi_clk.common,
512
+	&dram_ohci_clk.common,
513
+	&dram_ehci_clk.common,
514
+	&de_clk.common,
515
+	&tcon_clk.common,
516
+	&csi_misc_clk.common,
517
+	&csi0_mclk_clk.common,
518
+	&csi1_sclk_clk.common,
519
+	&csi1_mclk_clk.common,
520
+	&ve_clk.common,
521
+	&ac_dig_clk.common,
522
+	&avs_clk.common,
523
+	&mbus_clk.common,
524
+	&mipi_csi_clk.common,
525
+};
526
+
448527 /* We hardcode the divider to 4 for now */
449
-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
450
-			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
451
-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
452
-			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
453
-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
454
-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
455
-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
456
-			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
457
-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
458
-			"pll-periph0", 1, 2, 0);
528
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
529
+			    clk_parent_pll_audio,
530
+			    4, 1, CLK_SET_RATE_PARENT);
531
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
532
+			    clk_parent_pll_audio,
533
+			    2, 1, CLK_SET_RATE_PARENT);
534
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
535
+			    clk_parent_pll_audio,
536
+			    1, 1, CLK_SET_RATE_PARENT);
537
+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
538
+			    clk_parent_pll_audio,
539
+			    1, 2, CLK_SET_RATE_PARENT);
540
+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
541
+			   &pll_periph0_clk.common.hw,
542
+			   1, 2, 0);
459543 
460544 static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
461545 	.hws	= {
....@@ -534,7 +618,89 @@
534618 		[CLK_MBUS]		= &mbus_clk.common.hw,
535619 		[CLK_MIPI_CSI]		= &mipi_csi_clk.common.hw,
536620 	},
537
-	.num	= CLK_NUMBER,
621
+	.num	= CLK_PLL_DDR1 + 1,
622
+};
623
+
624
+static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
625
+	.hws	= {
626
+		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
627
+		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
628
+		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
629
+		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
630
+		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
631
+		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
632
+		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
633
+		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
634
+		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
635
+		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
636
+		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
637
+		[CLK_PLL_ISP]		= &pll_isp_clk.common.hw,
638
+		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
639
+		[CLK_PLL_DDR1]		= &pll_ddr1_clk.common.hw,
640
+		[CLK_CPU]		= &cpu_clk.common.hw,
641
+		[CLK_AXI]		= &axi_clk.common.hw,
642
+		[CLK_AHB1]		= &ahb1_clk.common.hw,
643
+		[CLK_APB1]		= &apb1_clk.common.hw,
644
+		[CLK_APB2]		= &apb2_clk.common.hw,
645
+		[CLK_AHB2]		= &ahb2_clk.common.hw,
646
+		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
647
+		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
648
+		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
649
+		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
650
+		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
651
+		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
652
+		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
653
+		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
654
+		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
655
+		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
656
+		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
657
+		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
658
+		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
659
+		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
660
+		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
661
+		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
662
+		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
663
+		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
664
+		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
665
+		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
666
+		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
667
+		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
668
+		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
669
+		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
670
+		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
671
+		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
672
+		[CLK_MMC0]		= &mmc0_clk.common.hw,
673
+		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
674
+		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
675
+		[CLK_MMC1]		= &mmc1_clk.common.hw,
676
+		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
677
+		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
678
+		[CLK_MMC2]		= &mmc2_clk.common.hw,
679
+		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
680
+		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
681
+		[CLK_CE]		= &ce_clk.common.hw,
682
+		[CLK_SPI0]		= &spi0_clk.common.hw,
683
+		[CLK_I2S0]		= &i2s0_clk.common.hw,
684
+		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
685
+		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
686
+		[CLK_DRAM]		= &dram_clk.common.hw,
687
+		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
688
+		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
689
+		[CLK_DRAM_EHCI]		= &dram_ehci_clk.common.hw,
690
+		[CLK_DRAM_OHCI]		= &dram_ohci_clk.common.hw,
691
+		[CLK_DE]		= &de_clk.common.hw,
692
+		[CLK_TCON0]		= &tcon_clk.common.hw,
693
+		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
694
+		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
695
+		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,
696
+		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
697
+		[CLK_VE]		= &ve_clk.common.hw,
698
+		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
699
+		[CLK_AVS]		= &avs_clk.common.hw,
700
+		[CLK_MBUS]		= &mbus_clk.common.hw,
701
+		[CLK_MIPI_CSI]		= &mipi_csi_clk.common.hw,
702
+	},
703
+	.num	= CLK_I2S0 + 1,
538704 };
539705 
540706 static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
....@@ -572,6 +738,42 @@
572738 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
573739 };
574740 
741
+static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
742
+	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
743
+
744
+	[RST_MBUS]		=  { 0x0fc, BIT(31) },
745
+
746
+	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
747
+	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
748
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
749
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
750
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
751
+	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
752
+	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
753
+	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
754
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
755
+	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
756
+	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(26) },
757
+	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(29) },
758
+
759
+	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
760
+	[RST_BUS_TCON0]		=  { 0x2c4, BIT(4) },
761
+	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
762
+	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
763
+	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
764
+
765
+	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
766
+
767
+	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
768
+	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
769
+
770
+	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
771
+	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
772
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
773
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
774
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
775
+};
776
+
575777 static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
576778 	.ccu_clks	= sun8i_v3s_ccu_clks,
577779 	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_ccu_clks),
....@@ -582,7 +784,18 @@
582784 	.num_resets	= ARRAY_SIZE(sun8i_v3s_ccu_resets),
583785 };
584786 
585
-static void __init sun8i_v3s_ccu_setup(struct device_node *node)
787
+static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
788
+	.ccu_clks	= sun8i_v3_ccu_clks,
789
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3_ccu_clks),
790
+
791
+	.hw_clks	= &sun8i_v3_hw_clks,
792
+
793
+	.resets		= sun8i_v3_ccu_resets,
794
+	.num_resets	= ARRAY_SIZE(sun8i_v3_ccu_resets),
795
+};
796
+
797
+static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
798
+					 const struct sunxi_ccu_desc *ccu_desc)
586799 {
587800 	void __iomem *reg;
588801 	u32 val;
....@@ -598,7 +811,21 @@
598811 	val &= ~GENMASK(19, 16);
599812 	writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
600813 
601
-	sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc);
814
+	sunxi_ccu_probe(node, reg, ccu_desc);
602815 }
816
+
817
+static void __init sun8i_v3s_ccu_setup(struct device_node *node)
818
+{
819
+	sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
820
+}
821
+
822
+static void __init sun8i_v3_ccu_setup(struct device_node *node)
823
+{
824
+	sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
825
+}
826
+
603827 CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
604828 	       sun8i_v3s_ccu_setup);
829
+
830
+CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
831
+	       sun8i_v3_ccu_setup);