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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
3
- *
4
- * This software is licensed under the terms of the GNU General Public
5
- * License version 2, as published by the Free Software Foundation, and
6
- * may be copied, distributed, and modified under those terms.
7
- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk.h>
....@@ -31,6 +23,8 @@
3123 		      0x04, BIT(1), 0);
3224 static SUNXI_CCU_GATE(bus_wb_clk,	"bus-wb",	"bus-de",
3325 		      0x04, BIT(2), 0);
26
+static SUNXI_CCU_GATE(bus_rot_clk,	"bus-rot",	"bus-de",
27
+		      0x04, BIT(3), 0);
3428 
3529 static SUNXI_CCU_GATE(mixer0_clk,	"mixer0",	"mixer0-div",
3630 		      0x00, BIT(0), CLK_SET_RATE_PARENT);
....@@ -38,6 +32,8 @@
3832 		      0x00, BIT(1), CLK_SET_RATE_PARENT);
3933 static SUNXI_CCU_GATE(wb_clk,		"wb",		"wb-div",
4034 		      0x00, BIT(2), CLK_SET_RATE_PARENT);
35
+static SUNXI_CCU_GATE(rot_clk,		"rot",		"rot-div",
36
+		      0x00, BIT(3), CLK_SET_RATE_PARENT);
4137 
4238 static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
4339 		   CLK_SET_RATE_PARENT);
....@@ -45,12 +41,16 @@
4541 		   CLK_SET_RATE_PARENT);
4642 static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
4743 		   CLK_SET_RATE_PARENT);
44
+static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4,
45
+		   CLK_SET_RATE_PARENT);
4846 
4947 static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
5048 		   CLK_SET_RATE_PARENT);
5149 static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
5250 		   CLK_SET_RATE_PARENT);
5351 static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
52
+		   CLK_SET_RATE_PARENT);
53
+static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
5454 		   CLK_SET_RATE_PARENT);
5555 
5656 static struct ccu_common *sun8i_a83t_de2_clks[] = {
....@@ -65,6 +65,10 @@
6565 	&mixer0_div_a83_clk.common,
6666 	&mixer1_div_a83_clk.common,
6767 	&wb_div_a83_clk.common,
68
+
69
+	&bus_rot_clk.common,
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+	&rot_clk.common,
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+	&rot_div_a83_clk.common,
6872 };
6973 
7074 static struct ccu_common *sun8i_h3_de2_clks[] = {
....@@ -92,21 +96,42 @@
9296 	&wb_div_clk.common,
9397 };
9498 
99
+static struct ccu_common *sun50i_a64_de2_clks[] = {
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+	&mixer0_clk.common,
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+	&mixer1_clk.common,
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+	&wb_clk.common,
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+
104
+	&bus_mixer0_clk.common,
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+	&bus_mixer1_clk.common,
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+	&bus_wb_clk.common,
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+
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+	&mixer0_div_clk.common,
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+	&mixer1_div_clk.common,
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+	&wb_div_clk.common,
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+
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+	&bus_rot_clk.common,
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+	&rot_clk.common,
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+	&rot_div_clk.common,
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+};
116
+
95117 static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
96118 	.hws	= {
97119 		[CLK_MIXER0]		= &mixer0_clk.common.hw,
98120 		[CLK_MIXER1]		= &mixer1_clk.common.hw,
99121 		[CLK_WB]		= &wb_clk.common.hw,
122
+		[CLK_ROT]		= &rot_clk.common.hw,
100123 
101124 		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
102125 		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
103126 		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
127
+		[CLK_BUS_ROT]		= &bus_rot_clk.common.hw,
104128 
105129 		[CLK_MIXER0_DIV]	= &mixer0_div_a83_clk.common.hw,
106130 		[CLK_MIXER1_DIV]	= &mixer1_div_a83_clk.common.hw,
107131 		[CLK_WB_DIV]		= &wb_div_a83_clk.common.hw,
132
+		[CLK_ROT_DIV]		= &rot_div_a83_clk.common.hw,
108133 	},
109
-	.num	= CLK_NUMBER,
134
+	.num	= CLK_NUMBER_WITH_ROT,
110135 };
111136 
112137 static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
....@@ -123,7 +148,7 @@
123148 		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
124149 		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
125150 	},
126
-	.num	= CLK_NUMBER,
151
+	.num	= CLK_NUMBER_WITHOUT_ROT,
127152 };
128153 
129154 static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
....@@ -137,20 +162,57 @@
137162 		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
138163 		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
139164 	},
140
-	.num	= CLK_NUMBER,
165
+	.num	= CLK_NUMBER_WITHOUT_ROT,
166
+};
167
+
168
+static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
169
+	.hws	= {
170
+		[CLK_MIXER0]		= &mixer0_clk.common.hw,
171
+		[CLK_MIXER1]		= &mixer1_clk.common.hw,
172
+		[CLK_WB]		= &wb_clk.common.hw,
173
+		[CLK_ROT]		= &rot_clk.common.hw,
174
+
175
+		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
176
+		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
177
+		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
178
+		[CLK_BUS_ROT]		= &bus_rot_clk.common.hw,
179
+
180
+		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
181
+		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
182
+		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
183
+		[CLK_ROT_DIV]		= &rot_div_clk.common.hw,
184
+	},
185
+	.num	= CLK_NUMBER_WITH_ROT,
141186 };
142187 
143188 static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
144189 	[RST_MIXER0]	= { 0x08, BIT(0) },
145190 	/*
146
-	 * For A83T, H3 and R40, mixer1 reset line is shared with wb, so
147
-	 * only RST_WB is exported here.
148
-	 * For V3s there's just no mixer1, so it also shares this struct.
191
+	 * Mixer1 reset line is shared with wb, so only RST_WB is
192
+	 * exported here.
193
+	 */
194
+	[RST_WB]	= { 0x08, BIT(2) },
195
+	[RST_ROT]	= { 0x08, BIT(3) },
196
+};
197
+
198
+static struct ccu_reset_map sun8i_h3_de2_resets[] = {
199
+	[RST_MIXER0]	= { 0x08, BIT(0) },
200
+	/*
201
+	 * Mixer1 reset line is shared with wb, so only RST_WB is
202
+	 * exported here.
203
+	 * V3s doesn't have mixer1, so it also shares this struct.
149204 	 */
150205 	[RST_WB]	= { 0x08, BIT(2) },
151206 };
152207 
153208 static struct ccu_reset_map sun50i_a64_de2_resets[] = {
209
+	[RST_MIXER0]	= { 0x08, BIT(0) },
210
+	[RST_MIXER1]	= { 0x08, BIT(1) },
211
+	[RST_WB]	= { 0x08, BIT(2) },
212
+	[RST_ROT]	= { 0x08, BIT(3) },
213
+};
214
+
215
+static struct ccu_reset_map sun50i_h5_de2_resets[] = {
154216 	[RST_MIXER0]	= { 0x08, BIT(0) },
155217 	[RST_MIXER1]	= { 0x08, BIT(1) },
156218 	[RST_WB]	= { 0x08, BIT(2) },
....@@ -172,18 +234,18 @@
172234 
173235 	.hw_clks	= &sun8i_h3_de2_hw_clks,
174236 
175
-	.resets		= sun8i_a83t_de2_resets,
176
-	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
237
+	.resets		= sun8i_h3_de2_resets,
238
+	.num_resets	= ARRAY_SIZE(sun8i_h3_de2_resets),
177239 };
178240 
179
-static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
180
-	.ccu_clks	= sun8i_h3_de2_clks,
181
-	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
241
+static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
242
+	.ccu_clks	= sun50i_a64_de2_clks,
243
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
182244 
183
-	.hw_clks	= &sun8i_h3_de2_hw_clks,
245
+	.hw_clks	= &sun50i_a64_de2_hw_clks,
184246 
185
-	.resets		= sun50i_a64_de2_resets,
186
-	.num_resets	= ARRAY_SIZE(sun50i_a64_de2_resets),
247
+	.resets		= sun8i_a83t_de2_resets,
248
+	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
187249 };
188250 
189251 static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
....@@ -194,6 +256,26 @@
194256 
195257 	.resets		= sun8i_a83t_de2_resets,
196258 	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
259
+};
260
+
261
+static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
262
+	.ccu_clks	= sun50i_a64_de2_clks,
263
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
264
+
265
+	.hw_clks	= &sun50i_a64_de2_hw_clks,
266
+
267
+	.resets		= sun50i_a64_de2_resets,
268
+	.num_resets	= ARRAY_SIZE(sun50i_a64_de2_resets),
269
+};
270
+
271
+static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
272
+	.ccu_clks	= sun8i_h3_de2_clks,
273
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
274
+
275
+	.hw_clks	= &sun8i_h3_de2_hw_clks,
276
+
277
+	.resets		= sun50i_h5_de2_resets,
278
+	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
197279 };
198280 
199281 static int sunxi_de2_clk_probe(struct platform_device *pdev)
....@@ -285,6 +367,10 @@
285367 		.data = &sun8i_h3_de2_clk_desc,
286368 	},
287369 	{
370
+		.compatible = "allwinner,sun8i-r40-de2-clk",
371
+		.data = &sun8i_r40_de2_clk_desc,
372
+	},
373
+	{
288374 		.compatible = "allwinner,sun8i-v3s-de2-clk",
289375 		.data = &sun8i_v3s_de2_clk_desc,
290376 	},
....@@ -294,7 +380,11 @@
294380 	},
295381 	{
296382 		.compatible = "allwinner,sun50i-h5-de2-clk",
297
-		.data = &sun50i_a64_de2_clk_desc,
383
+		.data = &sun50i_h5_de2_clk_desc,
384
+	},
385
+	{
386
+		.compatible = "allwinner,sun50i-h6-de3-clk",
387
+		.data = &sun50i_h5_de2_clk_desc,
298388 	},
299389 	{ }
300390 };