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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
....@@ -1,17 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3
- *
4
- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
124  */
135 
146 #include <linux/clk-provider.h>
7
+#include <linux/io.h>
158 #include <linux/of_address.h>
169 #include <linux/platform_device.h>
1710 
....@@ -51,30 +44,43 @@
5144  * the base (2x, 4x and 8x), and one variable divider (the one true
5245  * pll audio).
5346  *
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- * We don't have any need for the variable divider for now, so we just
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- * hardcode it to match with the clock names
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+ * With sigma-delta modulation for fractional-N on the audio PLL,
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+ * we have to use specific dividers. This means the variable divider
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+ * can no longer be used, as the audio codec requests the exact clock
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+ * rates we support through this mechanism. So we now hard code the
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+ * variable divider to 1. This means the clock rates will no longer
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+ * match the clock names.
5653  */
5754 #define SUN50I_A64_PLL_AUDIO_REG	0x008
5855 
59
-static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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-				   "osc24M", 0x008,
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-				   8, 7,	/* N */
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-				   0, 5,	/* M */
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-				   BIT(31),	/* gate */
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-				   BIT(28),	/* lock */
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-				   CLK_SET_RATE_UNGATE);
56
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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+	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
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+	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
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+};
6660 
67
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
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-					"osc24M", 0x010,
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-					8, 7,		/* N */
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-					0, 4,		/* M */
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-					BIT(24),	/* frac enable */
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-					BIT(25),	/* frac select */
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-					270000000,	/* frac rate 0 */
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-					297000000,	/* frac rate 1 */
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-					BIT(31),	/* gate */
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-					BIT(28),	/* lock */
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-					CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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+				       "osc24M", 0x008,
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+				       8, 7,	/* N */
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+				       0, 5,	/* M */
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+				       pll_audio_sdm_table, BIT(24),
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+				       0x284, BIT(31),
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+				       BIT(31),	/* gate */
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+				       BIT(28),	/* lock */
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+				       CLK_SET_RATE_UNGATE);
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+
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
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+						"osc24M", 0x010,
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+						192000000,	/* Minimum rate */
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+						1008000000,	/* Maximum rate */
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+						8, 7,		/* N */
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+						0, 4,		/* M */
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+						BIT(24),	/* frac enable */
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+						BIT(25),	/* frac select */
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+						270000000,	/* frac rate 0 */
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+						297000000,	/* frac rate 1 */
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+						BIT(31),	/* gate */
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+						BIT(28),	/* lock */
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+						CLK_SET_RATE_UNGATE);
7884 
7985 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
8086 					"osc24M", 0x018,
....@@ -125,17 +131,19 @@
125131 	},
126132 };
127133 
128
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
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-					"osc24M", 0x030,
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-					8, 7,		/* N */
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-					0, 4,		/* M */
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-					BIT(24),	/* frac enable */
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-					BIT(25),	/* frac select */
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-					270000000,	/* frac rate 0 */
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-					297000000,	/* frac rate 1 */
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-					BIT(31),	/* gate */
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-					BIT(28),	/* lock */
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-					CLK_SET_RATE_UNGATE);
134
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
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+						"osc24M", 0x030,
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+						192000000,	/* Minimum rate */
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+						1008000000,	/* Maximum rate */
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+						8, 7,		/* N */
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+						0, 4,		/* M */
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+						BIT(24),	/* frac enable */
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+						BIT(25),	/* frac select */
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+						270000000,	/* frac rate 0 */
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+						297000000,	/* frac rate 1 */
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+						BIT(31),	/* gate */
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+						BIT(28),	/* lock */
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+						CLK_SET_RATE_UNGATE);
139147 
140148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
141149 					"osc24M", 0x038,
....@@ -517,7 +525,8 @@
517525 
518526 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
519527 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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-				 0x104, 0, 4, 24, 3, BIT(31), 0);
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+				 0x104, 0, 4, 24, 3, BIT(31),
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+				 CLK_SET_RATE_PARENT);
521530 
522531 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
523532 static const u8 tcon0_table[] = { 0, 2, };
....@@ -556,7 +565,7 @@
556565 				 0x134, 0, 5, 8, 3, BIT(15), 0);
557566 
558567 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
559
-			     0x13c, 16, 3, BIT(31), 0);
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+			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
560569 
561570 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
562571 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
....@@ -589,23 +598,34 @@
589598 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
590599 
591600 /* Fixed Factor clocks */
592
-static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
601
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
593602 
594
-/* We hardcode the divider to 4 for now */
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-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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-			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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-			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
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-			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
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-			"pll-periph0", 1, 2, 0);
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-static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
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-			"pll-periph1", 1, 2, 0);
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-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
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-			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
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+static const struct clk_hw *clk_parent_pll_audio[] = {
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+	&pll_audio_base_clk.common.hw
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+};
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+
607
+/* We hardcode the divider to 1 for now */
608
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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+			    clk_parent_pll_audio,
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+			    2, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
618
+			    clk_parent_pll_audio,
619
+			    1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
621
+			   &pll_periph0_clk.common.hw,
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+			   1, 2, 0);
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+static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
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+			   &pll_periph1_clk.common.hw,
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+			   1, 2, 0);
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+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
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+			   &pll_video0_clk.common.hw,
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+			   1, 2, CLK_SET_RATE_PARENT);
609629 
610630 static struct ccu_common *sun50i_a64_ccu_clks[] = {
611631 	&pll_cpux_clk.common,
....@@ -928,10 +948,10 @@
928948 	if (IS_ERR(reg))
929949 		return PTR_ERR(reg);
930950 
931
-	/* Force the PLL-Audio-1x divider to 4 */
951
+	/* Force the PLL-Audio-1x divider to 1 */
932952 	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
933953 	val &= ~GENMASK(19, 16);
934
-	writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
954
+	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
935955 
936956 	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
937957