修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
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@@ -1,19 +1,12 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
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  * Copyright (c) 2017 Maxime Ripard.
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  * Copyright (c) 2017 Jonathan Liu.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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 #include <linux/of_address.h>
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 #include "ccu_common.h"
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@@ -167,8 +160,9 @@
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 	},
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 };
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-static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
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-			2, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
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+			   &pll_periph_base_clk.common.hw,
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+			   2, 1, CLK_SET_RATE_PARENT);
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 /* Not documented on A10 */
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 static struct ccu_div pll_periph_sata_clk = {
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@@ -1035,19 +1029,29 @@
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 	&out_b_clk.common
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 };
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+static const struct clk_hw *clk_parent_pll_audio[] = {
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+	&pll_audio_base_clk.common.hw
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+};
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+
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 /* Post-divider for pll-audio is hardcoded to 1 */
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-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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-			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
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-			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
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-			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
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-			"pll-video1", 1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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+			    clk_parent_pll_audio,
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+			    2, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
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+			    clk_parent_pll_audio,
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+			    1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
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+			   &pll_video0_clk.common.hw,
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+			   1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
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+			   &pll_video1_clk.common.hw,
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+			   1, 2, CLK_SET_RATE_PARENT);
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 static struct clk_hw_onecell_data sun4i_a10_hw_clks = {