| .. | .. |
|---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
|---|
| 1 | 2 | /* |
|---|
| 2 | 3 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
|---|
| 3 | 4 | * Author: Tarek Dakhran <t.dakhran@samsung.com> |
|---|
| 4 | | - * |
|---|
| 5 | | - * This program is free software; you can redistribute it and/or modify |
|---|
| 6 | | - * it under the terms of the GNU General Public License version 2 as |
|---|
| 7 | | - * published by the Free Software Foundation. |
|---|
| 8 | 5 | * |
|---|
| 9 | 6 | * Common Clock Framework support for Exynos5410 SoC. |
|---|
| 10 | 7 | */ |
|---|
| .. | .. |
|---|
| 209 | 206 | GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), |
|---|
| 210 | 207 | GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), |
|---|
| 211 | 208 | GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), |
|---|
| 209 | + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), |
|---|
| 212 | 210 | GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), |
|---|
| 213 | 211 | |
|---|
| 214 | 212 | GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", |
|---|