修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/samsung/clk-exynos5-subcmu.c
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@@ -4,6 +4,7 @@
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 // Author: Marek Szyprowski <m.szyprowski@samsung.com>
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 // Common Clock Framework support for Exynos5 power-domain dependent clocks
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+#include <linux/io.h>
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 #include <linux/of_platform.h>
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 #include <linux/platform_device.h>
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 #include <linux/pm_domain.h>
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@@ -13,7 +14,7 @@
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 #include "clk-exynos5-subcmu.h"
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 static struct samsung_clk_provider *ctx;
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-static const struct exynos5_subcmu_info *cmu;
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+static const struct exynos5_subcmu_info **cmu;
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 static int nr_cmus;
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 static void exynos5_subcmu_clk_save(void __iomem *base,
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@@ -55,17 +56,17 @@
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  * when OF-core populates all device-tree nodes.
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  */
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 void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
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-			  const struct exynos5_subcmu_info *_cmu)
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+			  const struct exynos5_subcmu_info **_cmu)
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 {
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 	ctx = _ctx;
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 	cmu = _cmu;
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 	nr_cmus = _nr_cmus;
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 	for (; _nr_cmus--; _cmu++) {
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-		exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks,
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-					  _cmu->nr_gate_clks);
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-		exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs,
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-					_cmu->nr_suspend_regs);
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+		exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
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+					  (*_cmu)->nr_gate_clks);
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+		exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
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+					(*_cmu)->nr_suspend_regs);
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 	}
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 }
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@@ -162,9 +163,9 @@
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 		if (of_property_read_string(np, "label", &name) < 0)
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 			continue;
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 		for (i = 0; i < nr_cmus; i++)
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-			if (strcmp(cmu[i].pd_name, name) == 0)
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+			if (strcmp(cmu[i]->pd_name, name) == 0)
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 				exynos5_clk_register_subcmu(&pdev->dev,
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-							    &cmu[i], np);
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+							    cmu[i], np);
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 	}
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 	return 0;
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 }