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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify |
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| 5 | | - * it under the terms of the GNU General Public License version 2 as |
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| 6 | | - * published by the Free Software Foundation. |
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| 7 | 4 | * |
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| 8 | 5 | * Common Clock Framework support for all PLL's in Samsung platforms |
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| 9 | 6 | */ |
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| .. | .. |
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| 49 | 46 | */ |
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| 50 | 47 | struct exynos_cpuclk { |
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| 51 | 48 | struct clk_hw hw; |
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| 52 | | - struct clk_hw *alt_parent; |
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| 49 | + const struct clk_hw *alt_parent; |
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| 53 | 50 | void __iomem *ctrl_base; |
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| 54 | 51 | spinlock_t *lock; |
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| 55 | 52 | const struct exynos_cpuclk_cfg_data *cfg; |
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| .. | .. |
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| 65 | 62 | #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) |
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| 66 | 63 | }; |
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| 67 | 64 | |
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| 68 | | -extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, |
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| 65 | +int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, |
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| 69 | 66 | unsigned int lookup_id, const char *name, |
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| 70 | | - const char *parent, const char *alt_parent, |
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| 67 | + const struct clk_hw *parent, const struct clk_hw *alt_parent, |
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| 71 | 68 | unsigned long offset, |
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| 72 | 69 | const struct exynos_cpuclk_cfg_data *cfg, |
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| 73 | 70 | unsigned long num_cfgs, unsigned long flags); |
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