forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/rockchip/clk-rk3562.c
....@@ -137,7 +137,7 @@
137137 		     0, RK3562_PMU1_PLL_CON(0),
138138 		     RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates),
139139 	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
140
-		     0, RK3562_SUBDDR_PLL_CON(0),
140
+		     CLK_IS_CRITICAL, RK3562_SUBDDR_PLL_CON(0),
141141 		     RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL),
142142 };
143143 
....@@ -624,7 +624,7 @@
624624 	COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
625625 			RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
626626 			RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS),
627
-	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3", CLK_SET_RATE_PARENT,
627
+	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
628628 			RK3562_PERI_CLKSEL_CON(26), 0,
629629 			RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS,
630630 			&rk3562_clk_uart3_fracmux),
....@@ -1011,10 +1011,10 @@
10111011 			RK3562_CLKGATE_CON(13), 6, GFLAGS),
10121012 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0,
10131013 			RK3562_CLKGATE_CON(13), 7, GFLAGS),
1014
-	COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1014
+	COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT,
10151015 			RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS,
10161016 			RK3562_CLKGATE_CON(13), 8, GFLAGS),
1017
-	COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1017
+	COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT,
10181018 			RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS,
10191019 			RK3562_CLKGATE_CON(13), 9, GFLAGS),
10201020 };