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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/renesas/renesas-cpg-mssr.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Renesas Clock Pulse Generator / Module Standby and Software Reset
34  *
....@@ -7,10 +8,6 @@
78  *
89  * Copyright (C) 2013 Ideas On Board SPRL
910  * Copyright (C) 2015 Renesas Electronics Corp.
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License as published by
13
- * the Free Software Foundation; version 2 of the License.
1411  */
1512 
1613 #include <linux/clk.h>
....@@ -19,6 +16,7 @@
1916 #include <linux/delay.h>
2017 #include <linux/device.h>
2118 #include <linux/init.h>
19
+#include <linux/io.h>
2220 #include <linux/mod_devicetable.h>
2321 #include <linux/module.h>
2422 #include <linux/of_address.h>
....@@ -59,8 +57,10 @@
5957 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
6058 };
6159 
62
-#define	MSTPSR(i)	mstpsr[i]
63
-
60
+static const u16 mstpsr_for_v3u[] = {
61
+	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62
+	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
63
+};
6464 
6565 /*
6666  * System Module Stop Control Register offsets
....@@ -71,8 +71,20 @@
7171 	0x990, 0x994, 0x998, 0x99C,
7272 };
7373 
74
-#define	SMSTPCR(i)	smstpcr[i]
74
+static const u16 mstpcr_for_v3u[] = {
75
+	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76
+	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
77
+};
7578 
79
+/*
80
+ * Standby Control Register offsets (RZ/A)
81
+ * Base address is FRQCR register
82
+ */
83
+
84
+static const u16 stbcr[] = {
85
+	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
86
+	0x424, 0x428, 0x42C,
87
+};
7688 
7789 /*
7890  * Software Reset Register offsets
....@@ -83,8 +95,10 @@
8395 	0x920, 0x924, 0x928, 0x92C,
8496 };
8597 
86
-#define	SRCR(i)		srcr[i]
87
-
98
+static const u16 srcr_for_v3u[] = {
99
+	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100
+	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
101
+};
88102 
89103 /* Realtime Module Stop Control Register offsets */
90104 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
....@@ -93,8 +107,16 @@
93107 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
94108 
95109 /* Software Reset Clearing Register offsets */
96
-#define	SRSTCLR(i)	(0x940 + (i) * 4)
97110 
111
+static const u16 srstclr[] = {
112
+	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
113
+	0x960, 0x964, 0x968, 0x96C,
114
+};
115
+
116
+static const u16 srstclr_for_v3u[] = {
117
+	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
118
+	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
119
+};
98120 
99121 /**
100122  * Clock Pulse Generator / Module Standby and Software Reset Private Data
....@@ -102,14 +124,20 @@
102124  * @rcdev: Optional reset controller entity
103125  * @dev: CPG/MSSR device
104126  * @base: CPG/MSSR register block base address
127
+ * @reg_layout: CPG/MSSR register layout
105128  * @rmw_lock: protects RMW register accesses
106
- * @clks: Array containing all Core and Module Clocks
129
+ * @np: Device node in DT for this CPG/MSSR module
107130  * @num_core_clks: Number of Core Clocks in clks[]
108131  * @num_mod_clks: Number of Module Clocks in clks[]
109132  * @last_dt_core_clk: ID of the last Core Clock exported to DT
110133  * @notifiers: Notifier chain to save/restore clock state for system resume
134
+ * @status_regs: Pointer to status registers array
135
+ * @control_regs: Pointer to control registers array
136
+ * @reset_regs: Pointer to reset registers array
137
+ * @reset_clear_regs:  Pointer to reset clearing registers array
111138  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
112139  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
140
+ * @clks: Array containing all Core and Module Clocks
113141  */
114142 struct cpg_mssr_priv {
115143 #ifdef CONFIG_RESET_CONTROLLER
....@@ -117,20 +145,28 @@
117145 #endif
118146 	struct device *dev;
119147 	void __iomem *base;
148
+	enum clk_reg_layout reg_layout;
120149 	spinlock_t rmw_lock;
150
+	struct device_node *np;
121151 
122
-	struct clk **clks;
123152 	unsigned int num_core_clks;
124153 	unsigned int num_mod_clks;
125154 	unsigned int last_dt_core_clk;
126155 
127156 	struct raw_notifier_head notifiers;
157
+	const u16 *status_regs;
158
+	const u16 *control_regs;
159
+	const u16 *reset_regs;
160
+	const u16 *reset_clear_regs;
128161 	struct {
129162 		u32 mask;
130163 		u32 val;
131
-	} smstpcr_saved[ARRAY_SIZE(smstpcr)];
164
+	} smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
165
+
166
+	struct clk *clks[];
132167 };
133168 
169
+static struct cpg_mssr_priv *cpg_mssr_priv;
134170 
135171 /**
136172  * struct mstp_clock - MSTP gating clock
....@@ -162,27 +198,40 @@
162198 		enable ? "ON" : "OFF");
163199 	spin_lock_irqsave(&priv->rmw_lock, flags);
164200 
165
-	value = readl(priv->base + SMSTPCR(reg));
166
-	if (enable)
167
-		value &= ~bitmask;
168
-	else
169
-		value |= bitmask;
170
-	writel(value, priv->base + SMSTPCR(reg));
201
+	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
202
+		value = readb(priv->base + priv->control_regs[reg]);
203
+		if (enable)
204
+			value &= ~bitmask;
205
+		else
206
+			value |= bitmask;
207
+		writeb(value, priv->base + priv->control_regs[reg]);
208
+
209
+		/* dummy read to ensure write has completed */
210
+		readb(priv->base + priv->control_regs[reg]);
211
+		barrier_data(priv->base + priv->control_regs[reg]);
212
+	} else {
213
+		value = readl(priv->base + priv->control_regs[reg]);
214
+		if (enable)
215
+			value &= ~bitmask;
216
+		else
217
+			value |= bitmask;
218
+		writel(value, priv->base + priv->control_regs[reg]);
219
+	}
171220 
172221 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
173222 
174
-	if (!enable)
223
+	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
175224 		return 0;
176225 
177226 	for (i = 1000; i > 0; --i) {
178
-		if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
227
+		if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
179228 			break;
180229 		cpu_relax();
181230 	}
182231 
183232 	if (!i) {
184233 		dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
185
-			priv->base + SMSTPCR(reg), bit);
234
+			priv->base + priv->control_regs[reg], bit);
186235 		return -ETIMEDOUT;
187236 	}
188237 
....@@ -205,7 +254,10 @@
205254 	struct cpg_mssr_priv *priv = clock->priv;
206255 	u32 value;
207256 
208
-	value = readl(priv->base + MSTPSR(clock->index / 32));
257
+	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
258
+		value = readb(priv->base + priv->control_regs[clock->index / 32]);
259
+	else
260
+		value = readl(priv->base + priv->status_regs[clock->index / 32]);
209261 
210262 	return !(value & BIT(clock->index % 32));
211263 }
....@@ -226,6 +278,7 @@
226278 	unsigned int idx;
227279 	const char *type;
228280 	struct clk *clk;
281
+	int range_check;
229282 
230283 	switch (clkspec->args[0]) {
231284 	case CPG_CORE:
....@@ -240,8 +293,14 @@
240293 
241294 	case CPG_MOD:
242295 		type = "module";
243
-		idx = MOD_CLK_PACK(clkidx);
244
-		if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
296
+		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
297
+			idx = MOD_CLK_PACK_10(clkidx);
298
+			range_check = 7 - (clkidx % 10);
299
+		} else {
300
+			idx = MOD_CLK_PACK(clkidx);
301
+			range_check = 31 - (clkidx % 100);
302
+		}
303
+		if (range_check < 0 || idx >= priv->num_mod_clks) {
245304 			dev_err(dev, "Invalid %s clock index %u\n", type,
246305 				clkidx);
247306 			return ERR_PTR(-EINVAL);
....@@ -283,7 +342,7 @@
283342 
284343 	switch (core->type) {
285344 	case CLK_TYPE_IN:
286
-		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
345
+		clk = of_clk_get_by_name(priv->np, core->name);
287346 		break;
288347 
289348 	case CLK_TYPE_FF:
....@@ -311,6 +370,11 @@
311370 							parent_name, 0,
312371 							core->mult, div);
313372 		}
373
+		break;
374
+
375
+	case CLK_TYPE_FR:
376
+		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
377
+					      core->mult);
314378 		break;
315379 
316380 	default:
....@@ -343,7 +407,7 @@
343407 	struct mstp_clock *clock = NULL;
344408 	struct device *dev = priv->dev;
345409 	unsigned int id = mod->id;
346
-	struct clk_init_data init = {};
410
+	struct clk_init_data init;
347411 	struct clk *parent, *clk;
348412 	const char *parent_name;
349413 	unsigned int i;
....@@ -372,15 +436,7 @@
372436 
373437 	init.name = mod->name;
374438 	init.ops = &cpg_mstp_clock_ops;
375
-	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
376
-	for (i = 0; i < info->num_crit_mod_clks; i++)
377
-		if (id == info->crit_mod_clks[i]) {
378
-			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
379
-				mod->name);
380
-			init.flags |= CLK_IS_CRITICAL;
381
-			break;
382
-		}
383
-
439
+	init.flags = CLK_SET_RATE_PARENT;
384440 	parent_name = __clk_get_name(parent);
385441 	init.parent_names = &parent_name;
386442 	init.num_parents = 1;
....@@ -388,6 +444,15 @@
388444 	clock->index = id - priv->num_core_clks;
389445 	clock->priv = priv;
390446 	clock->hw.init = &init;
447
+
448
+	for (i = 0; i < info->num_crit_mod_clks; i++)
449
+		if (id == info->crit_mod_clks[i] &&
450
+		    cpg_mstp_clock_is_enabled(&clock->hw)) {
451
+			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
452
+				mod->name);
453
+			init.flags |= CLK_IS_CRITICAL;
454
+			break;
455
+		}
391456 
392457 	clk = clk_register(NULL, &clock->hw);
393458 	if (IS_ERR(clk))
....@@ -406,9 +471,8 @@
406471 
407472 struct cpg_mssr_clk_domain {
408473 	struct generic_pm_domain genpd;
409
-	struct device_node *np;
410474 	unsigned int num_core_pm_clks;
411
-	unsigned int core_pm_clks[0];
475
+	unsigned int core_pm_clks[];
412476 };
413477 
414478 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
....@@ -418,7 +482,7 @@
418482 {
419483 	unsigned int i;
420484 
421
-	if (clkspec->np != pd->np || clkspec->args_count != 2)
485
+	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
422486 		return false;
423487 
424488 	switch (clkspec->args[0]) {
....@@ -469,16 +533,12 @@
469533 		return PTR_ERR(clk);
470534 
471535 	error = pm_clk_create(dev);
472
-	if (error) {
473
-		dev_err(dev, "pm_clk_create failed %d\n", error);
536
+	if (error)
474537 		goto fail_put;
475
-	}
476538 
477539 	error = pm_clk_add_clk(dev, clk);
478
-	if (error) {
479
-		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
540
+	if (error)
480541 		goto fail_destroy;
481
-	}
482542 
483543 	return 0;
484544 
....@@ -508,7 +568,6 @@
508568 	if (!pd)
509569 		return -ENOMEM;
510570 
511
-	pd->np = np;
512571 	pd->num_core_pm_clks = num_core_pm_clks;
513572 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
514573 
....@@ -540,13 +599,13 @@
540599 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
541600 
542601 	/* Reset module */
543
-	writel(bitmask, priv->base + SRCR(reg));
602
+	writel(bitmask, priv->base + priv->reset_regs[reg]);
544603 
545604 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
546605 	udelay(35);
547606 
548607 	/* Release module from reset state */
549
-	writel(bitmask, priv->base + SRSTCLR(reg));
608
+	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
550609 
551610 	return 0;
552611 }
....@@ -560,7 +619,7 @@
560619 
561620 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
562621 
563
-	writel(bitmask, priv->base + SRCR(reg));
622
+	writel(bitmask, priv->base + priv->reset_regs[reg]);
564623 	return 0;
565624 }
566625 
....@@ -574,7 +633,7 @@
574633 
575634 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
576635 
577
-	writel(bitmask, priv->base + SRSTCLR(reg));
636
+	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
578637 	return 0;
579638 }
580639 
....@@ -586,7 +645,7 @@
586645 	unsigned int bit = id % 32;
587646 	u32 bitmask = BIT(bit);
588647 
589
-	return !!(readl(priv->base + SRCR(reg)) & bitmask);
648
+	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
590649 }
591650 
592651 static const struct reset_control_ops cpg_mssr_reset_ops = {
....@@ -630,9 +689,26 @@
630689 
631690 
632691 static const struct of_device_id cpg_mssr_match[] = {
692
+#ifdef CONFIG_CLK_R7S9210
693
+	{
694
+		.compatible = "renesas,r7s9210-cpg-mssr",
695
+		.data = &r7s9210_cpg_mssr_info,
696
+	},
697
+#endif
698
+#ifdef CONFIG_CLK_R8A7742
699
+	{
700
+		.compatible = "renesas,r8a7742-cpg-mssr",
701
+		.data = &r8a7742_cpg_mssr_info,
702
+	},
703
+#endif
633704 #ifdef CONFIG_CLK_R8A7743
634705 	{
635706 		.compatible = "renesas,r8a7743-cpg-mssr",
707
+		.data = &r8a7743_cpg_mssr_info,
708
+	},
709
+	/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
710
+	{
711
+		.compatible = "renesas,r8a7744-cpg-mssr",
636712 		.data = &r8a7743_cpg_mssr_info,
637713 	},
638714 #endif
....@@ -646,6 +722,30 @@
646722 	{
647723 		.compatible = "renesas,r8a77470-cpg-mssr",
648724 		.data = &r8a77470_cpg_mssr_info,
725
+	},
726
+#endif
727
+#ifdef CONFIG_CLK_R8A774A1
728
+	{
729
+		.compatible = "renesas,r8a774a1-cpg-mssr",
730
+		.data = &r8a774a1_cpg_mssr_info,
731
+	},
732
+#endif
733
+#ifdef CONFIG_CLK_R8A774B1
734
+	{
735
+		.compatible = "renesas,r8a774b1-cpg-mssr",
736
+		.data = &r8a774b1_cpg_mssr_info,
737
+	},
738
+#endif
739
+#ifdef CONFIG_CLK_R8A774C0
740
+	{
741
+		.compatible = "renesas,r8a774c0-cpg-mssr",
742
+		.data = &r8a774c0_cpg_mssr_info,
743
+	},
744
+#endif
745
+#ifdef CONFIG_CLK_R8A774E1
746
+	{
747
+		.compatible = "renesas,r8a774e1-cpg-mssr",
748
+		.data = &r8a774e1_cpg_mssr_info,
649749 	},
650750 #endif
651751 #ifdef CONFIG_CLK_R8A7790
....@@ -683,9 +783,15 @@
683783 		.data = &r8a7795_cpg_mssr_info,
684784 	},
685785 #endif
686
-#ifdef CONFIG_CLK_R8A7796
786
+#ifdef CONFIG_CLK_R8A77960
687787 	{
688788 		.compatible = "renesas,r8a7796-cpg-mssr",
789
+		.data = &r8a7796_cpg_mssr_info,
790
+	},
791
+#endif
792
+#ifdef CONFIG_CLK_R8A77961
793
+	{
794
+		.compatible = "renesas,r8a77961-cpg-mssr",
689795 		.data = &r8a7796_cpg_mssr_info,
690796 	},
691797 #endif
....@@ -719,6 +825,12 @@
719825 		.data = &r8a77995_cpg_mssr_info,
720826 	},
721827 #endif
828
+#ifdef CONFIG_CLK_R8A779A0
829
+	{
830
+		.compatible = "renesas,r8a779a0-cpg-mssr",
831
+		.data = &r8a779a0_cpg_mssr_info,
832
+	},
833
+#endif
722834 	{ /* sentinel */ }
723835 };
724836 
....@@ -741,7 +853,9 @@
741853 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
742854 		if (priv->smstpcr_saved[reg].mask)
743855 			priv->smstpcr_saved[reg].val =
744
-				readl(priv->base + SMSTPCR(reg));
856
+				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
857
+				readb(priv->base + priv->control_regs[reg]) :
858
+				readl(priv->base + priv->control_regs[reg]);
745859 	}
746860 
747861 	/* Save core clocks */
....@@ -769,13 +883,23 @@
769883 		if (!mask)
770884 			continue;
771885 
772
-		oldval = readl(priv->base + SMSTPCR(reg));
886
+		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
887
+			oldval = readb(priv->base + priv->control_regs[reg]);
888
+		else
889
+			oldval = readl(priv->base + priv->control_regs[reg]);
773890 		newval = oldval & ~mask;
774891 		newval |= priv->smstpcr_saved[reg].val & mask;
775892 		if (newval == oldval)
776893 			continue;
777894 
778
-		writel(newval, priv->base + SMSTPCR(reg));
895
+		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
896
+			writeb(newval, priv->base + priv->control_regs[reg]);
897
+			/* dummy read to ensure write has completed */
898
+			readb(priv->base + priv->control_regs[reg]);
899
+			barrier_data(priv->base + priv->control_regs[reg]);
900
+			continue;
901
+		} else
902
+			writel(newval, priv->base + priv->control_regs[reg]);
779903 
780904 		/* Wait until enabled clocks are really enabled */
781905 		mask &= ~priv->smstpcr_saved[reg].val;
....@@ -783,15 +907,15 @@
783907 			continue;
784908 
785909 		for (i = 1000; i > 0; --i) {
786
-			oldval = readl(priv->base + MSTPSR(reg));
910
+			oldval = readl(priv->base + priv->status_regs[reg]);
787911 			if (!(oldval & mask))
788912 				break;
789913 			cpu_relax();
790914 		}
791915 
792916 		if (!i)
793
-			dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
794
-				 priv->base + SMSTPCR(reg), oldval & mask);
917
+			dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
918
+				 oldval & mask);
795919 	}
796920 
797921 	return 0;
....@@ -806,60 +930,122 @@
806930 #define DEV_PM_OPS	NULL
807931 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
808932 
809
-static int __init cpg_mssr_probe(struct platform_device *pdev)
933
+static int __init cpg_mssr_common_init(struct device *dev,
934
+				       struct device_node *np,
935
+				       const struct cpg_mssr_info *info)
810936 {
811
-	struct device *dev = &pdev->dev;
812
-	struct device_node *np = dev->of_node;
813
-	const struct cpg_mssr_info *info;
814937 	struct cpg_mssr_priv *priv;
815938 	unsigned int nclks, i;
816
-	struct resource *res;
817
-	struct clk **clks;
818939 	int error;
819940 
820
-	info = of_device_get_match_data(dev);
821941 	if (info->init) {
822942 		error = info->init(dev);
823943 		if (error)
824944 			return error;
825945 	}
826946 
827
-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
947
+	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
948
+	priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
828949 	if (!priv)
829950 		return -ENOMEM;
830951 
952
+	priv->np = np;
831953 	priv->dev = dev;
832954 	spin_lock_init(&priv->rmw_lock);
833955 
834
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
835
-	priv->base = devm_ioremap_resource(dev, res);
836
-	if (IS_ERR(priv->base))
837
-		return PTR_ERR(priv->base);
956
+	priv->base = of_iomap(np, 0);
957
+	if (!priv->base) {
958
+		error = -ENOMEM;
959
+		goto out_err;
960
+	}
838961 
839
-	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
840
-	clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
841
-	if (!clks)
842
-		return -ENOMEM;
843
-
844
-	dev_set_drvdata(dev, priv);
845
-	priv->clks = clks;
846962 	priv->num_core_clks = info->num_total_core_clks;
847963 	priv->num_mod_clks = info->num_hw_mod_clks;
848964 	priv->last_dt_core_clk = info->last_dt_core_clk;
849965 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
966
+	priv->reg_layout = info->reg_layout;
967
+	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
968
+		priv->status_regs = mstpsr;
969
+		priv->control_regs = smstpcr;
970
+		priv->reset_regs = srcr;
971
+		priv->reset_clear_regs = srstclr;
972
+	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
973
+		priv->control_regs = stbcr;
974
+	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
975
+		priv->status_regs = mstpsr_for_v3u;
976
+		priv->control_regs = mstpcr_for_v3u;
977
+		priv->reset_regs = srcr_for_v3u;
978
+		priv->reset_clear_regs = srstclr_for_v3u;
979
+	} else {
980
+		error = -EINVAL;
981
+		goto out_err;
982
+	}
850983 
851984 	for (i = 0; i < nclks; i++)
852
-		clks[i] = ERR_PTR(-ENOENT);
985
+		priv->clks[i] = ERR_PTR(-ENOENT);
986
+
987
+	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
988
+	if (error)
989
+		goto out_err;
990
+
991
+	cpg_mssr_priv = priv;
992
+
993
+	return 0;
994
+
995
+out_err:
996
+	if (priv->base)
997
+		iounmap(priv->base);
998
+	kfree(priv);
999
+
1000
+	return error;
1001
+}
1002
+
1003
+void __init cpg_mssr_early_init(struct device_node *np,
1004
+				const struct cpg_mssr_info *info)
1005
+{
1006
+	int error;
1007
+	int i;
1008
+
1009
+	error = cpg_mssr_common_init(NULL, np, info);
1010
+	if (error)
1011
+		return;
1012
+
1013
+	for (i = 0; i < info->num_early_core_clks; i++)
1014
+		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1015
+					   cpg_mssr_priv);
1016
+
1017
+	for (i = 0; i < info->num_early_mod_clks; i++)
1018
+		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1019
+					  cpg_mssr_priv);
1020
+
1021
+}
1022
+
1023
+static int __init cpg_mssr_probe(struct platform_device *pdev)
1024
+{
1025
+	struct device *dev = &pdev->dev;
1026
+	struct device_node *np = dev->of_node;
1027
+	const struct cpg_mssr_info *info;
1028
+	struct cpg_mssr_priv *priv;
1029
+	unsigned int i;
1030
+	int error;
1031
+
1032
+	info = of_device_get_match_data(dev);
1033
+
1034
+	if (!cpg_mssr_priv) {
1035
+		error = cpg_mssr_common_init(dev, dev->of_node, info);
1036
+		if (error)
1037
+			return error;
1038
+	}
1039
+
1040
+	priv = cpg_mssr_priv;
1041
+	priv->dev = dev;
1042
+	dev_set_drvdata(dev, priv);
8531043 
8541044 	for (i = 0; i < info->num_core_clks; i++)
8551045 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
8561046 
8571047 	for (i = 0; i < info->num_mod_clks; i++)
8581048 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
859
-
860
-	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
861
-	if (error)
862
-		return error;
8631049 
8641050 	error = devm_add_action_or_reset(dev,
8651051 					 cpg_mssr_del_clk_provider,
....@@ -872,6 +1058,10 @@
8721058 	if (error)
8731059 		return error;
8741060 
1061
+	/* Reset Controller not supported for Standby Control SoCs */
1062
+	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1063
+		return 0;
1064
+
8751065 	error = cpg_mssr_reset_controller_register(priv);
8761066 	if (error)
8771067 		return error;