修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/renesas/r8a77995-cpg-mssr.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
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  *
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@@ -7,10 +8,6 @@
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  *
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  * Copyright (C) 2015 Glider bvba
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  * Copyright (C) 2015 Renesas Electronics Corp.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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12
 
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 #include <linux/device.h>
..
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@@ -25,7 +22,7 @@
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 enum clk_ids {
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 	/* Core Clock Outputs exported to DT */
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-	LAST_DT_CORE_CLK = R8A77995_CLK_CP,
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+	LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
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 	/* External Input Clocks */
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 	CLK_EXTAL,
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@@ -45,7 +42,8 @@
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 	CLK_S2,
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 	CLK_S3,
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 	CLK_SDSRC,
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-	CLK_SSPSRC,
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+	CLK_RINT,
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+	CLK_OCO,
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 	/* Module Clocks */
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 	MOD_CLK_BASE
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@@ -72,6 +70,10 @@
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 	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
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 	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
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+	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
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+
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+	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
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+
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 	/* Core Clock Outputs */
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 	DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,     2, 1),
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 	DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
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@@ -90,9 +92,11 @@
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 	DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
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 	DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
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+	DEF_FIXED("cr",        R8A77995_CLK_CR,    CLK_PLL1D2,     2, 1),
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 	DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
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-	DEF_FIXED("osc",       R8A77995_CLK_OSC,   CLK_EXTAL,    384, 1),
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-	DEF_FIXED("r",         R8A77995_CLK_R,     CLK_EXTAL,   1536, 1),
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+	DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),
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+
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+	DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
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 	DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
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 	DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
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@@ -103,6 +107,8 @@
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 	DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
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 	DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
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+
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+	DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
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 };
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 static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
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@@ -118,6 +124,7 @@
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 	DEF_MOD("sys-dmac2",		 217,	R8A77995_CLK_S3D1),
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 	DEF_MOD("sys-dmac1",		 218,	R8A77995_CLK_S3D1),
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 	DEF_MOD("sys-dmac0",		 219,	R8A77995_CLK_S3D1),
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+	DEF_MOD("sceg-pub",		 229,	R8A77995_CLK_CR),
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 	DEF_MOD("cmt3",			 300,	R8A77995_CLK_R),
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 	DEF_MOD("cmt2",			 301,	R8A77995_CLK_R),
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 	DEF_MOD("cmt1",			 302,	R8A77995_CLK_R),
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@@ -129,7 +136,7 @@
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 	DEF_MOD("rwdt",			 402,	R8A77995_CLK_R),
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 	DEF_MOD("intc-ex",		 407,	R8A77995_CLK_CP),
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 	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S1D2),
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-	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S3D1),
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+	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S1D2),
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 	DEF_MOD("hscif3",		 517,	R8A77995_CLK_S3D1C),
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 	DEF_MOD("hscif0",		 520,	R8A77995_CLK_S3D1C),
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 	DEF_MOD("thermal",		 522,	R8A77995_CLK_CP),
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@@ -142,12 +149,11 @@
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 	DEF_MOD("vspbs",		 627,	R8A77995_CLK_S0D1),
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 	DEF_MOD("ehci0",		 703,	R8A77995_CLK_S3D2),
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 	DEF_MOD("hsusb",		 704,	R8A77995_CLK_S3D2),
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+	DEF_MOD("cmm1",			 710,	R8A77995_CLK_S1D1),
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+	DEF_MOD("cmm0",			 711,	R8A77995_CLK_S1D1),
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 	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),
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 	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),
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 	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),
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-	DEF_MOD("vin7",			 804,	R8A77995_CLK_S1D2),
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-	DEF_MOD("vin6",			 805,	R8A77995_CLK_S1D2),
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-	DEF_MOD("vin5",			 806,	R8A77995_CLK_S1D2),
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 	DEF_MOD("vin4",			 807,	R8A77995_CLK_S1D2),
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 	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),
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 	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),
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@@ -178,9 +184,9 @@
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 };
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 static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
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+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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-
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 /*
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  * CPG Clock Data
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@@ -190,14 +196,14 @@
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  * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
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  *--------------------------------------------------------------------
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  * 0		48 x 1		x250/4		x100/3		x100/3
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- * 1		48 x 1		x250/4		x100/3		x116/6
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+ * 1		48 x 1		x250/4		x100/3		x58/3
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  */
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 #define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
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 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
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 	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
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 	{ 1,		100,	3,	100,	3,	},
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-	{ 1,		100,	3,	116,	6,	},
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+	{ 1,		100,	3,	58,	3,	},
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 };
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 static int __init r8a77995_cpg_mssr_init(struct device *dev)