修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/renesas/r8a77980-cpg-mssr.c
..
..
@@ -41,6 +41,8 @@
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 	CLK_S2,
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 	CLK_S3,
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 	CLK_SDSRC,
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+	CLK_RPCSRC,
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+	CLK_OCO,
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 	/* Module Clocks */
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 	MOD_CLK_BASE
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@@ -64,6 +66,13 @@
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 	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,  4, 1),
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 	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,  6, 1),
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 	DEF_FIXED(".sdsrc",	CLK_SDSRC,	   CLK_PLL1_DIV2,  2, 1),
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+	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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+	DEF_RATE(".oco",	CLK_OCO,           32768),
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+
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+	DEF_BASE("rpc",		R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
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+		 CLK_RPCSRC),
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+	DEF_BASE("rpcd2",	R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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+		 R8A77980_CLK_RPC),
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 	/* Core Clock Outputs */
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 	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
..
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@@ -96,6 +105,9 @@
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 	DEF_DIV6P1("canfd",	R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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 	DEF_DIV6P1("csi0",	R8A77980_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
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 	DEF_DIV6P1("mso",	R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
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+
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+	DEF_GEN3_OSC("osc",	R8A77980_CLK_OSC,   CLK_EXTAL,     8),
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+	DEF_GEN3_MDSEL("r",	R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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111
 };
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 static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
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@@ -114,9 +126,14 @@
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 	DEF_MOD("msiof0",		 211,	R8A77980_CLK_MSO),
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 	DEF_MOD("sys-dmac2",		 217,	R8A77980_CLK_S0D3),
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 	DEF_MOD("sys-dmac1",		 218,	R8A77980_CLK_S0D3),
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+	DEF_MOD("cmt3",			 300,	R8A77980_CLK_R),
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+	DEF_MOD("cmt2",			 301,	R8A77980_CLK_R),
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+	DEF_MOD("cmt1",			 302,	R8A77980_CLK_R),
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+	DEF_MOD("cmt0",			 303,	R8A77980_CLK_R),
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 	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),
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 	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),
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 	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S2D2),
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+	DEF_MOD("rwdt",			 402,	R8A77980_CLK_R),
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 	DEF_MOD("intc-ex",		 407,	R8A77980_CLK_CP),
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 	DEF_MOD("intc-ap",		 408,	R8A77980_CLK_S0D3),
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 	DEF_MOD("hscif3",		 517,	R8A77980_CLK_S3D1),
..
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@@ -154,6 +171,7 @@
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 	DEF_MOD("gpio1",		 911,	R8A77980_CLK_CP),
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 	DEF_MOD("gpio0",		 912,	R8A77980_CLK_CP),
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 	DEF_MOD("can-fd",		 914,	R8A77980_CLK_S3D2),
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+	DEF_MOD("rpc-if",		 917,	R8A77980_CLK_RPCD2),
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 	DEF_MOD("i2c4",			 927,	R8A77980_CLK_S0D6),
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 	DEF_MOD("i2c3",			 928,	R8A77980_CLK_S0D6),
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 	DEF_MOD("i2c2",			 929,	R8A77980_CLK_S3D2),
..
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@@ -162,32 +180,32 @@
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 };
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 static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
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+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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-
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 /*
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  * CPG Clock Data
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  */
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 /*
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- *   MD		EXTAL		PLL2	PLL1	PLL3
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+ *   MD		EXTAL		PLL2	PLL1	PLL3	OSC
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  * 14 13	(MHz)
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- * --------------------------------------------------
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- * 0  0		16.66 x 1	x240	x192	x192
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- * 0  1		20    x 1	x200	x160	x160
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- * 1  0		27    x 1	x148	x118	x118
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- * 1  1		33.33 / 2	x240	x192	x192
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+ * --------------------------------------------------------
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+ * 0  0		16.66 x 1	x240	x192	x192	/16
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+ * 0  1		20    x 1	x200	x160	x160	/19
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+ * 1  0		27    x 1	x148	x118	x118	/26
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+ * 1  1		33.33 / 2	x240	x192	x192	/32
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  */
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 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
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 					 (((md) & BIT(13)) >> 13))
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 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
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-	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
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-	{ 1,		192,	1,	192,	1,	},
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-	{ 1,		160,	1,	160,	1,	},
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-	{ 1,		118,	1,	118,	1,	},
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-	{ 2,		192,	1,	192,	1,	},
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+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div	OSC prediv */
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+	{ 1,		192,	1,	192,	1,	16,	},
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+	{ 1,		160,	1,	160,	1,	19,	},
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+	{ 1,		118,	1,	118,	1,	26,	},
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+	{ 2,		192,	1,	192,	1,	32,	},
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 };
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 static int __init r8a77980_cpg_mssr_init(struct device *dev)