| .. | .. |
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| 22 | 22 | #define CX_GMU_CBCR_SLEEP_SHIFT 4 |
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| 23 | 23 | #define CX_GMU_CBCR_WAKE_MASK 0xf |
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| 24 | 24 | #define CX_GMU_CBCR_WAKE_SHIFT 8 |
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| 25 | | -#define CLK_DIS_WAIT_SHIFT 12 |
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| 26 | | -#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) |
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| 27 | 25 | |
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| 28 | 26 | enum { |
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| 29 | 27 | P_BI_TCXO, |
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| .. | .. |
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| 124 | 122 | static struct gdsc gpu_cx_gdsc = { |
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| 125 | 123 | .gdscr = 0x106c, |
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| 126 | 124 | .gds_hw_ctrl = 0x1540, |
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| 125 | + .clk_dis_wait_val = 0x8, |
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| 127 | 126 | .pd = { |
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| 128 | 127 | .name = "gpu_cx_gdsc", |
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| 129 | 128 | }, |
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| .. | .. |
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| 195 | 194 | mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; |
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| 196 | 195 | value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; |
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| 197 | 196 | regmap_update_bits(regmap, 0x1098, mask, value); |
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| 198 | | - |
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| 199 | | - /* Configure clk_dis_wait for gpu_cx_gdsc */ |
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| 200 | | - regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, |
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| 201 | | - 8 << CLK_DIS_WAIT_SHIFT); |
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| 202 | 197 | |
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| 203 | 198 | return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); |
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| 204 | 199 | } |
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