forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/qcom/gcc-sm8250.c
....@@ -200,7 +200,7 @@
200200 	.clkr.hw.init = &(struct clk_init_data){
201201 		.name = "gcc_cpuss_ahb_clk_src",
202202 		.parent_data = gcc_parent_data_0_ao,
203
-		.num_parents = 3,
203
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
204204 		.flags = CLK_SET_RATE_PARENT,
205205 		.ops = &clk_rcg2_ops,
206206 	},
....@@ -224,7 +224,7 @@
224224 	.clkr.hw.init = &(struct clk_init_data){
225225 		.name = "gcc_gp1_clk_src",
226226 		.parent_data = gcc_parent_data_1,
227
-		.num_parents = 4,
227
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
228228 		.ops = &clk_rcg2_ops,
229229 	},
230230 };
....@@ -238,7 +238,7 @@
238238 	.clkr.hw.init = &(struct clk_init_data){
239239 		.name = "gcc_gp2_clk_src",
240240 		.parent_data = gcc_parent_data_1,
241
-		.num_parents = 4,
241
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
242242 		.ops = &clk_rcg2_ops,
243243 	},
244244 };
....@@ -252,7 +252,7 @@
252252 	.clkr.hw.init = &(struct clk_init_data){
253253 		.name = "gcc_gp3_clk_src",
254254 		.parent_data = gcc_parent_data_1,
255
-		.num_parents = 4,
255
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
256256 		.ops = &clk_rcg2_ops,
257257 	},
258258 };
....@@ -272,7 +272,7 @@
272272 	.clkr.hw.init = &(struct clk_init_data){
273273 		.name = "gcc_pcie_0_aux_clk_src",
274274 		.parent_data = gcc_parent_data_2,
275
-		.num_parents = 2,
275
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
276276 		.ops = &clk_rcg2_ops,
277277 	},
278278 };
....@@ -286,7 +286,7 @@
286286 	.clkr.hw.init = &(struct clk_init_data){
287287 		.name = "gcc_pcie_1_aux_clk_src",
288288 		.parent_data = gcc_parent_data_2,
289
-		.num_parents = 2,
289
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
290290 		.ops = &clk_rcg2_ops,
291291 	},
292292 };
....@@ -300,7 +300,7 @@
300300 	.clkr.hw.init = &(struct clk_init_data){
301301 		.name = "gcc_pcie_2_aux_clk_src",
302302 		.parent_data = gcc_parent_data_2,
303
-		.num_parents = 2,
303
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
304304 		.ops = &clk_rcg2_ops,
305305 	},
306306 };
....@@ -320,7 +320,7 @@
320320 	.clkr.hw.init = &(struct clk_init_data){
321321 		.name = "gcc_pcie_phy_refgen_clk_src",
322322 		.parent_data = gcc_parent_data_0_ao,
323
-		.num_parents = 3,
323
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
324324 		.ops = &clk_rcg2_ops,
325325 	},
326326 };
....@@ -341,7 +341,7 @@
341341 	.clkr.hw.init = &(struct clk_init_data){
342342 		.name = "gcc_pdm2_clk_src",
343343 		.parent_data = gcc_parent_data_0,
344
-		.num_parents = 3,
344
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
345345 		.ops = &clk_rcg2_ops,
346346 	},
347347 };
....@@ -369,7 +369,7 @@
369369 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
370370 	.name = "gcc_qupv3_wrap0_s0_clk_src",
371371 	.parent_data = gcc_parent_data_0,
372
-	.num_parents = 3,
372
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
373373 	.ops = &clk_rcg2_ops,
374374 };
375375 
....@@ -385,7 +385,7 @@
385385 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
386386 	.name = "gcc_qupv3_wrap0_s1_clk_src",
387387 	.parent_data = gcc_parent_data_0,
388
-	.num_parents = 3,
388
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
389389 	.ops = &clk_rcg2_ops,
390390 };
391391 
....@@ -417,7 +417,7 @@
417417 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
418418 	.name = "gcc_qupv3_wrap0_s2_clk_src",
419419 	.parent_data = gcc_parent_data_0,
420
-	.num_parents = 3,
420
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
421421 	.ops = &clk_rcg2_ops,
422422 };
423423 
....@@ -433,7 +433,7 @@
433433 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
434434 	.name = "gcc_qupv3_wrap0_s3_clk_src",
435435 	.parent_data = gcc_parent_data_0,
436
-	.num_parents = 3,
436
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
437437 	.ops = &clk_rcg2_ops,
438438 };
439439 
....@@ -449,7 +449,7 @@
449449 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
450450 	.name = "gcc_qupv3_wrap0_s4_clk_src",
451451 	.parent_data = gcc_parent_data_0,
452
-	.num_parents = 3,
452
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
453453 	.ops = &clk_rcg2_ops,
454454 };
455455 
....@@ -465,7 +465,7 @@
465465 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
466466 	.name = "gcc_qupv3_wrap0_s5_clk_src",
467467 	.parent_data = gcc_parent_data_0,
468
-	.num_parents = 3,
468
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
469469 	.ops = &clk_rcg2_ops,
470470 };
471471 
....@@ -481,7 +481,7 @@
481481 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
482482 	.name = "gcc_qupv3_wrap0_s6_clk_src",
483483 	.parent_data = gcc_parent_data_0,
484
-	.num_parents = 3,
484
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
485485 	.ops = &clk_rcg2_ops,
486486 };
487487 
....@@ -497,7 +497,7 @@
497497 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
498498 	.name = "gcc_qupv3_wrap0_s7_clk_src",
499499 	.parent_data = gcc_parent_data_0,
500
-	.num_parents = 3,
500
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
501501 	.ops = &clk_rcg2_ops,
502502 };
503503 
....@@ -513,7 +513,7 @@
513513 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
514514 	.name = "gcc_qupv3_wrap1_s0_clk_src",
515515 	.parent_data = gcc_parent_data_0,
516
-	.num_parents = 3,
516
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
517517 	.ops = &clk_rcg2_ops,
518518 };
519519 
....@@ -529,7 +529,7 @@
529529 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
530530 	.name = "gcc_qupv3_wrap1_s1_clk_src",
531531 	.parent_data = gcc_parent_data_0,
532
-	.num_parents = 3,
532
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
533533 	.ops = &clk_rcg2_ops,
534534 };
535535 
....@@ -545,7 +545,7 @@
545545 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
546546 	.name = "gcc_qupv3_wrap1_s2_clk_src",
547547 	.parent_data = gcc_parent_data_0,
548
-	.num_parents = 3,
548
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
549549 	.ops = &clk_rcg2_ops,
550550 };
551551 
....@@ -561,7 +561,7 @@
561561 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
562562 	.name = "gcc_qupv3_wrap1_s3_clk_src",
563563 	.parent_data = gcc_parent_data_0,
564
-	.num_parents = 3,
564
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
565565 	.ops = &clk_rcg2_ops,
566566 };
567567 
....@@ -577,7 +577,7 @@
577577 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
578578 	.name = "gcc_qupv3_wrap1_s4_clk_src",
579579 	.parent_data = gcc_parent_data_0,
580
-	.num_parents = 3,
580
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
581581 	.ops = &clk_rcg2_ops,
582582 };
583583 
....@@ -593,7 +593,7 @@
593593 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
594594 	.name = "gcc_qupv3_wrap1_s5_clk_src",
595595 	.parent_data = gcc_parent_data_0,
596
-	.num_parents = 3,
596
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
597597 	.ops = &clk_rcg2_ops,
598598 };
599599 
....@@ -609,7 +609,7 @@
609609 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
610610 	.name = "gcc_qupv3_wrap2_s0_clk_src",
611611 	.parent_data = gcc_parent_data_0,
612
-	.num_parents = 3,
612
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613613 	.ops = &clk_rcg2_ops,
614614 };
615615 
....@@ -625,7 +625,7 @@
625625 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
626626 	.name = "gcc_qupv3_wrap2_s1_clk_src",
627627 	.parent_data = gcc_parent_data_0,
628
-	.num_parents = 3,
628
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
629629 	.ops = &clk_rcg2_ops,
630630 };
631631 
....@@ -641,7 +641,7 @@
641641 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
642642 	.name = "gcc_qupv3_wrap2_s2_clk_src",
643643 	.parent_data = gcc_parent_data_0,
644
-	.num_parents = 3,
644
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
645645 	.ops = &clk_rcg2_ops,
646646 };
647647 
....@@ -657,7 +657,7 @@
657657 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
658658 	.name = "gcc_qupv3_wrap2_s3_clk_src",
659659 	.parent_data = gcc_parent_data_0,
660
-	.num_parents = 3,
660
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
661661 	.ops = &clk_rcg2_ops,
662662 };
663663 
....@@ -673,7 +673,7 @@
673673 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
674674 	.name = "gcc_qupv3_wrap2_s4_clk_src",
675675 	.parent_data = gcc_parent_data_0,
676
-	.num_parents = 3,
676
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
677677 	.ops = &clk_rcg2_ops,
678678 };
679679 
....@@ -689,7 +689,7 @@
689689 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
690690 	.name = "gcc_qupv3_wrap2_s5_clk_src",
691691 	.parent_data = gcc_parent_data_0,
692
-	.num_parents = 3,
692
+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
693693 	.ops = &clk_rcg2_ops,
694694 };
695695 
....@@ -721,7 +721,8 @@
721721 	.clkr.hw.init = &(struct clk_init_data){
722722 		.name = "gcc_sdcc2_apps_clk_src",
723723 		.parent_data = gcc_parent_data_4,
724
-		.num_parents = 5,
724
+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
725
+		.flags = CLK_OPS_PARENT_ENABLE,
725726 		.ops = &clk_rcg2_floor_ops,
726727 	},
727728 };
....@@ -744,7 +745,7 @@
744745 	.clkr.hw.init = &(struct clk_init_data){
745746 		.name = "gcc_sdcc4_apps_clk_src",
746747 		.parent_data = gcc_parent_data_0,
747
-		.num_parents = 3,
748
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
748749 		.ops = &clk_rcg2_floor_ops,
749750 	},
750751 };
....@@ -763,7 +764,7 @@
763764 	.clkr.hw.init = &(struct clk_init_data){
764765 		.name = "gcc_tsif_ref_clk_src",
765766 		.parent_data = gcc_parent_data_5,
766
-		.num_parents = 4,
767
+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
767768 		.ops = &clk_rcg2_ops,
768769 	},
769770 };
....@@ -785,7 +786,7 @@
785786 	.clkr.hw.init = &(struct clk_init_data){
786787 		.name = "gcc_ufs_card_axi_clk_src",
787788 		.parent_data = gcc_parent_data_0,
788
-		.num_parents = 3,
789
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
789790 		.ops = &clk_rcg2_ops,
790791 	},
791792 };
....@@ -807,7 +808,7 @@
807808 	.clkr.hw.init = &(struct clk_init_data){
808809 		.name = "gcc_ufs_card_ice_core_clk_src",
809810 		.parent_data = gcc_parent_data_0,
810
-		.num_parents = 3,
811
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
811812 		.ops = &clk_rcg2_ops,
812813 	},
813814 };
....@@ -826,7 +827,7 @@
826827 	.clkr.hw.init = &(struct clk_init_data){
827828 		.name = "gcc_ufs_card_phy_aux_clk_src",
828829 		.parent_data = gcc_parent_data_3,
829
-		.num_parents = 1,
830
+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
830831 		.ops = &clk_rcg2_ops,
831832 	},
832833 };
....@@ -847,7 +848,7 @@
847848 	.clkr.hw.init = &(struct clk_init_data){
848849 		.name = "gcc_ufs_card_unipro_core_clk_src",
849850 		.parent_data = gcc_parent_data_0,
850
-		.num_parents = 3,
851
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
851852 		.ops = &clk_rcg2_ops,
852853 	},
853854 };
....@@ -870,7 +871,7 @@
870871 	.clkr.hw.init = &(struct clk_init_data){
871872 		.name = "gcc_ufs_phy_axi_clk_src",
872873 		.parent_data = gcc_parent_data_0,
873
-		.num_parents = 3,
874
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
874875 		.ops = &clk_rcg2_ops,
875876 	},
876877 };
....@@ -884,7 +885,7 @@
884885 	.clkr.hw.init = &(struct clk_init_data){
885886 		.name = "gcc_ufs_phy_ice_core_clk_src",
886887 		.parent_data = gcc_parent_data_0,
887
-		.num_parents = 3,
888
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888889 		.ops = &clk_rcg2_ops,
889890 	},
890891 };
....@@ -898,7 +899,7 @@
898899 	.clkr.hw.init = &(struct clk_init_data){
899900 		.name = "gcc_ufs_phy_phy_aux_clk_src",
900901 		.parent_data = gcc_parent_data_3,
901
-		.num_parents = 1,
902
+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
902903 		.ops = &clk_rcg2_ops,
903904 	},
904905 };
....@@ -912,7 +913,7 @@
912913 	.clkr.hw.init = &(struct clk_init_data){
913914 		.name = "gcc_ufs_phy_unipro_core_clk_src",
914915 		.parent_data = gcc_parent_data_0,
915
-		.num_parents = 3,
916
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
916917 		.ops = &clk_rcg2_ops,
917918 	},
918919 };
....@@ -935,7 +936,7 @@
935936 	.clkr.hw.init = &(struct clk_init_data){
936937 		.name = "gcc_usb30_prim_master_clk_src",
937938 		.parent_data = gcc_parent_data_0,
938
-		.num_parents = 3,
939
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
939940 		.ops = &clk_rcg2_ops,
940941 	},
941942 };
....@@ -949,7 +950,7 @@
949950 	.clkr.hw.init = &(struct clk_init_data){
950951 		.name = "gcc_usb30_prim_mock_utmi_clk_src",
951952 		.parent_data = gcc_parent_data_0,
952
-		.num_parents = 3,
953
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
953954 		.ops = &clk_rcg2_ops,
954955 	},
955956 };
....@@ -963,7 +964,7 @@
963964 	.clkr.hw.init = &(struct clk_init_data){
964965 		.name = "gcc_usb30_sec_master_clk_src",
965966 		.parent_data = gcc_parent_data_0,
966
-		.num_parents = 3,
967
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
967968 		.ops = &clk_rcg2_ops,
968969 	},
969970 };
....@@ -977,7 +978,7 @@
977978 	.clkr.hw.init = &(struct clk_init_data){
978979 		.name = "gcc_usb30_sec_mock_utmi_clk_src",
979980 		.parent_data = gcc_parent_data_0,
980
-		.num_parents = 3,
981
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
981982 		.ops = &clk_rcg2_ops,
982983 	},
983984 };
....@@ -991,7 +992,7 @@
991992 	.clkr.hw.init = &(struct clk_init_data){
992993 		.name = "gcc_usb3_prim_phy_aux_clk_src",
993994 		.parent_data = gcc_parent_data_2,
994
-		.num_parents = 2,
995
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
995996 		.ops = &clk_rcg2_ops,
996997 	},
997998 };
....@@ -1005,7 +1006,7 @@
10051006 	.clkr.hw.init = &(struct clk_init_data){
10061007 		.name = "gcc_usb3_sec_phy_aux_clk_src",
10071008 		.parent_data = gcc_parent_data_2,
1008
-		.num_parents = 2,
1009
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
10091010 		.ops = &clk_rcg2_ops,
10101011 	},
10111012 };
....@@ -3268,7 +3269,7 @@
32683269 	.pd = {
32693270 		.name = "usb30_prim_gdsc",
32703271 	},
3271
-	.pwrsts = PWRSTS_OFF_ON,
3272
+	.pwrsts = PWRSTS_RET_ON,
32723273 };
32733274 
32743275 static struct gdsc usb30_sec_gdsc = {
....@@ -3276,7 +3277,7 @@
32763277 	.pd = {
32773278 		.name = "usb30_sec_gdsc",
32783279 	},
3279
-	.pwrsts = PWRSTS_OFF_ON,
3280
+	.pwrsts = PWRSTS_RET_ON,
32803281 };
32813282 
32823283 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {