| .. | .. |
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| 18 | 18 | u32 val; |
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| 19 | 19 | |
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| 20 | 20 | if (!br->hwcg_reg) |
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| 21 | | - return 0; |
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| 21 | + return false; |
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| 22 | 22 | |
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| 23 | 23 | regmap_read(br->clkr.regmap, br->hwcg_reg, &val); |
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| 24 | 24 | |
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| .. | .. |
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| 146 | 146 | }; |
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| 147 | 147 | EXPORT_SYMBOL_GPL(clk_branch2_ops); |
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| 148 | 148 | |
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| 149 | +const struct clk_ops clk_branch2_aon_ops = { |
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| 150 | + .enable = clk_branch2_enable, |
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| 151 | + .is_enabled = clk_is_enabled_regmap, |
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| 152 | +}; |
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| 153 | +EXPORT_SYMBOL_GPL(clk_branch2_aon_ops); |
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| 154 | + |
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| 149 | 155 | const struct clk_ops clk_branch_simple_ops = { |
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| 150 | 156 | .enable = clk_enable_regmap, |
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| 151 | 157 | .disable = clk_disable_regmap, |
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