修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/mvebu/cp110-system-controller.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Marvell Armada CP110 System Controller
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  *
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@@ -5,9 +6,6 @@
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  *
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  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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  *
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- * This file is licensed under the terms of the GNU General Public
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- * License version 2.  This program is licensed "as is" without any
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- * warranty of any kind, whether express or implied.
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  */
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 /*
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@@ -23,16 +21,16 @@
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  *    - Equal to SDIO clock
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  *    - 2/5 PLL0
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  *
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- * CP110 has 32 gatable clocks, for the various peripherals in the IP.
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+ * CP110 has 32 gateable clocks, for the various peripherals in the IP.
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  */
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 #define pr_fmt(fmt) "cp110-system-controller: " fmt
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+#include "armada_ap_cp_helper.h"
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 #include <linux/clk-provider.h>
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 #include <linux/mfd/syscon.h>
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 #include <linux/init.h>
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 #include <linux/of.h>
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-#include <linux/of_address.h>
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 #include <linux/platform_device.h>
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 #include <linux/regmap.h>
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 #include <linux/slab.h>
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@@ -59,7 +57,7 @@
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 #define CP110_CORE_NAND			4
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 #define CP110_CORE_SDIO			5
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-/* A number of gatable clocks need special handling */
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+/* A number of gateable clocks need special handling */
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 #define CP110_GATE_AUDIO		0
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 #define CP110_GATE_COMM_UNIT		1
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 #define CP110_GATE_NAND			2
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@@ -160,7 +158,7 @@
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 {
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 	struct cp110_gate_clk *gate;
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 	struct clk_hw *hw;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	int ret;
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 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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@@ -214,22 +212,6 @@
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 	return ERR_PTR(-EINVAL);
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 }
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-static char *cp110_unique_name(struct device *dev, struct device_node *np,
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-			       const char *name)
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-{
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-	const __be32 *reg;
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-	u64 addr;
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-
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-	/* Do not create a name if there is no clock */
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-	if (!name)
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-		return NULL;
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-
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-	reg = of_get_property(np, "reg", NULL);
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-	addr = of_translate_address(np, reg);
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-	return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
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-			      (unsigned long long)addr, name);
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-}
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-
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 static int cp110_syscon_common_probe(struct platform_device *pdev,
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 				     struct device_node *syscon_node)
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 {
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@@ -253,8 +235,8 @@
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 	if (ret)
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 		return ret;
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-	cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
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-				      sizeof(struct clk_hw *) * CP110_CLK_NUM,
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+	cp110_clk_data = devm_kzalloc(dev, struct_size(cp110_clk_data, hws,
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+						       CP110_CLK_NUM),
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 				      GFP_KERNEL);
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 	if (!cp110_clk_data)
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 		return -ENOMEM;
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@@ -263,7 +245,7 @@
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 	cp110_clk_data->num = CP110_CLK_NUM;
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 	/* Register the PLL0 which is the root of the hw tree */
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-	pll0_name = cp110_unique_name(dev, syscon_node, "pll0");
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+	pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
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 	hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
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 					1000 * 1000 * 1000);
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 	if (IS_ERR(hw)) {
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@@ -274,7 +256,7 @@
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 	cp110_clks[CP110_CORE_PLL0] = hw;
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 	/* PPv2 is PLL0/3 */
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-	ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core");
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+	ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
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 	hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
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 	if (IS_ERR(hw)) {
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 		ret = PTR_ERR(hw);
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@@ -284,7 +266,7 @@
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 	cp110_clks[CP110_CORE_PPV2] = hw;
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 	/* X2CORE clock is PLL0/2 */
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-	x2core_name = cp110_unique_name(dev, syscon_node, "x2core");
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+	x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
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 	hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
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 					  0, 1, 2);
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 	if (IS_ERR(hw)) {
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@@ -295,7 +277,7 @@
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 	cp110_clks[CP110_CORE_X2CORE] = hw;
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 	/* Core clock is X2CORE/2 */
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-	core_name = cp110_unique_name(dev, syscon_node, "core");
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+	core_name = ap_cp_unique_name(dev, syscon_node, "core");
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 	hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
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 					  0, 1, 2);
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 	if (IS_ERR(hw)) {
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@@ -305,7 +287,7 @@
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 	cp110_clks[CP110_CORE_CORE] = hw;
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 	/* NAND can be either PLL0/2.5 or core clock */
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-	nand_name = cp110_unique_name(dev, syscon_node, "nand-core");
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+	nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
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 	if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
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 		hw = clk_hw_register_fixed_factor(NULL, nand_name,
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 						   pll0_name, 0, 2, 5);
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@@ -320,7 +302,7 @@
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 	cp110_clks[CP110_CORE_NAND] = hw;
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 	/* SDIO clock is PLL0/2.5 */
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-	sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
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+	sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
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 	hw = clk_hw_register_fixed_factor(NULL, sdio_name,
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 					  pll0_name, 0, 2, 5);
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 	if (IS_ERR(hw)) {
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@@ -332,7 +314,7 @@
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 	/* create the unique name for all the gate clocks */
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 	for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
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-		gate_name[i] =	cp110_unique_name(dev, syscon_node,
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+		gate_name[i] =	ap_cp_unique_name(dev, syscon_node,
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 						  gate_base_names[i]);
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 	for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {