修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/mvebu/ap806-system-controller.c
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..
@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0
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2
 /*
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  * Marvell Armada AP806 System Controller
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  *
..
..
@@ -5,25 +6,22 @@
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  *
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  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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  *
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- * This file is licensed under the terms of the GNU General Public
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- * License version 2.  This program is licensed "as is" without any
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- * warranty of any kind, whether express or implied.
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9
  */
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10
 
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 #define pr_fmt(fmt) "ap806-system-controller: " fmt
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12
 
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+#include "armada_ap_cp_helper.h"
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 #include <linux/clk-provider.h>
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 #include <linux/mfd/syscon.h>
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 #include <linux/init.h>
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 #include <linux/of.h>
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-#include <linux/of_address.h>
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 #include <linux/platform_device.h>
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 #include <linux/regmap.h>
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20
 
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 #define AP806_SAR_REG			0x400
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 #define AP806_SAR_CLKFREQ_MODE_MASK	0x1f
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23
 
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-#define AP806_CLK_NUM			5
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+#define AP806_CLK_NUM			6
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25
 
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 static struct clk *ap806_clks[AP806_CLK_NUM];
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27
 
..
..
@@ -32,22 +30,106 @@
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 	.clk_num = AP806_CLK_NUM,
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 };
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32
 
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-static char *ap806_unique_name(struct device *dev, struct device_node *np,
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-			       char *name)
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+static int ap806_get_sar_clocks(unsigned int freq_mode,
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+				unsigned int *cpuclk_freq,
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+				unsigned int *dclk_freq)
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 {
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-	const __be32 *reg;
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-	u64 addr;
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+	switch (freq_mode) {
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+	case 0x0:
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+		*cpuclk_freq = 2000;
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+		*dclk_freq = 600;
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+		break;
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+	case 0x1:
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+		*cpuclk_freq = 2000;
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+		*dclk_freq = 525;
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+		break;
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+	case 0x6:
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+		*cpuclk_freq = 1800;
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+		*dclk_freq = 600;
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+		break;
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+	case 0x7:
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+		*cpuclk_freq = 1800;
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+		*dclk_freq = 525;
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+		break;
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+	case 0x4:
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+		*cpuclk_freq = 1600;
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+		*dclk_freq = 400;
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+		break;
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+	case 0xB:
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+		*cpuclk_freq = 1600;
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+		*dclk_freq = 450;
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+		break;
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+	case 0xD:
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+		*cpuclk_freq = 1600;
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+		*dclk_freq = 525;
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+		break;
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+	case 0x1a:
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+		*cpuclk_freq = 1400;
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+		*dclk_freq = 400;
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+		break;
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+	case 0x14:
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+		*cpuclk_freq = 1300;
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+		*dclk_freq = 400;
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+		break;
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+	case 0x17:
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+		*cpuclk_freq = 1300;
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+		*dclk_freq = 325;
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+		break;
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+	case 0x19:
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+		*cpuclk_freq = 1200;
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+		*dclk_freq = 400;
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+		break;
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+	case 0x13:
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+		*cpuclk_freq = 1000;
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+		*dclk_freq = 325;
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+		break;
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+	case 0x1d:
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+		*cpuclk_freq = 1000;
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+		*dclk_freq = 400;
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+		break;
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+	case 0x1c:
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+		*cpuclk_freq = 800;
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+		*dclk_freq = 400;
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+		break;
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+	case 0x1b:
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+		*cpuclk_freq = 600;
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+		*dclk_freq = 400;
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+		break;
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+	default:
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+		return -EINVAL;
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+	}
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-	reg = of_get_property(np, "reg", NULL);
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-	addr = of_translate_address(np, reg);
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-	return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
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-			(unsigned long long)addr, name);
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+	return 0;
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+}
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+
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+static int ap807_get_sar_clocks(unsigned int freq_mode,
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+				unsigned int *cpuclk_freq,
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+				unsigned int *dclk_freq)
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+{
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+	switch (freq_mode) {
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+	case 0x0:
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+		*cpuclk_freq = 2000;
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+		*dclk_freq = 1200;
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+		break;
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+	case 0x6:
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+		*cpuclk_freq = 2200;
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+		*dclk_freq = 1200;
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+		break;
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+	case 0xD:
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+		*cpuclk_freq = 1600;
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+		*dclk_freq = 1200;
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+		break;
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+	default:
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+		return -EINVAL;
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+	}
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+
126
+	return 0;
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127
 }
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128
 
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129
 static int ap806_syscon_common_probe(struct platform_device *pdev,
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130
 				     struct device_node *syscon_node)
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131
 {
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-	unsigned int freq_mode, cpuclk_freq;
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+	unsigned int freq_mode, cpuclk_freq, dclk_freq;
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133
 	const char *name, *fixedclk_name;
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134
 	struct device *dev = &pdev->dev;
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135
 	struct device_node *np = dev->of_node;
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@@ -68,50 +150,29 @@
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150
 	}
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151
 
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 	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
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-	switch (freq_mode) {
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-	case 0x0:
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-	case 0x1:
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-		cpuclk_freq = 2000;
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-		break;
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-	case 0x6:
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-	case 0x7:
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-		cpuclk_freq = 1800;
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-		break;
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-	case 0x4:
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-	case 0xB:
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-	case 0xD:
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-		cpuclk_freq = 1600;
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-		break;
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-	case 0x1a:
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-		cpuclk_freq = 1400;
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-		break;
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-	case 0x14:
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-	case 0x17:
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-		cpuclk_freq = 1300;
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-		break;
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-	case 0x19:
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-		cpuclk_freq = 1200;
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-		break;
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-	case 0x13:
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-	case 0x1d:
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-		cpuclk_freq = 1000;
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-		break;
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-	case 0x1c:
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-		cpuclk_freq = 800;
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-		break;
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-	case 0x1b:
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-		cpuclk_freq = 600;
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-		break;
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-	default:
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-		dev_err(dev, "invalid SAR value\n");
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+
154
+	if (of_device_is_compatible(pdev->dev.of_node,
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+				    "marvell,ap806-clock")) {
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+		ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
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+	} else if (of_device_is_compatible(pdev->dev.of_node,
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+					   "marvell,ap807-clock")) {
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+		ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
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+	} else {
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+		dev_err(dev, "compatible not supported\n");
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 		return -EINVAL;
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+	}
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+
165
+	if (ret) {
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+		dev_err(dev, "invalid Sample at Reset value\n");
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+		return ret;
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168
 	}
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169
 
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 	/* Convert to hertz */
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 	cpuclk_freq *= 1000 * 1000;
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+	dclk_freq *= 1000 * 1000;
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173
 
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 	/* CPU clocks depend on the Sample At Reset configuration */
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-	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
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+	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
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 	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
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177
 						0, cpuclk_freq);
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178
 	if (IS_ERR(ap806_clks[0])) {
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@@ -119,7 +180,7 @@
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180
 		goto fail0;
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 	}
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182
 
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-	name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
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+	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
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 	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
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 						cpuclk_freq);
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 	if (IS_ERR(ap806_clks[1])) {
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@@ -128,7 +189,7 @@
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 	}
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190
 
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 	/* Fixed clock is always 1200 Mhz */
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-	fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed");
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+	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
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 	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
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 						0, 1200 * 1000 * 1000);
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 	if (IS_ERR(ap806_clks[2])) {
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@@ -137,7 +198,7 @@
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 	}
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199
 
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 	/* MSS Clock is fixed clock divided by 6 */
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-	name = ap806_unique_name(dev, syscon_node, "mss");
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+	name = ap_cp_unique_name(dev, syscon_node, "mss");
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 	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
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 						  0, 1, 6);
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 	if (IS_ERR(ap806_clks[3])) {
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@@ -146,7 +207,7 @@
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 	}
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208
 
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 	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
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-	name = ap806_unique_name(dev, syscon_node, "sdio");
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+	name = ap_cp_unique_name(dev, syscon_node, "sdio");
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 	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
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 						  fixedclk_name,
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213
 						  0, 1, 3);
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@@ -155,7 +216,14 @@
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 		goto fail4;
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 	}
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218
 
158
-	of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
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+	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
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+	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
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+	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
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+	if (IS_ERR(ap806_clks[5])) {
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+		ret = PTR_ERR(ap806_clks[5]);
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+		goto fail5;
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+	}
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+
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 	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
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 	if (ret)
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 		goto fail_clk_add;
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@@ -163,6 +231,8 @@
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 	return 0;
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232
 
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233
 fail_clk_add:
234
+	clk_unregister_fixed_factor(ap806_clks[5]);
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+fail5:
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 	clk_unregister_fixed_factor(ap806_clks[4]);
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 fail4:
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 	clk_unregister_fixed_factor(ap806_clks[3]);
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@@ -209,6 +279,7 @@
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279
 
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 static const struct of_device_id ap806_clock_of_match[] = {
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 	{ .compatible = "marvell,ap806-clock", },
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+	{ .compatible = "marvell,ap807-clock", },
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 	{ }
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 };
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285