修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/clk/mediatek/clk-pll.c
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@@ -1,15 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2014 MediaTek Inc.
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  * Author: James Liao <jamesjj.liao@mediatek.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/of.h>
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@@ -27,11 +19,13 @@
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 #define CON0_BASE_EN		BIT(0)
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 #define CON0_PWR_ON		BIT(0)
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 #define CON0_ISO_EN		BIT(1)
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-#define CON0_PCW_CHG		BIT(31)
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+#define PCW_CHG_MASK		BIT(31)
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 #define AUDPLL_TUNER_EN		BIT(31)
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 #define POSTDIV_MASK		0x7
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+
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+/* default 7 bits integer, can be overridden with pcwibits. */
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 #define INTEGER_BITS		7
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 /*
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@@ -49,6 +43,7 @@
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 	void __iomem	*tuner_addr;
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 	void __iomem	*tuner_en_addr;
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 	void __iomem	*pcw_addr;
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+	void __iomem	*pcw_chg_addr;
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 	const struct mtk_pll_data *data;
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 };
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@@ -68,12 +63,15 @@
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 		u32 pcw, int postdiv)
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 {
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 	int pcwbits = pll->data->pcwbits;
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-	int pcwfbits;
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+	int pcwfbits = 0;
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+	int ibits;
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 	u64 vco;
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 	u8 c = 0;
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 	/* The fractional part of the PLL divider. */
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-	pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
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+	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
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+	if (pcwbits > ibits)
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+		pcwfbits = pcwbits - ibits;
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 	vco = (u64)fin * pcw;
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@@ -117,10 +115,7 @@
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 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
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 		int postdiv)
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 {
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-	u32 con1, val;
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-	int pll_en;
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-
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-	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
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+	u32 chg, val;
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 	/* disable tuner */
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 	__mtk_pll_tuner_disable(pll);
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@@ -141,21 +136,15 @@
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 			pll->data->pcw_shift);
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 	val |= pcw << pll->data->pcw_shift;
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 	writel(val, pll->pcw_addr);
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-
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-	con1 = readl(pll->base_addr + REG_CON1);
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-
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-	if (pll_en)
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-		con1 |= CON0_PCW_CHG;
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-
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-	writel(con1, pll->base_addr + REG_CON1);
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+	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
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+	writel(chg, pll->pcw_chg_addr);
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 	if (pll->tuner_addr)
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-		writel(con1 + 1, pll->tuner_addr);
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+		writel(val + 1, pll->tuner_addr);
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 	/* restore tuner_en */
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 	__mtk_pll_tuner_enable(pll);
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-	if (pll_en)
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-		udelay(20);
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+	udelay(20);
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 }
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 /*
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@@ -170,9 +159,10 @@
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 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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 		u32 freq, u32 fin)
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 {
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-	unsigned long fmin = 1000 * MHZ;
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+	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
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 	const struct mtk_pll_div_table *div_table = pll->data->div_table;
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 	u64 _pcw;
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+	int ibits;
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 	u32 val;
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 	if (freq > pll->data->fmax)
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@@ -196,7 +186,8 @@
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 	}
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 	/* _pcw = freq * postdiv / fin * 2^pcwfbits */
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-	_pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
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+	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
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+	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
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 	do_div(_pcw, fin);
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 	*pcw = (u32)_pcw;
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@@ -322,6 +313,10 @@
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 	pll->pwr_addr = base + data->pwr_reg;
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 	pll->pd_addr = base + data->pd_reg;
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 	pll->pcw_addr = base + data->pcw_reg;
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+	if (data->pcw_chg_reg)
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+		pll->pcw_chg_addr = base + data->pcw_chg_reg;
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+	else
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+		pll->pcw_chg_addr = pll->base_addr + REG_CON1;
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 	if (data->tuner_reg)
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 		pll->tuner_addr = base + data->tuner_reg;
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 	if (data->tuner_en_reg)