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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/clk/at91/clk-generated.c
....@@ -1,16 +1,12 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  *  Copyright (C) 2015 Atmel Corporation,
34  *                     Nicolas Ferre <nicolas.ferre@atmel.com>
45  *
56  * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License as published by
9
- * the Free Software Foundation; either version 2 of the License, or
10
- * (at your option) any later version.
11
- *
127  */
138 
9
+#include <linux/bitfield.h>
1410 #include <linux/clk-provider.h>
1511 #include <linux/clkdev.h>
1612 #include <linux/clk/at91_pmc.h>
....@@ -20,28 +16,19 @@
2016 
2117 #include "pmc.h"
2218 
23
-#define PERIPHERAL_MAX		64
24
-#define PERIPHERAL_ID_MIN	2
25
-
26
-#define GENERATED_SOURCE_MAX	6
2719 #define GENERATED_MAX_DIV	255
28
-
29
-#define GCK_ID_SSC0		43
30
-#define GCK_ID_SSC1		44
31
-#define GCK_ID_I2S0		54
32
-#define GCK_ID_I2S1		55
33
-#define GCK_ID_CLASSD		59
34
-#define GCK_INDEX_DT_AUDIO_PLL	5
3520 
3621 struct clk_generated {
3722 	struct clk_hw hw;
3823 	struct regmap *regmap;
3924 	struct clk_range range;
4025 	spinlock_t *lock;
26
+	u32 *mux_table;
4127 	u32 id;
4228 	u32 gckdiv;
29
+	const struct clk_pcr_layout *layout;
4330 	u8 parent_id;
44
-	bool audio_pll_allowed;
31
+	int chg_pid;
4532 };
4633 
4734 #define to_clk_generated(hw) \
....@@ -56,14 +43,14 @@
5643 		 __func__, gck->gckdiv, gck->parent_id);
5744 
5845 	spin_lock_irqsave(gck->lock, flags);
59
-	regmap_write(gck->regmap, AT91_PMC_PCR,
60
-		     (gck->id & AT91_PMC_PCR_PID_MASK));
61
-	regmap_update_bits(gck->regmap, AT91_PMC_PCR,
62
-			   AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK |
63
-			   AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
64
-			   AT91_PMC_PCR_GCKCSS(gck->parent_id) |
65
-			   AT91_PMC_PCR_CMD |
66
-			   AT91_PMC_PCR_GCKDIV(gck->gckdiv) |
46
+	regmap_write(gck->regmap, gck->layout->offset,
47
+		     (gck->id & gck->layout->pid_mask));
48
+	regmap_update_bits(gck->regmap, gck->layout->offset,
49
+			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
50
+			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
51
+			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
52
+			   gck->layout->cmd |
53
+			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
6754 			   AT91_PMC_PCR_GCKEN);
6855 	spin_unlock_irqrestore(gck->lock, flags);
6956 	return 0;
....@@ -75,11 +62,11 @@
7562 	unsigned long flags;
7663 
7764 	spin_lock_irqsave(gck->lock, flags);
78
-	regmap_write(gck->regmap, AT91_PMC_PCR,
79
-		     (gck->id & AT91_PMC_PCR_PID_MASK));
80
-	regmap_update_bits(gck->regmap, AT91_PMC_PCR,
81
-			   AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
82
-			   AT91_PMC_PCR_CMD);
65
+	regmap_write(gck->regmap, gck->layout->offset,
66
+		     (gck->id & gck->layout->pid_mask));
67
+	regmap_update_bits(gck->regmap, gck->layout->offset,
68
+			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
69
+			   gck->layout->cmd);
8370 	spin_unlock_irqrestore(gck->lock, flags);
8471 }
8572 
....@@ -90,12 +77,12 @@
9077 	unsigned int status;
9178 
9279 	spin_lock_irqsave(gck->lock, flags);
93
-	regmap_write(gck->regmap, AT91_PMC_PCR,
94
-		     (gck->id & AT91_PMC_PCR_PID_MASK));
95
-	regmap_read(gck->regmap, AT91_PMC_PCR, &status);
80
+	regmap_write(gck->regmap, gck->layout->offset,
81
+		     (gck->id & gck->layout->pid_mask));
82
+	regmap_read(gck->regmap, gck->layout->offset, &status);
9683 	spin_unlock_irqrestore(gck->lock, flags);
9784 
98
-	return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
85
+	return !!(status & AT91_PMC_PCR_GCKEN);
9986 }
10087 
10188 static unsigned long
....@@ -119,9 +106,13 @@
119106 		tmp_rate = parent_rate;
120107 	else
121108 		tmp_rate = parent_rate / div;
109
+
110
+	if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
111
+		return;
112
+
122113 	tmp_diff = abs(req->rate - tmp_rate);
123114 
124
-	if (*best_diff < 0 || *best_diff > tmp_diff) {
115
+	if (*best_diff < 0 || *best_diff >= tmp_diff) {
125116 		*best_rate = tmp_rate;
126117 		*best_diff = tmp_diff;
127118 		req->best_parent_rate = parent_rate;
....@@ -141,7 +132,16 @@
141132 	int i;
142133 	u32 div;
143134 
144
-	for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
135
+	/* do not look for a rate that is outside of our range */
136
+	if (gck->range.max && req->rate > gck->range.max)
137
+		req->rate = gck->range.max;
138
+	if (gck->range.min && req->rate < gck->range.min)
139
+		req->rate = gck->range.min;
140
+
141
+	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
142
+		if (gck->chg_pid == i)
143
+			continue;
144
+
145145 		parent = clk_hw_get_parent_by_index(hw, i);
146146 		if (!parent)
147147 			continue;
....@@ -173,16 +173,17 @@
173173 	 * that the only clks able to modify gck rate are those of audio IPs.
174174 	 */
175175 
176
-	if (!gck->audio_pll_allowed)
176
+	if (gck->chg_pid < 0)
177177 		goto end;
178178 
179
-	parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
179
+	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
180180 	if (!parent)
181181 		goto end;
182182 
183183 	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
184184 		req_parent.rate = req->rate * div;
185
-		__clk_determine_rate(parent, &req_parent);
185
+		if (__clk_determine_rate(parent, &req_parent))
186
+			continue;
186187 		clk_generated_best_diff(req, parent, req_parent.rate, div,
187188 					&best_diff, &best_rate);
188189 
....@@ -196,8 +197,8 @@
196197 		 __clk_get_name((req->best_parent_hw)->clk),
197198 		 req->best_parent_rate);
198199 
199
-	if (best_rate < 0)
200
-		return best_rate;
200
+	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
201
+		return -EINVAL;
201202 
202203 	req->rate = best_rate;
203204 	return 0;
....@@ -211,7 +212,11 @@
211212 	if (index >= clk_hw_get_num_parents(hw))
212213 		return -EINVAL;
213214 
214
-	gck->parent_id = index;
215
+	if (gck->mux_table)
216
+		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
217
+	else
218
+		gck->parent_id = index;
219
+
215220 	return 0;
216221 }
217222 
....@@ -270,25 +275,25 @@
270275 	unsigned long flags;
271276 
272277 	spin_lock_irqsave(gck->lock, flags);
273
-	regmap_write(gck->regmap, AT91_PMC_PCR,
274
-		     (gck->id & AT91_PMC_PCR_PID_MASK));
275
-	regmap_read(gck->regmap, AT91_PMC_PCR, &tmp);
278
+	regmap_write(gck->regmap, gck->layout->offset,
279
+		     (gck->id & gck->layout->pid_mask));
280
+	regmap_read(gck->regmap, gck->layout->offset, &tmp);
276281 	spin_unlock_irqrestore(gck->lock, flags);
277282 
278
-	gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK)
279
-					>> AT91_PMC_PCR_GCKCSS_OFFSET;
280
-	gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK)
281
-					>> AT91_PMC_PCR_GCKDIV_OFFSET;
283
+	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
284
+	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
282285 }
283286 
284
-static struct clk_hw * __init
287
+struct clk_hw * __init
285288 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
289
+			    const struct clk_pcr_layout *layout,
286290 			    const char *name, const char **parent_names,
287
-			    u8 num_parents, u8 id, bool pll_audio,
288
-			    const struct clk_range *range)
291
+			    u32 *mux_table, u8 num_parents, u8 id,
292
+			    const struct clk_range *range,
293
+			    int chg_pid)
289294 {
290295 	struct clk_generated *gck;
291
-	struct clk_init_data init = {};
296
+	struct clk_init_data init;
292297 	struct clk_hw *hw;
293298 	int ret;
294299 
....@@ -300,15 +305,18 @@
300305 	init.ops = &generated_ops;
301306 	init.parent_names = parent_names;
302307 	init.num_parents = num_parents;
303
-	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
304
-		CLK_SET_RATE_PARENT;
308
+	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
309
+	if (chg_pid >= 0)
310
+		init.flags |= CLK_SET_RATE_PARENT;
305311 
306312 	gck->id = id;
307313 	gck->hw.init = &init;
308314 	gck->regmap = regmap;
309315 	gck->lock = lock;
310316 	gck->range = *range;
311
-	gck->audio_pll_allowed = pll_audio;
317
+	gck->chg_pid = chg_pid;
318
+	gck->layout = layout;
319
+	gck->mux_table = mux_table;
312320 
313321 	clk_generated_startup(gck);
314322 	hw = &gck->hw;
....@@ -322,61 +330,3 @@
322330 
323331 	return hw;
324332 }
325
-
326
-static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
327
-{
328
-	int num;
329
-	u32 id;
330
-	const char *name;
331
-	struct clk_hw *hw;
332
-	unsigned int num_parents;
333
-	const char *parent_names[GENERATED_SOURCE_MAX];
334
-	struct device_node *gcknp;
335
-	struct clk_range range = CLK_RANGE(0, 0);
336
-	struct regmap *regmap;
337
-
338
-	num_parents = of_clk_get_parent_count(np);
339
-	if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
340
-		return;
341
-
342
-	of_clk_parent_fill(np, parent_names, num_parents);
343
-
344
-	num = of_get_child_count(np);
345
-	if (!num || num > PERIPHERAL_MAX)
346
-		return;
347
-
348
-	regmap = syscon_node_to_regmap(of_get_parent(np));
349
-	if (IS_ERR(regmap))
350
-		return;
351
-
352
-	for_each_child_of_node(np, gcknp) {
353
-		bool pll_audio = false;
354
-
355
-		if (of_property_read_u32(gcknp, "reg", &id))
356
-			continue;
357
-
358
-		if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
359
-			continue;
360
-
361
-		if (of_property_read_string(np, "clock-output-names", &name))
362
-			name = gcknp->name;
363
-
364
-		of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
365
-				      &range);
366
-
367
-		if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
368
-		    (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
369
-		     id == GCK_ID_CLASSD))
370
-			pll_audio = true;
371
-
372
-		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
373
-						  parent_names, num_parents,
374
-						  id, pll_audio, &range);
375
-		if (IS_ERR(hw))
376
-			continue;
377
-
378
-		of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
379
-	}
380
-}
381
-CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
382
-	       of_sama5d2_clk_generated_setup);