.. | .. |
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27 | 27 | PERF_REG_X86_R13, |
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28 | 28 | PERF_REG_X86_R14, |
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29 | 29 | PERF_REG_X86_R15, |
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30 | | - |
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| 30 | + /* These are the limits for the GPRs. */ |
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31 | 31 | PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, |
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32 | 32 | PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, |
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| 33 | + |
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| 34 | + /* These all need two bits set because they are 128bit */ |
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| 35 | + PERF_REG_X86_XMM0 = 32, |
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| 36 | + PERF_REG_X86_XMM1 = 34, |
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| 37 | + PERF_REG_X86_XMM2 = 36, |
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| 38 | + PERF_REG_X86_XMM3 = 38, |
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| 39 | + PERF_REG_X86_XMM4 = 40, |
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| 40 | + PERF_REG_X86_XMM5 = 42, |
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| 41 | + PERF_REG_X86_XMM6 = 44, |
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| 42 | + PERF_REG_X86_XMM7 = 46, |
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| 43 | + PERF_REG_X86_XMM8 = 48, |
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| 44 | + PERF_REG_X86_XMM9 = 50, |
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| 45 | + PERF_REG_X86_XMM10 = 52, |
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| 46 | + PERF_REG_X86_XMM11 = 54, |
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| 47 | + PERF_REG_X86_XMM12 = 56, |
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| 48 | + PERF_REG_X86_XMM13 = 58, |
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| 49 | + PERF_REG_X86_XMM14 = 60, |
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| 50 | + PERF_REG_X86_XMM15 = 62, |
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| 51 | + |
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| 52 | + /* These include both GPRs and XMMX registers */ |
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| 53 | + PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2, |
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33 | 54 | }; |
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| 55 | + |
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| 56 | +#define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) |
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| 57 | + |
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34 | 58 | #endif /* _ASM_X86_PERF_REGS_H */ |
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