forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/arch/x86/include/asm/uv/uv_mmrs.h
....@@ -3,8 +3,9 @@
33  * License.  See the file "COPYING" in the main directory of this archive
44  * for more details.
55  *
6
- * SGI UV MMR definitions
6
+ * HPE UV MMR definitions
77  *
8
+ * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
89  * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
910  */
1011 
....@@ -18,58 +19,43 @@
1819  * grouped by architecture types.
1920  *
2021  * UVH  - definitions common to all UV hub types.
21
- * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4).
22
- * UV1H - definitions specific to UV type 1 hub.
23
- * UV2H - definitions specific to UV type 2 hub.
24
- * UV3H - definitions specific to UV type 3 hub.
22
+ * UVXH - definitions common to UVX class (2, 3, 4).
23
+ * UVYH - definitions common to UVY class (5).
24
+ * UV5H - definitions specific to UV type 5 hub.
25
+ * UV4AH - definitions specific to UV type 4A hub.
2526  * UV4H - definitions specific to UV type 4 hub.
26
- *
27
- * So in general, MMR addresses and structures are identical on all hubs types.
28
- * These MMRs are identified as:
29
- *	#define UVH_xxx		<address>
30
- *	union uvh_xxx {
31
- *		unsigned long       v;
32
- *		struct uvh_int_cmpd_s {
33
- *		} s;
34
- *	};
27
+ * UV3H - definitions specific to UV type 3 hub.
28
+ * UV2H - definitions specific to UV type 2 hub.
3529  *
3630  * If the MMR exists on all hub types but have different addresses,
37
- * use a conditional operator to define the value at runtime.
38
- *	#define UV1Hxxx	a
39
- *	#define UV2Hxxx	b
40
- *	#define UV3Hxxx	c
41
- *	#define UV4Hxxx	d
42
- *	#define UV4AHxxx e
43
- *	#define UVHxxx	(is_uv1_hub() ? UV1Hxxx :
44
- *			(is_uv2_hub() ? UV2Hxxx :
45
- *			(is_uv3_hub() ? UV3Hxxx :
46
- *			(is_uv4a_hub() ? UV4AHxxx :
47
- *					UV4Hxxx))
31
+ * use a conditional operator to define the value at runtime.  Any
32
+ * that are not defined are blank.
33
+ *	(UV4A variations only generated if different from uv4)
34
+ *	#define UVHxxx (
35
+ *		is_uv(UV5) ? UV5Hxxx value :
36
+ *		is_uv(UV4A) ? UV4AHxxx value :
37
+ *		is_uv(UV4) ? UV4Hxxx value :
38
+ *		is_uv(UV3) ? UV3Hxxx value :
39
+ *		is_uv(UV2) ? UV2Hxxx value :
40
+ *		<ucv> or <undef value>)
4841  *
49
- * If the MMR exists on all hub types > 1 but have different addresses, the
50
- * variation using "UVX" as the prefix exists.
51
- *	#define UV2Hxxx	b
52
- *	#define UV3Hxxx	c
53
- *	#define UV4Hxxx	d
54
- *	#define UV4AHxxx e
55
- *	#define UVHxxx	(is_uv2_hub() ? UV2Hxxx :
56
- *			(is_uv3_hub() ? UV3Hxxx :
57
- *			(is_uv4a_hub() ? UV4AHxxx :
58
- *					UV4Hxxx))
42
+ * Class UVX has UVs (2|3|4|4A).
43
+ * Class UVY has UVs (5).
5944  *
6045  *	union uvh_xxx {
6146  *		unsigned long       v;
6247  *		struct uvh_xxx_s {	 # Common fields only
6348  *		} s;
64
- *		struct uv1h_xxx_s {	 # Full UV1 definition (*)
65
- *		} s1;
66
- *		struct uv2h_xxx_s {	 # Full UV2 definition (*)
67
- *		} s2;
68
- *		struct uv3h_xxx_s {	 # Full UV3 definition (*)
69
- *		} s3;
70
- *		(NOTE: No struct uv4ah_xxx_s members exist)
49
+ *		struct uv5h_xxx_s {	 # Full UV5 definition (*)
50
+ *		} s5;
51
+ *		struct uv4ah_xxx_s {	 # Full UV4A definition (*)
52
+ *		} s4a;
7153  *		struct uv4h_xxx_s {	 # Full UV4 definition (*)
7254  *		} s4;
55
+ *		struct uv3h_xxx_s {	 # Full UV3 definition (*)
56
+ *		} s3;
57
+ *		struct uv2h_xxx_s {	 # Full UV2 definition (*)
58
+ *		} s2;
7359  *	};
7460  *		(* - if present and different than the common struct)
7561  *
....@@ -78,17 +64,21 @@
7864  * if the contents is the same for all hubs, only the "s" structure is
7965  * generated.
8066  *
81
- * If the MMR exists on ONLY 1 type of hub, no generic definition is
82
- * generated:
83
- *	#define UVnH_xxx	<uvn address>
84
- *	union uvnh_xxx {
85
- *		unsigned long       v;
86
- *		struct uvh_int_cmpd_s {
87
- *		} sn;
88
- *	};
89
- *
90
- * (GEN Flags: mflags_opt= undefs=function UV234=UVXH)
67
+ * (GEN Flags: undefs=function)
9168  */
69
+
70
+ /* UV bit masks */
71
+#define	UV2	(1 << 0)
72
+#define	UV3	(1 << 1)
73
+#define	UV4	(1 << 2)
74
+#define	UV4A	(1 << 3)
75
+#define	UV5	(1 << 4)
76
+#define	UVX	(UV2|UV3|UV4)
77
+#define	UVY	(UV5)
78
+#define	UV_ANY	(~0)
79
+
80
+
81
+
9282 
9383 #define UV_MMR_ENABLE		(1UL << 63)
9484 
....@@ -98,533 +88,475 @@
9888 #define UV3_HUB_PART_NUMBER	0x9578
9989 #define UV3_HUB_PART_NUMBER_X	0x4321
10090 #define UV4_HUB_PART_NUMBER	0x99a1
101
-
102
-/* Compat: Indicate which UV Hubs are supported. */
103
-#define UV1_HUB_IS_SUPPORTED	1
104
-#define UV2_HUB_IS_SUPPORTED	1
105
-#define UV3_HUB_IS_SUPPORTED	1
106
-#define UV4_HUB_IS_SUPPORTED	1
107
-#define UV4A_HUB_IS_SUPPORTED	1
91
+#define UV5_HUB_PART_NUMBER	0xa171
10892 
10993 /* Error function to catch undefined references */
11094 extern unsigned long uv_undefined(char *str);
11195 
11296 /* ========================================================================= */
113
-/*                          UVH_BAU_DATA_BROADCAST                           */
114
-/* ========================================================================= */
115
-#define UVH_BAU_DATA_BROADCAST 0x61688UL
116
-
117
-#define UV1H_BAU_DATA_BROADCAST_32 0x440
118
-#define UV2H_BAU_DATA_BROADCAST_32 0x440
119
-#define UV3H_BAU_DATA_BROADCAST_32 0x440
120
-#define UV4H_BAU_DATA_BROADCAST_32 0x360
121
-#define UVH_BAU_DATA_BROADCAST_32 (					\
122
-	is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 :			\
123
-	is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 :			\
124
-	is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 :			\
125
-	/*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32)
126
-
127
-#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT		0
128
-#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK		0x0000000000000001UL
129
-
130
-
131
-union uvh_bau_data_broadcast_u {
132
-	unsigned long	v;
133
-	struct uvh_bau_data_broadcast_s {
134
-		unsigned long	enable:1;			/* RW */
135
-		unsigned long	rsvd_1_63:63;
136
-	} s;
137
-};
138
-
139
-/* ========================================================================= */
140
-/*                           UVH_BAU_DATA_CONFIG                             */
141
-/* ========================================================================= */
142
-#define UVH_BAU_DATA_CONFIG 0x61680UL
143
-
144
-#define UV1H_BAU_DATA_CONFIG_32 0x438
145
-#define UV2H_BAU_DATA_CONFIG_32 0x438
146
-#define UV3H_BAU_DATA_CONFIG_32 0x438
147
-#define UV4H_BAU_DATA_CONFIG_32 0x358
148
-#define UVH_BAU_DATA_CONFIG_32 (					\
149
-	is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 :			\
150
-	is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 :			\
151
-	is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 :			\
152
-	/*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32)
153
-
154
-#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT			0
155
-#define UVH_BAU_DATA_CONFIG_DM_SHFT			8
156
-#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT		11
157
-#define UVH_BAU_DATA_CONFIG_STATUS_SHFT			12
158
-#define UVH_BAU_DATA_CONFIG_P_SHFT			13
159
-#define UVH_BAU_DATA_CONFIG_T_SHFT			15
160
-#define UVH_BAU_DATA_CONFIG_M_SHFT			16
161
-#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT		32
162
-#define UVH_BAU_DATA_CONFIG_VECTOR_MASK			0x00000000000000ffUL
163
-#define UVH_BAU_DATA_CONFIG_DM_MASK			0x0000000000000700UL
164
-#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK		0x0000000000000800UL
165
-#define UVH_BAU_DATA_CONFIG_STATUS_MASK			0x0000000000001000UL
166
-#define UVH_BAU_DATA_CONFIG_P_MASK			0x0000000000002000UL
167
-#define UVH_BAU_DATA_CONFIG_T_MASK			0x0000000000008000UL
168
-#define UVH_BAU_DATA_CONFIG_M_MASK			0x0000000000010000UL
169
-#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
170
-
171
-
172
-union uvh_bau_data_config_u {
173
-	unsigned long	v;
174
-	struct uvh_bau_data_config_s {
175
-		unsigned long	vector_:8;			/* RW */
176
-		unsigned long	dm:3;				/* RW */
177
-		unsigned long	destmode:1;			/* RW */
178
-		unsigned long	status:1;			/* RO */
179
-		unsigned long	p:1;				/* RO */
180
-		unsigned long	rsvd_14:1;
181
-		unsigned long	t:1;				/* RO */
182
-		unsigned long	m:1;				/* RW */
183
-		unsigned long	rsvd_17_31:15;
184
-		unsigned long	apic_id:32;			/* RW */
185
-	} s;
186
-};
187
-
188
-/* ========================================================================= */
18997 /*                           UVH_EVENT_OCCURRED0                             */
19098 /* ========================================================================= */
19199 #define UVH_EVENT_OCCURRED0 0x70000UL
192
-#define UVH_EVENT_OCCURRED0_32 0x5e8
193100 
101
+/* UVH common defines*/
194102 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT		0
195
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT		11
196103 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK		0x0000000000000001UL
197
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK		0x0000000000000800UL
198104 
199
-#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT		1
200
-#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT		2
201
-#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT		3
202
-#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT		4
203
-#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT		5
204
-#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT		6
205
-#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT		7
206
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT		8
207
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT		9
208
-#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT		10
209
-#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT		12
210
-#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT		13
211
-#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT		14
212
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		15
213
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		16
214
-#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT		17
215
-#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT		18
216
-#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT		19
217
-#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT		20
218
-#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT		21
219
-#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	22
220
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		23
221
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		24
222
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		25
223
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		26
224
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		27
225
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		28
226
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		29
227
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		30
228
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		31
229
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		32
230
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		33
231
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		34
232
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		35
233
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		36
234
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		37
235
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		38
236
-#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		39
237
-#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		40
238
-#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		41
239
-#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		42
240
-#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT		43
241
-#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	44
242
-#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT		45
243
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		46
244
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		47
245
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		48
246
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		49
247
-#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT		50
248
-#define UV1H_EVENT_OCCURRED0_RTC0_SHFT			51
249
-#define UV1H_EVENT_OCCURRED0_RTC1_SHFT			52
250
-#define UV1H_EVENT_OCCURRED0_RTC2_SHFT			53
251
-#define UV1H_EVENT_OCCURRED0_RTC3_SHFT			54
252
-#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT		55
253
-#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT	56
254
-#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000002UL
255
-#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000004UL
256
-#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK		0x0000000000000008UL
257
-#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000010UL
258
-#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK		0x0000000000000020UL
259
-#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK		0x0000000000000040UL
260
-#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000080UL
261
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000000100UL
262
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000000200UL
263
-#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK		0x0000000000000400UL
264
-#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK		0x0000000000001000UL
265
-#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK		0x0000000000002000UL
266
-#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000004000UL
267
-#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000000008000UL
268
-#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000000010000UL
269
-#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK		0x0000000000020000UL
270
-#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000040000UL
271
-#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK		0x0000000000080000UL
272
-#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK		0x0000000000100000UL
273
-#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK		0x0000000000200000UL
274
-#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000000400000UL
275
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000000800000UL
276
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000001000000UL
277
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000002000000UL
278
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000004000000UL
279
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000000008000000UL
280
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000000010000000UL
281
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000000020000000UL
282
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000000040000000UL
283
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000000080000000UL
284
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000000100000000UL
285
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000000200000000UL
286
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000000400000000UL
287
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000000800000000UL
288
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000001000000000UL
289
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000002000000000UL
290
-#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000004000000000UL
291
-#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0000008000000000UL
292
-#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0000010000000000UL
293
-#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0000020000000000UL
294
-#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0000040000000000UL
295
-#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK		0x0000080000000000UL
296
-#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0000100000000000UL
297
-#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK		0x0000200000000000UL
298
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0000400000000000UL
299
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0000800000000000UL
300
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0001000000000000UL
301
-#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0002000000000000UL
302
-#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0004000000000000UL
303
-#define UV1H_EVENT_OCCURRED0_RTC0_MASK			0x0008000000000000UL
304
-#define UV1H_EVENT_OCCURRED0_RTC1_MASK			0x0010000000000000UL
305
-#define UV1H_EVENT_OCCURRED0_RTC2_MASK			0x0020000000000000UL
306
-#define UV1H_EVENT_OCCURRED0_RTC3_MASK			0x0040000000000000UL
307
-#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK		0x0080000000000000UL
308
-#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK	0x0100000000000000UL
309
-
105
+/* UVXH common defines */
310106 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT		2
311
-#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT		3
312
-#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT		4
313
-#define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT		5
314
-#define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT		6
315
-#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT		7
316
-#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT		8
317
-#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT		9
318
-#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT		12
319
-#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT		13
320
-#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT		14
321
-#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT		15
322
-#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT		16
323107 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000004UL
108
+#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT		3
324109 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK		0x0000000000000008UL
110
+#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT		4
325111 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK		0x0000000000000010UL
112
+#define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT		5
326113 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000020UL
114
+#define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT		6
327115 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000040UL
116
+#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT		7
328117 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK		0x0000000000000080UL
118
+#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT		8
329119 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK		0x0000000000000100UL
120
+#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT		9
330121 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000200UL
122
+#define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT		11
123
+#define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK		0x0000000000000800UL
124
+#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT		12
331125 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK		0x0000000000001000UL
126
+#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT		13
332127 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK		0x0000000000002000UL
128
+#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT		14
333129 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000004000UL
130
+#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT		15
334131 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000008000UL
132
+#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT		16
335133 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK		0x0000000000010000UL
336134 
337
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
338
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
339
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
340
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
341
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
342
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
343
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
344
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
345
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
346
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
347
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
348
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
349
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
350
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
351
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
352
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
353
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
354
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
355
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
356
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
357
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
358
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
359
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
360
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
361
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
362
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
363
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
364
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
365
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
366
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
367
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
368
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
369
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
370
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
371
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
372
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
373
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
374
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
375
-#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT		53
376
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
377
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
378
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
379
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
380
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
381
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
382
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
383
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
384
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
385
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
386
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
387
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
388
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
389
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
390
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
391
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
392
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
393
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
394
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
395
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
396
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
397
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
398
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
399
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
400
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
401
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
402
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
403
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
404
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
405
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
406
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
407
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
408
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
409
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
410
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
411
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
412
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
413
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
414
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
415
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
416
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
417
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
418
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
419
-#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
420
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
421
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
422
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
423
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
424
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
135
+/* UVYH common defines */
136
+#define UVYH_EVENT_OCCURRED0_KT_HCERR_SHFT		1
137
+#define UVYH_EVENT_OCCURRED0_KT_HCERR_MASK		0x0000000000000002UL
138
+#define UVYH_EVENT_OCCURRED0_RH0_HCERR_SHFT		2
139
+#define UVYH_EVENT_OCCURRED0_RH0_HCERR_MASK		0x0000000000000004UL
140
+#define UVYH_EVENT_OCCURRED0_RH1_HCERR_SHFT		3
141
+#define UVYH_EVENT_OCCURRED0_RH1_HCERR_MASK		0x0000000000000008UL
142
+#define UVYH_EVENT_OCCURRED0_LH0_HCERR_SHFT		4
143
+#define UVYH_EVENT_OCCURRED0_LH0_HCERR_MASK		0x0000000000000010UL
144
+#define UVYH_EVENT_OCCURRED0_LH1_HCERR_SHFT		5
145
+#define UVYH_EVENT_OCCURRED0_LH1_HCERR_MASK		0x0000000000000020UL
146
+#define UVYH_EVENT_OCCURRED0_LH2_HCERR_SHFT		6
147
+#define UVYH_EVENT_OCCURRED0_LH2_HCERR_MASK		0x0000000000000040UL
148
+#define UVYH_EVENT_OCCURRED0_LH3_HCERR_SHFT		7
149
+#define UVYH_EVENT_OCCURRED0_LH3_HCERR_MASK		0x0000000000000080UL
150
+#define UVYH_EVENT_OCCURRED0_XB_HCERR_SHFT		8
151
+#define UVYH_EVENT_OCCURRED0_XB_HCERR_MASK		0x0000000000000100UL
152
+#define UVYH_EVENT_OCCURRED0_RDM_HCERR_SHFT		9
153
+#define UVYH_EVENT_OCCURRED0_RDM_HCERR_MASK		0x0000000000000200UL
154
+#define UVYH_EVENT_OCCURRED0_NI0_HCERR_SHFT		10
155
+#define UVYH_EVENT_OCCURRED0_NI0_HCERR_MASK		0x0000000000000400UL
156
+#define UVYH_EVENT_OCCURRED0_NI1_HCERR_SHFT		11
157
+#define UVYH_EVENT_OCCURRED0_NI1_HCERR_MASK		0x0000000000000800UL
158
+#define UVYH_EVENT_OCCURRED0_LB_AOERR0_SHFT		12
159
+#define UVYH_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000001000UL
160
+#define UVYH_EVENT_OCCURRED0_KT_AOERR0_SHFT		13
161
+#define UVYH_EVENT_OCCURRED0_KT_AOERR0_MASK		0x0000000000002000UL
162
+#define UVYH_EVENT_OCCURRED0_RH0_AOERR0_SHFT		14
163
+#define UVYH_EVENT_OCCURRED0_RH0_AOERR0_MASK		0x0000000000004000UL
164
+#define UVYH_EVENT_OCCURRED0_RH1_AOERR0_SHFT		15
165
+#define UVYH_EVENT_OCCURRED0_RH1_AOERR0_MASK		0x0000000000008000UL
166
+#define UVYH_EVENT_OCCURRED0_LH0_AOERR0_SHFT		16
167
+#define UVYH_EVENT_OCCURRED0_LH0_AOERR0_MASK		0x0000000000010000UL
168
+#define UVYH_EVENT_OCCURRED0_LH1_AOERR0_SHFT		17
169
+#define UVYH_EVENT_OCCURRED0_LH1_AOERR0_MASK		0x0000000000020000UL
170
+#define UVYH_EVENT_OCCURRED0_LH2_AOERR0_SHFT		18
171
+#define UVYH_EVENT_OCCURRED0_LH2_AOERR0_MASK		0x0000000000040000UL
172
+#define UVYH_EVENT_OCCURRED0_LH3_AOERR0_SHFT		19
173
+#define UVYH_EVENT_OCCURRED0_LH3_AOERR0_MASK		0x0000000000080000UL
174
+#define UVYH_EVENT_OCCURRED0_XB_AOERR0_SHFT		20
175
+#define UVYH_EVENT_OCCURRED0_XB_AOERR0_MASK		0x0000000000100000UL
176
+#define UVYH_EVENT_OCCURRED0_RDM_AOERR0_SHFT		21
177
+#define UVYH_EVENT_OCCURRED0_RDM_AOERR0_MASK		0x0000000000200000UL
178
+#define UVYH_EVENT_OCCURRED0_RT0_AOERR0_SHFT		22
179
+#define UVYH_EVENT_OCCURRED0_RT0_AOERR0_MASK		0x0000000000400000UL
180
+#define UVYH_EVENT_OCCURRED0_RT1_AOERR0_SHFT		23
181
+#define UVYH_EVENT_OCCURRED0_RT1_AOERR0_MASK		0x0000000000800000UL
182
+#define UVYH_EVENT_OCCURRED0_NI0_AOERR0_SHFT		24
183
+#define UVYH_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000001000000UL
184
+#define UVYH_EVENT_OCCURRED0_NI1_AOERR0_SHFT		25
185
+#define UVYH_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000002000000UL
186
+#define UVYH_EVENT_OCCURRED0_LB_AOERR1_SHFT		26
187
+#define UVYH_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000004000000UL
188
+#define UVYH_EVENT_OCCURRED0_KT_AOERR1_SHFT		27
189
+#define UVYH_EVENT_OCCURRED0_KT_AOERR1_MASK		0x0000000008000000UL
190
+#define UVYH_EVENT_OCCURRED0_RH0_AOERR1_SHFT		28
191
+#define UVYH_EVENT_OCCURRED0_RH0_AOERR1_MASK		0x0000000010000000UL
192
+#define UVYH_EVENT_OCCURRED0_RH1_AOERR1_SHFT		29
193
+#define UVYH_EVENT_OCCURRED0_RH1_AOERR1_MASK		0x0000000020000000UL
194
+#define UVYH_EVENT_OCCURRED0_LH0_AOERR1_SHFT		30
195
+#define UVYH_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000040000000UL
196
+#define UVYH_EVENT_OCCURRED0_LH1_AOERR1_SHFT		31
197
+#define UVYH_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000080000000UL
198
+#define UVYH_EVENT_OCCURRED0_LH2_AOERR1_SHFT		32
199
+#define UVYH_EVENT_OCCURRED0_LH2_AOERR1_MASK		0x0000000100000000UL
200
+#define UVYH_EVENT_OCCURRED0_LH3_AOERR1_SHFT		33
201
+#define UVYH_EVENT_OCCURRED0_LH3_AOERR1_MASK		0x0000000200000000UL
202
+#define UVYH_EVENT_OCCURRED0_XB_AOERR1_SHFT		34
203
+#define UVYH_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000400000000UL
204
+#define UVYH_EVENT_OCCURRED0_RDM_AOERR1_SHFT		35
205
+#define UVYH_EVENT_OCCURRED0_RDM_AOERR1_MASK		0x0000000800000000UL
206
+#define UVYH_EVENT_OCCURRED0_RT0_AOERR1_SHFT		36
207
+#define UVYH_EVENT_OCCURRED0_RT0_AOERR1_MASK		0x0000001000000000UL
208
+#define UVYH_EVENT_OCCURRED0_RT1_AOERR1_SHFT		37
209
+#define UVYH_EVENT_OCCURRED0_RT1_AOERR1_MASK		0x0000002000000000UL
210
+#define UVYH_EVENT_OCCURRED0_NI0_AOERR1_SHFT		38
211
+#define UVYH_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000004000000000UL
212
+#define UVYH_EVENT_OCCURRED0_NI1_AOERR1_SHFT		39
213
+#define UVYH_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000008000000000UL
214
+#define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	40
215
+#define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000010000000000UL
216
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		41
217
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000020000000000UL
218
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		42
219
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000040000000000UL
220
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		43
221
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000080000000000UL
222
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		44
223
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000100000000000UL
224
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		45
225
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000200000000000UL
226
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		46
227
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000400000000000UL
228
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		47
229
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000800000000000UL
230
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		48
231
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0001000000000000UL
232
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		49
233
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0002000000000000UL
234
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		50
235
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0004000000000000UL
236
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		51
237
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0008000000000000UL
238
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		52
239
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0010000000000000UL
240
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		53
241
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0020000000000000UL
242
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		54
243
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0040000000000000UL
244
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		55
245
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0080000000000000UL
246
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		56
247
+#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0100000000000000UL
248
+#define UVYH_EVENT_OCCURRED0_L1_NMI_INT_SHFT		57
249
+#define UVYH_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0200000000000000UL
250
+#define UVYH_EVENT_OCCURRED0_STOP_CLOCK_SHFT		58
251
+#define UVYH_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0400000000000000UL
252
+#define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		59
253
+#define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0800000000000000UL
254
+#define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		60
255
+#define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x1000000000000000UL
256
+#define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	61
257
+#define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x2000000000000000UL
425258 
426
-#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
427
-#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
428
-#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
429
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
430
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
431
-#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
432
-#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
433
-#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
434
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
435
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
436
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
437
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
438
-#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
439
-#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
440
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
441
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
442
-#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
443
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
444
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
445
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
446
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
447
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
448
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
449
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
450
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
451
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
452
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
453
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
454
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
455
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
456
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
457
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
458
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
459
-#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
460
-#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
461
-#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
462
-#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
463
-#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
464
-#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT		53
465
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
466
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
467
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
468
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
469
-#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
470
-#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
471
-#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
472
-#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
473
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
474
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
475
-#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
476
-#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
477
-#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
478
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
479
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
480
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
481
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
482
-#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
483
-#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
484
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
485
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
486
-#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
487
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
488
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
489
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
490
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
491
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
492
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
493
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
494
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
495
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
496
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
497
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
498
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
499
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
500
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
501
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
502
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
503
-#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
504
-#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
505
-#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
506
-#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
507
-#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
508
-#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
509
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
510
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
511
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
512
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
513
-#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
514
-
259
+/* UV4 unique defines */
515260 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT		1
516
-#define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT		10
517
-#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT		17
518
-#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT		18
519
-#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT		19
520
-#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT		20
521
-#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		21
522
-#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		22
523
-#define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT		23
524
-#define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT		24
525
-#define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT		25
526
-#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		26
527
-#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		27
528
-#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		28
529
-#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		29
530
-#define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT		30
531
-#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT		31
532
-#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT		32
533
-#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT		33
534
-#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT		34
535
-#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		35
536
-#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		36
537
-#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	37
538
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		38
539
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		39
540
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		40
541
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		41
542
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		42
543
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		43
544
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		44
545
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		45
546
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		46
547
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		47
548
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		48
549
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		49
550
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		50
551
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		51
552
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		52
553
-#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		53
554
-#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		54
555
-#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		55
556
-#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		56
557
-#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		57
558
-#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	58
559
-#define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT		59
560
-#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		60
561
-#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		61
562
-#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		62
563
-#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		63
564261 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK		0x0000000000000002UL
262
+#define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT		10
565263 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK		0x0000000000000400UL
264
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT		17
566265 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK		0x0000000000020000UL
266
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT		18
567267 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK		0x0000000000040000UL
268
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT		19
568269 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK		0x0000000000080000UL
270
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT		20
569271 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK		0x0000000000100000UL
272
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		21
570273 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000200000UL
274
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		22
571275 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000400000UL
276
+#define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT		23
572277 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000800000UL
278
+#define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT		24
573279 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK		0x0000000001000000UL
280
+#define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT		25
574281 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000002000000UL
282
+#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		26
575283 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000004000000UL
284
+#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		27
576285 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000008000000UL
286
+#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		28
577287 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000010000000UL
288
+#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		29
578289 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000020000000UL
290
+#define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT		30
579291 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000040000000UL
292
+#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT		31
580293 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK		0x0000000080000000UL
294
+#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT		32
581295 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK		0x0000000100000000UL
296
+#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT		33
582297 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK		0x0000000200000000UL
298
+#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT		34
583299 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK		0x0000000400000000UL
300
+#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		35
584301 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000800000000UL
302
+#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		36
585303 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000001000000000UL
304
+#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	37
586305 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000002000000000UL
306
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		38
587307 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000004000000000UL
308
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		39
588309 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000008000000000UL
310
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		40
589311 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000010000000000UL
312
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		41
590313 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000020000000000UL
314
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		42
591315 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000040000000000UL
316
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		43
592317 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000080000000000UL
318
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		44
593319 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000100000000000UL
320
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		45
594321 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000200000000000UL
322
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		46
595323 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000400000000000UL
324
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		47
596325 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000800000000000UL
326
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		48
597327 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0001000000000000UL
328
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		49
598329 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0002000000000000UL
330
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		50
599331 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0004000000000000UL
332
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		51
600333 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0008000000000000UL
334
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		52
601335 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0010000000000000UL
336
+#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		53
602337 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0020000000000000UL
338
+#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		54
603339 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0040000000000000UL
340
+#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		55
604341 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0080000000000000UL
342
+#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		56
605343 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0100000000000000UL
344
+#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		57
606345 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0200000000000000UL
346
+#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	58
607347 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0400000000000000UL
348
+#define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT		59
608349 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK		0x0800000000000000UL
350
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		60
609351 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x1000000000000000UL
352
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		61
610353 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x2000000000000000UL
354
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		62
611355 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x4000000000000000UL
356
+#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		63
612357 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x8000000000000000UL
613358 
359
+/* UV3 unique defines */
360
+#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
361
+#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
362
+#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
363
+#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
364
+#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
365
+#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
366
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
367
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
368
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
369
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
370
+#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
371
+#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
372
+#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
373
+#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
374
+#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
375
+#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
376
+#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
377
+#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
378
+#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
379
+#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
380
+#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
381
+#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
382
+#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
383
+#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
384
+#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
385
+#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
386
+#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
387
+#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
388
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
389
+#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
390
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
391
+#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
392
+#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
393
+#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
394
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
395
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
396
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
397
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
398
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
399
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
400
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
401
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
402
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
403
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
404
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
405
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
406
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
407
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
408
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
409
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
410
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
411
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
412
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
413
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
414
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
415
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
416
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
417
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
418
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
419
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
420
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
421
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
422
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
423
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
424
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
425
+#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
426
+#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
427
+#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
428
+#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
429
+#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
430
+#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
431
+#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
432
+#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
433
+#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
434
+#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
435
+#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
436
+#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT		53
437
+#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
438
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
439
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
440
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
441
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
442
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
443
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
444
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
445
+#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
446
+#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
447
+#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
448
+
449
+/* UV2 unique defines */
450
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
451
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
452
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
453
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
454
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
455
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
456
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
457
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
458
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
459
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
460
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
461
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
462
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
463
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
464
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
465
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
466
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
467
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
468
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
469
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
470
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
471
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
472
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
473
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
474
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
475
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
476
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
477
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
478
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
479
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
480
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
481
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
482
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
483
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
484
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
485
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
486
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
487
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
488
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
489
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
490
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
491
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
492
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
493
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
494
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
495
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
496
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
497
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
498
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
499
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
500
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
501
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
502
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
503
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
504
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
505
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
506
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
507
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
508
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
509
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
510
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
511
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
512
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
513
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
514
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
515
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
516
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
517
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
518
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
519
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
520
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
521
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
522
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
523
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
524
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
525
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
526
+#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT		53
527
+#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
528
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
529
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
530
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
531
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
532
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
533
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
534
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
535
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
536
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
537
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
538
+
539
+#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK (				\
540
+	is_uv(UV4) ? 0x1000000000000000UL :				\
541
+	is_uv(UV3) ? 0x0040000000000000UL :				\
542
+	is_uv(UV2) ? 0x0040000000000000UL :				\
543
+	0)
614544 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT (				\
615
-	is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
616
-	is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
617
-	is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
618
-	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
545
+	is_uv(UV4) ? 60 :						\
546
+	is_uv(UV3) ? 54 :						\
547
+	is_uv(UV2) ? 54 :						\
548
+	-1)
619549 
620550 union uvh_event_occurred0_u {
621551 	unsigned long	v;
552
+
553
+	/* UVH common struct */
622554 	struct uvh_event_occurred0_s {
623
-		unsigned long	lb_hcerr:1;			/* RW, W1C */
624
-		unsigned long	rsvd_1_10:10;
625
-		unsigned long	rh_aoerr0:1;			/* RW, W1C */
626
-		unsigned long	rsvd_12_63:52;
555
+		unsigned long	lb_hcerr:1;			/* RW */
556
+		unsigned long	rsvd_1_63:63;
627557 	} s;
558
+
559
+	/* UVXH common struct */
628560 	struct uvxh_event_occurred0_s {
629561 		unsigned long	lb_hcerr:1;			/* RW */
630562 		unsigned long	rsvd_1:1;
....@@ -645,6 +577,142 @@
645577 		unsigned long	xb_aoerr0:1;			/* RW */
646578 		unsigned long	rsvd_17_63:47;
647579 	} sx;
580
+
581
+	/* UVYH common struct */
582
+	struct uvyh_event_occurred0_s {
583
+		unsigned long	lb_hcerr:1;			/* RW */
584
+		unsigned long	kt_hcerr:1;			/* RW */
585
+		unsigned long	rh0_hcerr:1;			/* RW */
586
+		unsigned long	rh1_hcerr:1;			/* RW */
587
+		unsigned long	lh0_hcerr:1;			/* RW */
588
+		unsigned long	lh1_hcerr:1;			/* RW */
589
+		unsigned long	lh2_hcerr:1;			/* RW */
590
+		unsigned long	lh3_hcerr:1;			/* RW */
591
+		unsigned long	xb_hcerr:1;			/* RW */
592
+		unsigned long	rdm_hcerr:1;			/* RW */
593
+		unsigned long	ni0_hcerr:1;			/* RW */
594
+		unsigned long	ni1_hcerr:1;			/* RW */
595
+		unsigned long	lb_aoerr0:1;			/* RW */
596
+		unsigned long	kt_aoerr0:1;			/* RW */
597
+		unsigned long	rh0_aoerr0:1;			/* RW */
598
+		unsigned long	rh1_aoerr0:1;			/* RW */
599
+		unsigned long	lh0_aoerr0:1;			/* RW */
600
+		unsigned long	lh1_aoerr0:1;			/* RW */
601
+		unsigned long	lh2_aoerr0:1;			/* RW */
602
+		unsigned long	lh3_aoerr0:1;			/* RW */
603
+		unsigned long	xb_aoerr0:1;			/* RW */
604
+		unsigned long	rdm_aoerr0:1;			/* RW */
605
+		unsigned long	rt0_aoerr0:1;			/* RW */
606
+		unsigned long	rt1_aoerr0:1;			/* RW */
607
+		unsigned long	ni0_aoerr0:1;			/* RW */
608
+		unsigned long	ni1_aoerr0:1;			/* RW */
609
+		unsigned long	lb_aoerr1:1;			/* RW */
610
+		unsigned long	kt_aoerr1:1;			/* RW */
611
+		unsigned long	rh0_aoerr1:1;			/* RW */
612
+		unsigned long	rh1_aoerr1:1;			/* RW */
613
+		unsigned long	lh0_aoerr1:1;			/* RW */
614
+		unsigned long	lh1_aoerr1:1;			/* RW */
615
+		unsigned long	lh2_aoerr1:1;			/* RW */
616
+		unsigned long	lh3_aoerr1:1;			/* RW */
617
+		unsigned long	xb_aoerr1:1;			/* RW */
618
+		unsigned long	rdm_aoerr1:1;			/* RW */
619
+		unsigned long	rt0_aoerr1:1;			/* RW */
620
+		unsigned long	rt1_aoerr1:1;			/* RW */
621
+		unsigned long	ni0_aoerr1:1;			/* RW */
622
+		unsigned long	ni1_aoerr1:1;			/* RW */
623
+		unsigned long	system_shutdown_int:1;		/* RW */
624
+		unsigned long	lb_irq_int_0:1;			/* RW */
625
+		unsigned long	lb_irq_int_1:1;			/* RW */
626
+		unsigned long	lb_irq_int_2:1;			/* RW */
627
+		unsigned long	lb_irq_int_3:1;			/* RW */
628
+		unsigned long	lb_irq_int_4:1;			/* RW */
629
+		unsigned long	lb_irq_int_5:1;			/* RW */
630
+		unsigned long	lb_irq_int_6:1;			/* RW */
631
+		unsigned long	lb_irq_int_7:1;			/* RW */
632
+		unsigned long	lb_irq_int_8:1;			/* RW */
633
+		unsigned long	lb_irq_int_9:1;			/* RW */
634
+		unsigned long	lb_irq_int_10:1;		/* RW */
635
+		unsigned long	lb_irq_int_11:1;		/* RW */
636
+		unsigned long	lb_irq_int_12:1;		/* RW */
637
+		unsigned long	lb_irq_int_13:1;		/* RW */
638
+		unsigned long	lb_irq_int_14:1;		/* RW */
639
+		unsigned long	lb_irq_int_15:1;		/* RW */
640
+		unsigned long	l1_nmi_int:1;			/* RW */
641
+		unsigned long	stop_clock:1;			/* RW */
642
+		unsigned long	asic_to_l1:1;			/* RW */
643
+		unsigned long	l1_to_asic:1;			/* RW */
644
+		unsigned long	la_seq_trigger:1;		/* RW */
645
+		unsigned long	rsvd_62_63:2;
646
+	} sy;
647
+
648
+	/* UV5 unique struct */
649
+	struct uv5h_event_occurred0_s {
650
+		unsigned long	lb_hcerr:1;			/* RW */
651
+		unsigned long	kt_hcerr:1;			/* RW */
652
+		unsigned long	rh0_hcerr:1;			/* RW */
653
+		unsigned long	rh1_hcerr:1;			/* RW */
654
+		unsigned long	lh0_hcerr:1;			/* RW */
655
+		unsigned long	lh1_hcerr:1;			/* RW */
656
+		unsigned long	lh2_hcerr:1;			/* RW */
657
+		unsigned long	lh3_hcerr:1;			/* RW */
658
+		unsigned long	xb_hcerr:1;			/* RW */
659
+		unsigned long	rdm_hcerr:1;			/* RW */
660
+		unsigned long	ni0_hcerr:1;			/* RW */
661
+		unsigned long	ni1_hcerr:1;			/* RW */
662
+		unsigned long	lb_aoerr0:1;			/* RW */
663
+		unsigned long	kt_aoerr0:1;			/* RW */
664
+		unsigned long	rh0_aoerr0:1;			/* RW */
665
+		unsigned long	rh1_aoerr0:1;			/* RW */
666
+		unsigned long	lh0_aoerr0:1;			/* RW */
667
+		unsigned long	lh1_aoerr0:1;			/* RW */
668
+		unsigned long	lh2_aoerr0:1;			/* RW */
669
+		unsigned long	lh3_aoerr0:1;			/* RW */
670
+		unsigned long	xb_aoerr0:1;			/* RW */
671
+		unsigned long	rdm_aoerr0:1;			/* RW */
672
+		unsigned long	rt0_aoerr0:1;			/* RW */
673
+		unsigned long	rt1_aoerr0:1;			/* RW */
674
+		unsigned long	ni0_aoerr0:1;			/* RW */
675
+		unsigned long	ni1_aoerr0:1;			/* RW */
676
+		unsigned long	lb_aoerr1:1;			/* RW */
677
+		unsigned long	kt_aoerr1:1;			/* RW */
678
+		unsigned long	rh0_aoerr1:1;			/* RW */
679
+		unsigned long	rh1_aoerr1:1;			/* RW */
680
+		unsigned long	lh0_aoerr1:1;			/* RW */
681
+		unsigned long	lh1_aoerr1:1;			/* RW */
682
+		unsigned long	lh2_aoerr1:1;			/* RW */
683
+		unsigned long	lh3_aoerr1:1;			/* RW */
684
+		unsigned long	xb_aoerr1:1;			/* RW */
685
+		unsigned long	rdm_aoerr1:1;			/* RW */
686
+		unsigned long	rt0_aoerr1:1;			/* RW */
687
+		unsigned long	rt1_aoerr1:1;			/* RW */
688
+		unsigned long	ni0_aoerr1:1;			/* RW */
689
+		unsigned long	ni1_aoerr1:1;			/* RW */
690
+		unsigned long	system_shutdown_int:1;		/* RW */
691
+		unsigned long	lb_irq_int_0:1;			/* RW */
692
+		unsigned long	lb_irq_int_1:1;			/* RW */
693
+		unsigned long	lb_irq_int_2:1;			/* RW */
694
+		unsigned long	lb_irq_int_3:1;			/* RW */
695
+		unsigned long	lb_irq_int_4:1;			/* RW */
696
+		unsigned long	lb_irq_int_5:1;			/* RW */
697
+		unsigned long	lb_irq_int_6:1;			/* RW */
698
+		unsigned long	lb_irq_int_7:1;			/* RW */
699
+		unsigned long	lb_irq_int_8:1;			/* RW */
700
+		unsigned long	lb_irq_int_9:1;			/* RW */
701
+		unsigned long	lb_irq_int_10:1;		/* RW */
702
+		unsigned long	lb_irq_int_11:1;		/* RW */
703
+		unsigned long	lb_irq_int_12:1;		/* RW */
704
+		unsigned long	lb_irq_int_13:1;		/* RW */
705
+		unsigned long	lb_irq_int_14:1;		/* RW */
706
+		unsigned long	lb_irq_int_15:1;		/* RW */
707
+		unsigned long	l1_nmi_int:1;			/* RW */
708
+		unsigned long	stop_clock:1;			/* RW */
709
+		unsigned long	asic_to_l1:1;			/* RW */
710
+		unsigned long	l1_to_asic:1;			/* RW */
711
+		unsigned long	la_seq_trigger:1;		/* RW */
712
+		unsigned long	rsvd_62_63:2;
713
+	} s5;
714
+
715
+	/* UV4 unique struct */
648716 	struct uv4h_event_occurred0_s {
649717 		unsigned long	lb_hcerr:1;			/* RW */
650718 		unsigned long	kt_hcerr:1;			/* RW */
....@@ -711,3834 +779,1147 @@
711779 		unsigned long	extio_int2:1;			/* RW */
712780 		unsigned long	extio_int3:1;			/* RW */
713781 	} s4;
782
+
783
+	/* UV3 unique struct */
784
+	struct uv3h_event_occurred0_s {
785
+		unsigned long	lb_hcerr:1;			/* RW */
786
+		unsigned long	qp_hcerr:1;			/* RW */
787
+		unsigned long	rh_hcerr:1;			/* RW */
788
+		unsigned long	lh0_hcerr:1;			/* RW */
789
+		unsigned long	lh1_hcerr:1;			/* RW */
790
+		unsigned long	gr0_hcerr:1;			/* RW */
791
+		unsigned long	gr1_hcerr:1;			/* RW */
792
+		unsigned long	ni0_hcerr:1;			/* RW */
793
+		unsigned long	ni1_hcerr:1;			/* RW */
794
+		unsigned long	lb_aoerr0:1;			/* RW */
795
+		unsigned long	qp_aoerr0:1;			/* RW */
796
+		unsigned long	rh_aoerr0:1;			/* RW */
797
+		unsigned long	lh0_aoerr0:1;			/* RW */
798
+		unsigned long	lh1_aoerr0:1;			/* RW */
799
+		unsigned long	gr0_aoerr0:1;			/* RW */
800
+		unsigned long	gr1_aoerr0:1;			/* RW */
801
+		unsigned long	xb_aoerr0:1;			/* RW */
802
+		unsigned long	rt_aoerr0:1;			/* RW */
803
+		unsigned long	ni0_aoerr0:1;			/* RW */
804
+		unsigned long	ni1_aoerr0:1;			/* RW */
805
+		unsigned long	lb_aoerr1:1;			/* RW */
806
+		unsigned long	qp_aoerr1:1;			/* RW */
807
+		unsigned long	rh_aoerr1:1;			/* RW */
808
+		unsigned long	lh0_aoerr1:1;			/* RW */
809
+		unsigned long	lh1_aoerr1:1;			/* RW */
810
+		unsigned long	gr0_aoerr1:1;			/* RW */
811
+		unsigned long	gr1_aoerr1:1;			/* RW */
812
+		unsigned long	xb_aoerr1:1;			/* RW */
813
+		unsigned long	rt_aoerr1:1;			/* RW */
814
+		unsigned long	ni0_aoerr1:1;			/* RW */
815
+		unsigned long	ni1_aoerr1:1;			/* RW */
816
+		unsigned long	system_shutdown_int:1;		/* RW */
817
+		unsigned long	lb_irq_int_0:1;			/* RW */
818
+		unsigned long	lb_irq_int_1:1;			/* RW */
819
+		unsigned long	lb_irq_int_2:1;			/* RW */
820
+		unsigned long	lb_irq_int_3:1;			/* RW */
821
+		unsigned long	lb_irq_int_4:1;			/* RW */
822
+		unsigned long	lb_irq_int_5:1;			/* RW */
823
+		unsigned long	lb_irq_int_6:1;			/* RW */
824
+		unsigned long	lb_irq_int_7:1;			/* RW */
825
+		unsigned long	lb_irq_int_8:1;			/* RW */
826
+		unsigned long	lb_irq_int_9:1;			/* RW */
827
+		unsigned long	lb_irq_int_10:1;		/* RW */
828
+		unsigned long	lb_irq_int_11:1;		/* RW */
829
+		unsigned long	lb_irq_int_12:1;		/* RW */
830
+		unsigned long	lb_irq_int_13:1;		/* RW */
831
+		unsigned long	lb_irq_int_14:1;		/* RW */
832
+		unsigned long	lb_irq_int_15:1;		/* RW */
833
+		unsigned long	l1_nmi_int:1;			/* RW */
834
+		unsigned long	stop_clock:1;			/* RW */
835
+		unsigned long	asic_to_l1:1;			/* RW */
836
+		unsigned long	l1_to_asic:1;			/* RW */
837
+		unsigned long	la_seq_trigger:1;		/* RW */
838
+		unsigned long	ipi_int:1;			/* RW */
839
+		unsigned long	extio_int0:1;			/* RW */
840
+		unsigned long	extio_int1:1;			/* RW */
841
+		unsigned long	extio_int2:1;			/* RW */
842
+		unsigned long	extio_int3:1;			/* RW */
843
+		unsigned long	profile_int:1;			/* RW */
844
+		unsigned long	rsvd_59_63:5;
845
+	} s3;
846
+
847
+	/* UV2 unique struct */
848
+	struct uv2h_event_occurred0_s {
849
+		unsigned long	lb_hcerr:1;			/* RW */
850
+		unsigned long	qp_hcerr:1;			/* RW */
851
+		unsigned long	rh_hcerr:1;			/* RW */
852
+		unsigned long	lh0_hcerr:1;			/* RW */
853
+		unsigned long	lh1_hcerr:1;			/* RW */
854
+		unsigned long	gr0_hcerr:1;			/* RW */
855
+		unsigned long	gr1_hcerr:1;			/* RW */
856
+		unsigned long	ni0_hcerr:1;			/* RW */
857
+		unsigned long	ni1_hcerr:1;			/* RW */
858
+		unsigned long	lb_aoerr0:1;			/* RW */
859
+		unsigned long	qp_aoerr0:1;			/* RW */
860
+		unsigned long	rh_aoerr0:1;			/* RW */
861
+		unsigned long	lh0_aoerr0:1;			/* RW */
862
+		unsigned long	lh1_aoerr0:1;			/* RW */
863
+		unsigned long	gr0_aoerr0:1;			/* RW */
864
+		unsigned long	gr1_aoerr0:1;			/* RW */
865
+		unsigned long	xb_aoerr0:1;			/* RW */
866
+		unsigned long	rt_aoerr0:1;			/* RW */
867
+		unsigned long	ni0_aoerr0:1;			/* RW */
868
+		unsigned long	ni1_aoerr0:1;			/* RW */
869
+		unsigned long	lb_aoerr1:1;			/* RW */
870
+		unsigned long	qp_aoerr1:1;			/* RW */
871
+		unsigned long	rh_aoerr1:1;			/* RW */
872
+		unsigned long	lh0_aoerr1:1;			/* RW */
873
+		unsigned long	lh1_aoerr1:1;			/* RW */
874
+		unsigned long	gr0_aoerr1:1;			/* RW */
875
+		unsigned long	gr1_aoerr1:1;			/* RW */
876
+		unsigned long	xb_aoerr1:1;			/* RW */
877
+		unsigned long	rt_aoerr1:1;			/* RW */
878
+		unsigned long	ni0_aoerr1:1;			/* RW */
879
+		unsigned long	ni1_aoerr1:1;			/* RW */
880
+		unsigned long	system_shutdown_int:1;		/* RW */
881
+		unsigned long	lb_irq_int_0:1;			/* RW */
882
+		unsigned long	lb_irq_int_1:1;			/* RW */
883
+		unsigned long	lb_irq_int_2:1;			/* RW */
884
+		unsigned long	lb_irq_int_3:1;			/* RW */
885
+		unsigned long	lb_irq_int_4:1;			/* RW */
886
+		unsigned long	lb_irq_int_5:1;			/* RW */
887
+		unsigned long	lb_irq_int_6:1;			/* RW */
888
+		unsigned long	lb_irq_int_7:1;			/* RW */
889
+		unsigned long	lb_irq_int_8:1;			/* RW */
890
+		unsigned long	lb_irq_int_9:1;			/* RW */
891
+		unsigned long	lb_irq_int_10:1;		/* RW */
892
+		unsigned long	lb_irq_int_11:1;		/* RW */
893
+		unsigned long	lb_irq_int_12:1;		/* RW */
894
+		unsigned long	lb_irq_int_13:1;		/* RW */
895
+		unsigned long	lb_irq_int_14:1;		/* RW */
896
+		unsigned long	lb_irq_int_15:1;		/* RW */
897
+		unsigned long	l1_nmi_int:1;			/* RW */
898
+		unsigned long	stop_clock:1;			/* RW */
899
+		unsigned long	asic_to_l1:1;			/* RW */
900
+		unsigned long	l1_to_asic:1;			/* RW */
901
+		unsigned long	la_seq_trigger:1;		/* RW */
902
+		unsigned long	ipi_int:1;			/* RW */
903
+		unsigned long	extio_int0:1;			/* RW */
904
+		unsigned long	extio_int1:1;			/* RW */
905
+		unsigned long	extio_int2:1;			/* RW */
906
+		unsigned long	extio_int3:1;			/* RW */
907
+		unsigned long	profile_int:1;			/* RW */
908
+		unsigned long	rsvd_59_63:5;
909
+	} s2;
714910 };
715911 
716912 /* ========================================================================= */
717913 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
718914 /* ========================================================================= */
719915 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
720
-#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
721916 
722917 
723918 /* ========================================================================= */
724
-/*                         UVH_EXTIO_INT0_BROADCAST                          */
919
+/*                           UVH_EVENT_OCCURRED1                             */
725920 /* ========================================================================= */
726
-#define UVH_EXTIO_INT0_BROADCAST 0x61448UL
727
-
728
-#define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0
729
-#define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0
730
-#define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0
731
-#define UV4H_EXTIO_INT0_BROADCAST_32 0x310
732
-#define UVH_EXTIO_INT0_BROADCAST_32 (					\
733
-	is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 :			\
734
-	is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 :			\
735
-	is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 :			\
736
-	/*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32)
737
-
738
-#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT		0
739
-#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK		0x0000000000000001UL
921
+#define UVH_EVENT_OCCURRED1 0x70080UL
740922 
741923 
742
-union uvh_extio_int0_broadcast_u {
924
+
925
+/* UVYH common defines */
926
+#define UVYH_EVENT_OCCURRED1_IPI_INT_SHFT		0
927
+#define UVYH_EVENT_OCCURRED1_IPI_INT_MASK		0x0000000000000001UL
928
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT0_SHFT		1
929
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT0_MASK		0x0000000000000002UL
930
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT1_SHFT		2
931
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT1_MASK		0x0000000000000004UL
932
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT2_SHFT		3
933
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT2_MASK		0x0000000000000008UL
934
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT3_SHFT		4
935
+#define UVYH_EVENT_OCCURRED1_EXTIO_INT3_MASK		0x0000000000000010UL
936
+#define UVYH_EVENT_OCCURRED1_PROFILE_INT_SHFT		5
937
+#define UVYH_EVENT_OCCURRED1_PROFILE_INT_MASK		0x0000000000000020UL
938
+#define UVYH_EVENT_OCCURRED1_BAU_DATA_SHFT		6
939
+#define UVYH_EVENT_OCCURRED1_BAU_DATA_MASK		0x0000000000000040UL
940
+#define UVYH_EVENT_OCCURRED1_PROC_GENERAL_SHFT		7
941
+#define UVYH_EVENT_OCCURRED1_PROC_GENERAL_MASK		0x0000000000000080UL
942
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_SHFT		8
943
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_MASK		0x0000000000000100UL
944
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_SHFT		9
945
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_MASK		0x0000000000000200UL
946
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_SHFT		10
947
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_MASK		0x0000000000000400UL
948
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_SHFT		11
949
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_MASK		0x0000000000000800UL
950
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_SHFT		12
951
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_MASK		0x0000000000001000UL
952
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_SHFT		13
953
+#define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_MASK		0x0000000000002000UL
954
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_SHFT		14
955
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_MASK		0x0000000000004000UL
956
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_SHFT		15
957
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_MASK		0x0000000000008000UL
958
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_SHFT		16
959
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_MASK		0x0000000000010000UL
960
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_SHFT		17
961
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_MASK		0x0000000000020000UL
962
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_SHFT		18
963
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_MASK		0x0000000000040000UL
964
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_SHFT		19
965
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_MASK		0x0000000000080000UL
966
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_SHFT		20
967
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_MASK		0x0000000000100000UL
968
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_SHFT		21
969
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_MASK		0x0000000000200000UL
970
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_SHFT		22
971
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_MASK		0x0000000000400000UL
972
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_SHFT		23
973
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_MASK		0x0000000000800000UL
974
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_SHFT		24
975
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_MASK		0x0000000001000000UL
976
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_SHFT		25
977
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_MASK		0x0000000002000000UL
978
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_SHFT		26
979
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_MASK		0x0000000004000000UL
980
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_SHFT		27
981
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_MASK		0x0000000008000000UL
982
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_SHFT		28
983
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_MASK		0x0000000010000000UL
984
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_SHFT		29
985
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_MASK		0x0000000020000000UL
986
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_SHFT		30
987
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_MASK		0x0000000040000000UL
988
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_SHFT		31
989
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_MASK		0x0000000080000000UL
990
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_SHFT		32
991
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_MASK		0x0000000100000000UL
992
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_SHFT		33
993
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_MASK		0x0000000200000000UL
994
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_SHFT		34
995
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_MASK		0x0000000400000000UL
996
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_SHFT		35
997
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_MASK		0x0000000800000000UL
998
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_SHFT		36
999
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_MASK		0x0000001000000000UL
1000
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_SHFT		37
1001
+#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_MASK		0x0000002000000000UL
1002
+
1003
+/* UV4 unique defines */
1004
+#define UV4H_EVENT_OCCURRED1_PROFILE_INT_SHFT		0
1005
+#define UV4H_EVENT_OCCURRED1_PROFILE_INT_MASK		0x0000000000000001UL
1006
+#define UV4H_EVENT_OCCURRED1_BAU_DATA_SHFT		1
1007
+#define UV4H_EVENT_OCCURRED1_BAU_DATA_MASK		0x0000000000000002UL
1008
+#define UV4H_EVENT_OCCURRED1_PROC_GENERAL_SHFT		2
1009
+#define UV4H_EVENT_OCCURRED1_PROC_GENERAL_MASK		0x0000000000000004UL
1010
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT		3
1011
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK		0x0000000000000008UL
1012
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT		4
1013
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK		0x0000000000000010UL
1014
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT		5
1015
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK		0x0000000000000020UL
1016
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT		6
1017
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK		0x0000000000000040UL
1018
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT		7
1019
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK		0x0000000000000080UL
1020
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT		8
1021
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK		0x0000000000000100UL
1022
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT		9
1023
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK		0x0000000000000200UL
1024
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT		10
1025
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK		0x0000000000000400UL
1026
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT		11
1027
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK		0x0000000000000800UL
1028
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT		12
1029
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK		0x0000000000001000UL
1030
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT		13
1031
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK		0x0000000000002000UL
1032
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT		14
1033
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK		0x0000000000004000UL
1034
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT		15
1035
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK		0x0000000000008000UL
1036
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT		16
1037
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK		0x0000000000010000UL
1038
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT		17
1039
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK		0x0000000000020000UL
1040
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT		18
1041
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK		0x0000000000040000UL
1042
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_SHFT		19
1043
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_MASK		0x0000000000080000UL
1044
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_SHFT		20
1045
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_MASK		0x0000000000100000UL
1046
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_SHFT		21
1047
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_MASK		0x0000000000200000UL
1048
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_SHFT		22
1049
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_MASK		0x0000000000400000UL
1050
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_SHFT		23
1051
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_MASK		0x0000000000800000UL
1052
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_SHFT		24
1053
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_MASK		0x0000000001000000UL
1054
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_SHFT		25
1055
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_MASK		0x0000000002000000UL
1056
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_SHFT		26
1057
+#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_MASK		0x0000000004000000UL
1058
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT		27
1059
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK		0x0000000008000000UL
1060
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT		28
1061
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK		0x0000000010000000UL
1062
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT		29
1063
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK		0x0000000020000000UL
1064
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT		30
1065
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK		0x0000000040000000UL
1066
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT		31
1067
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK		0x0000000080000000UL
1068
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT		32
1069
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK		0x0000000100000000UL
1070
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT		33
1071
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK		0x0000000200000000UL
1072
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT		34
1073
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK		0x0000000400000000UL
1074
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT		35
1075
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK		0x0000000800000000UL
1076
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT		36
1077
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK		0x0000001000000000UL
1078
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT		37
1079
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK		0x0000002000000000UL
1080
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT		38
1081
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK		0x0000004000000000UL
1082
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT		39
1083
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK		0x0000008000000000UL
1084
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT		40
1085
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK		0x0000010000000000UL
1086
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT		41
1087
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK		0x0000020000000000UL
1088
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT		42
1089
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK		0x0000040000000000UL
1090
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_SHFT		43
1091
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_MASK		0x0000080000000000UL
1092
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_SHFT		44
1093
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_MASK		0x0000100000000000UL
1094
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_SHFT		45
1095
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_MASK		0x0000200000000000UL
1096
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_SHFT		46
1097
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_MASK		0x0000400000000000UL
1098
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_SHFT		47
1099
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_MASK		0x0000800000000000UL
1100
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_SHFT		48
1101
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_MASK		0x0001000000000000UL
1102
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_SHFT		49
1103
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_MASK		0x0002000000000000UL
1104
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_SHFT		50
1105
+#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_MASK		0x0004000000000000UL
1106
+
1107
+/* UV3 unique defines */
1108
+#define UV3H_EVENT_OCCURRED1_BAU_DATA_SHFT		0
1109
+#define UV3H_EVENT_OCCURRED1_BAU_DATA_MASK		0x0000000000000001UL
1110
+#define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT	1
1111
+#define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK	0x0000000000000002UL
1112
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2
1113
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
1114
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3
1115
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
1116
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4
1117
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
1118
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5
1119
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
1120
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6
1121
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
1122
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7
1123
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
1124
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8
1125
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
1126
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9
1127
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
1128
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10
1129
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
1130
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11
1131
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
1132
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12
1133
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
1134
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13
1135
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
1136
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14
1137
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
1138
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15
1139
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
1140
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16
1141
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
1142
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17
1143
+#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
1144
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT		18
1145
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK		0x0000000000040000UL
1146
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT		19
1147
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK		0x0000000000080000UL
1148
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT		20
1149
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK		0x0000000000100000UL
1150
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT		21
1151
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK		0x0000000000200000UL
1152
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT		22
1153
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK		0x0000000000400000UL
1154
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT		23
1155
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK		0x0000000000800000UL
1156
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT		24
1157
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK		0x0000000001000000UL
1158
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT		25
1159
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK		0x0000000002000000UL
1160
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT		26
1161
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK		0x0000000004000000UL
1162
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT		27
1163
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK		0x0000000008000000UL
1164
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT		28
1165
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK		0x0000000010000000UL
1166
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT		29
1167
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK		0x0000000020000000UL
1168
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT		30
1169
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK		0x0000000040000000UL
1170
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT		31
1171
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK		0x0000000080000000UL
1172
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT		32
1173
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK		0x0000000100000000UL
1174
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT		33
1175
+#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK		0x0000000200000000UL
1176
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT		34
1177
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK		0x0000000400000000UL
1178
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT		35
1179
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK		0x0000000800000000UL
1180
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT		36
1181
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK		0x0000001000000000UL
1182
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT		37
1183
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK		0x0000002000000000UL
1184
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT		38
1185
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK		0x0000004000000000UL
1186
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT		39
1187
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK		0x0000008000000000UL
1188
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT		40
1189
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK		0x0000010000000000UL
1190
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT		41
1191
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK		0x0000020000000000UL
1192
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT		42
1193
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK		0x0000040000000000UL
1194
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT		43
1195
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK		0x0000080000000000UL
1196
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT		44
1197
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK		0x0000100000000000UL
1198
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT		45
1199
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK		0x0000200000000000UL
1200
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT		46
1201
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK		0x0000400000000000UL
1202
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT		47
1203
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK		0x0000800000000000UL
1204
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT		48
1205
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK		0x0001000000000000UL
1206
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT		49
1207
+#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK		0x0002000000000000UL
1208
+#define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT	50
1209
+#define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK	0x0004000000000000UL
1210
+#define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT	51
1211
+#define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK	0x0008000000000000UL
1212
+
1213
+/* UV2 unique defines */
1214
+#define UV2H_EVENT_OCCURRED1_BAU_DATA_SHFT		0
1215
+#define UV2H_EVENT_OCCURRED1_BAU_DATA_MASK		0x0000000000000001UL
1216
+#define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT	1
1217
+#define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK	0x0000000000000002UL
1218
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2
1219
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
1220
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3
1221
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
1222
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4
1223
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
1224
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5
1225
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
1226
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6
1227
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
1228
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7
1229
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
1230
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8
1231
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
1232
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9
1233
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
1234
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10
1235
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
1236
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11
1237
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
1238
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12
1239
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
1240
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13
1241
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
1242
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14
1243
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
1244
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15
1245
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
1246
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16
1247
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
1248
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17
1249
+#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
1250
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT		18
1251
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK		0x0000000000040000UL
1252
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT		19
1253
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK		0x0000000000080000UL
1254
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT		20
1255
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK		0x0000000000100000UL
1256
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT		21
1257
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK		0x0000000000200000UL
1258
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT		22
1259
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK		0x0000000000400000UL
1260
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT		23
1261
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK		0x0000000000800000UL
1262
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT		24
1263
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK		0x0000000001000000UL
1264
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT		25
1265
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK		0x0000000002000000UL
1266
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT		26
1267
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK		0x0000000004000000UL
1268
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT		27
1269
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK		0x0000000008000000UL
1270
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT		28
1271
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK		0x0000000010000000UL
1272
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT		29
1273
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK		0x0000000020000000UL
1274
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT		30
1275
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK		0x0000000040000000UL
1276
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT		31
1277
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK		0x0000000080000000UL
1278
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT		32
1279
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK		0x0000000100000000UL
1280
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT		33
1281
+#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK		0x0000000200000000UL
1282
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT		34
1283
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK		0x0000000400000000UL
1284
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT		35
1285
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK		0x0000000800000000UL
1286
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT		36
1287
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK		0x0000001000000000UL
1288
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT		37
1289
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK		0x0000002000000000UL
1290
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT		38
1291
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK		0x0000004000000000UL
1292
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT		39
1293
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK		0x0000008000000000UL
1294
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT		40
1295
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK		0x0000010000000000UL
1296
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT		41
1297
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK		0x0000020000000000UL
1298
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT		42
1299
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK		0x0000040000000000UL
1300
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT		43
1301
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK		0x0000080000000000UL
1302
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT		44
1303
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK		0x0000100000000000UL
1304
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT		45
1305
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK		0x0000200000000000UL
1306
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT		46
1307
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK		0x0000400000000000UL
1308
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT		47
1309
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK		0x0000800000000000UL
1310
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT		48
1311
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK		0x0001000000000000UL
1312
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT		49
1313
+#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK		0x0002000000000000UL
1314
+#define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT	50
1315
+#define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK	0x0004000000000000UL
1316
+#define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT	51
1317
+#define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK	0x0008000000000000UL
1318
+
1319
+#define UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK (				\
1320
+	is_uv(UV5) ? 0x0000000000000002UL :				\
1321
+	0)
1322
+#define UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT (				\
1323
+	is_uv(UV5) ? 1 :						\
1324
+	-1)
1325
+
1326
+union uvyh_event_occurred1_u {
7431327 	unsigned long	v;
744
-	struct uvh_extio_int0_broadcast_s {
745
-		unsigned long	enable:1;			/* RW */
746
-		unsigned long	rsvd_1_63:63;
747
-	} s;
748
-};
7491328 
750
-/* ========================================================================= */
751
-/*                         UVH_GR0_TLB_INT0_CONFIG                           */
752
-/* ========================================================================= */
753
-#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
1329
+	/* UVYH common struct */
1330
+	struct uvyh_event_occurred1_s {
1331
+		unsigned long	ipi_int:1;			/* RW */
1332
+		unsigned long	extio_int0:1;			/* RW */
1333
+		unsigned long	extio_int1:1;			/* RW */
1334
+		unsigned long	extio_int2:1;			/* RW */
1335
+		unsigned long	extio_int3:1;			/* RW */
1336
+		unsigned long	profile_int:1;			/* RW */
1337
+		unsigned long	bau_data:1;			/* RW */
1338
+		unsigned long	proc_general:1;			/* RW */
1339
+		unsigned long	xh_tlb_int0:1;			/* RW */
1340
+		unsigned long	xh_tlb_int1:1;			/* RW */
1341
+		unsigned long	xh_tlb_int2:1;			/* RW */
1342
+		unsigned long	xh_tlb_int3:1;			/* RW */
1343
+		unsigned long	xh_tlb_int4:1;			/* RW */
1344
+		unsigned long	xh_tlb_int5:1;			/* RW */
1345
+		unsigned long	rdm_tlb_int0:1;			/* RW */
1346
+		unsigned long	rdm_tlb_int1:1;			/* RW */
1347
+		unsigned long	rdm_tlb_int2:1;			/* RW */
1348
+		unsigned long	rdm_tlb_int3:1;			/* RW */
1349
+		unsigned long	rdm_tlb_int4:1;			/* RW */
1350
+		unsigned long	rdm_tlb_int5:1;			/* RW */
1351
+		unsigned long	rdm_tlb_int6:1;			/* RW */
1352
+		unsigned long	rdm_tlb_int7:1;			/* RW */
1353
+		unsigned long	rdm_tlb_int8:1;			/* RW */
1354
+		unsigned long	rdm_tlb_int9:1;			/* RW */
1355
+		unsigned long	rdm_tlb_int10:1;		/* RW */
1356
+		unsigned long	rdm_tlb_int11:1;		/* RW */
1357
+		unsigned long	rdm_tlb_int12:1;		/* RW */
1358
+		unsigned long	rdm_tlb_int13:1;		/* RW */
1359
+		unsigned long	rdm_tlb_int14:1;		/* RW */
1360
+		unsigned long	rdm_tlb_int15:1;		/* RW */
1361
+		unsigned long	rdm_tlb_int16:1;		/* RW */
1362
+		unsigned long	rdm_tlb_int17:1;		/* RW */
1363
+		unsigned long	rdm_tlb_int18:1;		/* RW */
1364
+		unsigned long	rdm_tlb_int19:1;		/* RW */
1365
+		unsigned long	rdm_tlb_int20:1;		/* RW */
1366
+		unsigned long	rdm_tlb_int21:1;		/* RW */
1367
+		unsigned long	rdm_tlb_int22:1;		/* RW */
1368
+		unsigned long	rdm_tlb_int23:1;		/* RW */
1369
+		unsigned long	rsvd_38_63:26;
1370
+	} sy;
7541371 
755
-#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT		0
756
-#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT			8
757
-#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT		11
758
-#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT		12
759
-#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT			13
760
-#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT			15
761
-#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT			16
762
-#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT		32
763
-#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
764
-#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
765
-#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
766
-#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
767
-#define UVH_GR0_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
768
-#define UVH_GR0_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
769
-#define UVH_GR0_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
770
-#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
1372
+	/* UV5 unique struct */
1373
+	struct uv5h_event_occurred1_s {
1374
+		unsigned long	ipi_int:1;			/* RW */
1375
+		unsigned long	extio_int0:1;			/* RW */
1376
+		unsigned long	extio_int1:1;			/* RW */
1377
+		unsigned long	extio_int2:1;			/* RW */
1378
+		unsigned long	extio_int3:1;			/* RW */
1379
+		unsigned long	profile_int:1;			/* RW */
1380
+		unsigned long	bau_data:1;			/* RW */
1381
+		unsigned long	proc_general:1;			/* RW */
1382
+		unsigned long	xh_tlb_int0:1;			/* RW */
1383
+		unsigned long	xh_tlb_int1:1;			/* RW */
1384
+		unsigned long	xh_tlb_int2:1;			/* RW */
1385
+		unsigned long	xh_tlb_int3:1;			/* RW */
1386
+		unsigned long	xh_tlb_int4:1;			/* RW */
1387
+		unsigned long	xh_tlb_int5:1;			/* RW */
1388
+		unsigned long	rdm_tlb_int0:1;			/* RW */
1389
+		unsigned long	rdm_tlb_int1:1;			/* RW */
1390
+		unsigned long	rdm_tlb_int2:1;			/* RW */
1391
+		unsigned long	rdm_tlb_int3:1;			/* RW */
1392
+		unsigned long	rdm_tlb_int4:1;			/* RW */
1393
+		unsigned long	rdm_tlb_int5:1;			/* RW */
1394
+		unsigned long	rdm_tlb_int6:1;			/* RW */
1395
+		unsigned long	rdm_tlb_int7:1;			/* RW */
1396
+		unsigned long	rdm_tlb_int8:1;			/* RW */
1397
+		unsigned long	rdm_tlb_int9:1;			/* RW */
1398
+		unsigned long	rdm_tlb_int10:1;		/* RW */
1399
+		unsigned long	rdm_tlb_int11:1;		/* RW */
1400
+		unsigned long	rdm_tlb_int12:1;		/* RW */
1401
+		unsigned long	rdm_tlb_int13:1;		/* RW */
1402
+		unsigned long	rdm_tlb_int14:1;		/* RW */
1403
+		unsigned long	rdm_tlb_int15:1;		/* RW */
1404
+		unsigned long	rdm_tlb_int16:1;		/* RW */
1405
+		unsigned long	rdm_tlb_int17:1;		/* RW */
1406
+		unsigned long	rdm_tlb_int18:1;		/* RW */
1407
+		unsigned long	rdm_tlb_int19:1;		/* RW */
1408
+		unsigned long	rdm_tlb_int20:1;		/* RW */
1409
+		unsigned long	rdm_tlb_int21:1;		/* RW */
1410
+		unsigned long	rdm_tlb_int22:1;		/* RW */
1411
+		unsigned long	rdm_tlb_int23:1;		/* RW */
1412
+		unsigned long	rsvd_38_63:26;
1413
+	} s5;
7711414 
1415
+	/* UV4 unique struct */
1416
+	struct uv4h_event_occurred1_s {
1417
+		unsigned long	profile_int:1;			/* RW */
1418
+		unsigned long	bau_data:1;			/* RW */
1419
+		unsigned long	proc_general:1;			/* RW */
1420
+		unsigned long	gr0_tlb_int0:1;			/* RW */
1421
+		unsigned long	gr0_tlb_int1:1;			/* RW */
1422
+		unsigned long	gr0_tlb_int2:1;			/* RW */
1423
+		unsigned long	gr0_tlb_int3:1;			/* RW */
1424
+		unsigned long	gr0_tlb_int4:1;			/* RW */
1425
+		unsigned long	gr0_tlb_int5:1;			/* RW */
1426
+		unsigned long	gr0_tlb_int6:1;			/* RW */
1427
+		unsigned long	gr0_tlb_int7:1;			/* RW */
1428
+		unsigned long	gr0_tlb_int8:1;			/* RW */
1429
+		unsigned long	gr0_tlb_int9:1;			/* RW */
1430
+		unsigned long	gr0_tlb_int10:1;		/* RW */
1431
+		unsigned long	gr0_tlb_int11:1;		/* RW */
1432
+		unsigned long	gr0_tlb_int12:1;		/* RW */
1433
+		unsigned long	gr0_tlb_int13:1;		/* RW */
1434
+		unsigned long	gr0_tlb_int14:1;		/* RW */
1435
+		unsigned long	gr0_tlb_int15:1;		/* RW */
1436
+		unsigned long	gr0_tlb_int16:1;		/* RW */
1437
+		unsigned long	gr0_tlb_int17:1;		/* RW */
1438
+		unsigned long	gr0_tlb_int18:1;		/* RW */
1439
+		unsigned long	gr0_tlb_int19:1;		/* RW */
1440
+		unsigned long	gr0_tlb_int20:1;		/* RW */
1441
+		unsigned long	gr0_tlb_int21:1;		/* RW */
1442
+		unsigned long	gr0_tlb_int22:1;		/* RW */
1443
+		unsigned long	gr0_tlb_int23:1;		/* RW */
1444
+		unsigned long	gr1_tlb_int0:1;			/* RW */
1445
+		unsigned long	gr1_tlb_int1:1;			/* RW */
1446
+		unsigned long	gr1_tlb_int2:1;			/* RW */
1447
+		unsigned long	gr1_tlb_int3:1;			/* RW */
1448
+		unsigned long	gr1_tlb_int4:1;			/* RW */
1449
+		unsigned long	gr1_tlb_int5:1;			/* RW */
1450
+		unsigned long	gr1_tlb_int6:1;			/* RW */
1451
+		unsigned long	gr1_tlb_int7:1;			/* RW */
1452
+		unsigned long	gr1_tlb_int8:1;			/* RW */
1453
+		unsigned long	gr1_tlb_int9:1;			/* RW */
1454
+		unsigned long	gr1_tlb_int10:1;		/* RW */
1455
+		unsigned long	gr1_tlb_int11:1;		/* RW */
1456
+		unsigned long	gr1_tlb_int12:1;		/* RW */
1457
+		unsigned long	gr1_tlb_int13:1;		/* RW */
1458
+		unsigned long	gr1_tlb_int14:1;		/* RW */
1459
+		unsigned long	gr1_tlb_int15:1;		/* RW */
1460
+		unsigned long	gr1_tlb_int16:1;		/* RW */
1461
+		unsigned long	gr1_tlb_int17:1;		/* RW */
1462
+		unsigned long	gr1_tlb_int18:1;		/* RW */
1463
+		unsigned long	gr1_tlb_int19:1;		/* RW */
1464
+		unsigned long	gr1_tlb_int20:1;		/* RW */
1465
+		unsigned long	gr1_tlb_int21:1;		/* RW */
1466
+		unsigned long	gr1_tlb_int22:1;		/* RW */
1467
+		unsigned long	gr1_tlb_int23:1;		/* RW */
1468
+		unsigned long	rsvd_51_63:13;
1469
+	} s4;
7721470 
773
-union uvh_gr0_tlb_int0_config_u {
774
-	unsigned long	v;
775
-	struct uvh_gr0_tlb_int0_config_s {
776
-		unsigned long	vector_:8;			/* RW */
777
-		unsigned long	dm:3;				/* RW */
778
-		unsigned long	destmode:1;			/* RW */
779
-		unsigned long	status:1;			/* RO */
780
-		unsigned long	p:1;				/* RO */
781
-		unsigned long	rsvd_14:1;
782
-		unsigned long	t:1;				/* RO */
783
-		unsigned long	m:1;				/* RW */
784
-		unsigned long	rsvd_17_31:15;
785
-		unsigned long	apic_id:32;			/* RW */
786
-	} s;
787
-};
788
-
789
-/* ========================================================================= */
790
-/*                         UVH_GR0_TLB_INT1_CONFIG                           */
791
-/* ========================================================================= */
792
-#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
793
-
794
-#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT		0
795
-#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT			8
796
-#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT		11
797
-#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT		12
798
-#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT			13
799
-#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT			15
800
-#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT			16
801
-#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT		32
802
-#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
803
-#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
804
-#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
805
-#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
806
-#define UVH_GR0_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
807
-#define UVH_GR0_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
808
-#define UVH_GR0_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
809
-#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
810
-
811
-
812
-union uvh_gr0_tlb_int1_config_u {
813
-	unsigned long	v;
814
-	struct uvh_gr0_tlb_int1_config_s {
815
-		unsigned long	vector_:8;			/* RW */
816
-		unsigned long	dm:3;				/* RW */
817
-		unsigned long	destmode:1;			/* RW */
818
-		unsigned long	status:1;			/* RO */
819
-		unsigned long	p:1;				/* RO */
820
-		unsigned long	rsvd_14:1;
821
-		unsigned long	t:1;				/* RO */
822
-		unsigned long	m:1;				/* RW */
823
-		unsigned long	rsvd_17_31:15;
824
-		unsigned long	apic_id:32;			/* RW */
825
-	} s;
826
-};
827
-
828
-/* ========================================================================= */
829
-/*                         UVH_GR0_TLB_MMR_CONTROL                           */
830
-/* ========================================================================= */
831
-#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
832
-#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
833
-#define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
834
-#define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL
835
-#define UVH_GR0_TLB_MMR_CONTROL (					\
836
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :			\
837
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :			\
838
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL :			\
839
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL)
840
-
841
-#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
842
-#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
843
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
844
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
845
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
846
-#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
847
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
848
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
849
-#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
850
-
851
-#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
852
-#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
853
-#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
854
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
855
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
856
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
857
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
858
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
859
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
860
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
861
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
862
-#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
863
-#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
864
-#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
865
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
866
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
867
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
868
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
869
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
870
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
871
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
872
-#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL
873
-
874
-#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
875
-#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
876
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
877
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
878
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
879
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
880
-#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
881
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
882
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
883
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
884
-#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
885
-
886
-#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
887
-#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
888
-#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
889
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
890
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
891
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
892
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
893
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
894
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
895
-#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
896
-#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
897
-#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
898
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
899
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
900
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
901
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
902
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
903
-#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
904
-
905
-#define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
906
-#define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
907
-#define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
908
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
909
-#define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
910
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
911
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
912
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
913
-#define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
914
-#define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
915
-#define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
916
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
917
-#define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
918
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
919
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
920
-#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
921
-
922
-#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
923
-#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		13
924
-#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
925
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
926
-#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
927
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
928
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
929
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
930
-#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT		59
931
-#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000001fffUL
932
-#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000006000UL
933
-#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
934
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
935
-#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
936
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
937
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
938
-#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
939
-#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK		0xf800000000000000UL
940
-
941
-#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK (				\
942
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
943
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
944
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
945
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK)
946
-#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK (				\
947
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
948
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
949
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
950
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK)
951
-#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT (				\
952
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
953
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
954
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
955
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT)
956
-
957
-union uvh_gr0_tlb_mmr_control_u {
958
-	unsigned long	v;
959
-	struct uvh_gr0_tlb_mmr_control_s {
960
-		unsigned long	rsvd_0_15:16;
961
-		unsigned long	auto_valid_en:1;		/* RW */
962
-		unsigned long	rsvd_17_19:3;
963
-		unsigned long	mmr_hash_index_en:1;		/* RW */
964
-		unsigned long	rsvd_21_29:9;
965
-		unsigned long	mmr_write:1;			/* WP */
966
-		unsigned long	mmr_read:1;			/* WP */
967
-		unsigned long	rsvd_32_48:17;
968
-		unsigned long	rsvd_49_51:3;
1471
+	/* UV3 unique struct */
1472
+	struct uv3h_event_occurred1_s {
1473
+		unsigned long	bau_data:1;			/* RW */
1474
+		unsigned long	power_management_req:1;		/* RW */
1475
+		unsigned long	message_accelerator_int0:1;	/* RW */
1476
+		unsigned long	message_accelerator_int1:1;	/* RW */
1477
+		unsigned long	message_accelerator_int2:1;	/* RW */
1478
+		unsigned long	message_accelerator_int3:1;	/* RW */
1479
+		unsigned long	message_accelerator_int4:1;	/* RW */
1480
+		unsigned long	message_accelerator_int5:1;	/* RW */
1481
+		unsigned long	message_accelerator_int6:1;	/* RW */
1482
+		unsigned long	message_accelerator_int7:1;	/* RW */
1483
+		unsigned long	message_accelerator_int8:1;	/* RW */
1484
+		unsigned long	message_accelerator_int9:1;	/* RW */
1485
+		unsigned long	message_accelerator_int10:1;	/* RW */
1486
+		unsigned long	message_accelerator_int11:1;	/* RW */
1487
+		unsigned long	message_accelerator_int12:1;	/* RW */
1488
+		unsigned long	message_accelerator_int13:1;	/* RW */
1489
+		unsigned long	message_accelerator_int14:1;	/* RW */
1490
+		unsigned long	message_accelerator_int15:1;	/* RW */
1491
+		unsigned long	gr0_tlb_int0:1;			/* RW */
1492
+		unsigned long	gr0_tlb_int1:1;			/* RW */
1493
+		unsigned long	gr0_tlb_int2:1;			/* RW */
1494
+		unsigned long	gr0_tlb_int3:1;			/* RW */
1495
+		unsigned long	gr0_tlb_int4:1;			/* RW */
1496
+		unsigned long	gr0_tlb_int5:1;			/* RW */
1497
+		unsigned long	gr0_tlb_int6:1;			/* RW */
1498
+		unsigned long	gr0_tlb_int7:1;			/* RW */
1499
+		unsigned long	gr0_tlb_int8:1;			/* RW */
1500
+		unsigned long	gr0_tlb_int9:1;			/* RW */
1501
+		unsigned long	gr0_tlb_int10:1;		/* RW */
1502
+		unsigned long	gr0_tlb_int11:1;		/* RW */
1503
+		unsigned long	gr0_tlb_int12:1;		/* RW */
1504
+		unsigned long	gr0_tlb_int13:1;		/* RW */
1505
+		unsigned long	gr0_tlb_int14:1;		/* RW */
1506
+		unsigned long	gr0_tlb_int15:1;		/* RW */
1507
+		unsigned long	gr1_tlb_int0:1;			/* RW */
1508
+		unsigned long	gr1_tlb_int1:1;			/* RW */
1509
+		unsigned long	gr1_tlb_int2:1;			/* RW */
1510
+		unsigned long	gr1_tlb_int3:1;			/* RW */
1511
+		unsigned long	gr1_tlb_int4:1;			/* RW */
1512
+		unsigned long	gr1_tlb_int5:1;			/* RW */
1513
+		unsigned long	gr1_tlb_int6:1;			/* RW */
1514
+		unsigned long	gr1_tlb_int7:1;			/* RW */
1515
+		unsigned long	gr1_tlb_int8:1;			/* RW */
1516
+		unsigned long	gr1_tlb_int9:1;			/* RW */
1517
+		unsigned long	gr1_tlb_int10:1;		/* RW */
1518
+		unsigned long	gr1_tlb_int11:1;		/* RW */
1519
+		unsigned long	gr1_tlb_int12:1;		/* RW */
1520
+		unsigned long	gr1_tlb_int13:1;		/* RW */
1521
+		unsigned long	gr1_tlb_int14:1;		/* RW */
1522
+		unsigned long	gr1_tlb_int15:1;		/* RW */
1523
+		unsigned long	rtc_interval_int:1;		/* RW */
1524
+		unsigned long	bau_dashboard_int:1;		/* RW */
9691525 		unsigned long	rsvd_52_63:12;
970
-	} s;
971
-	struct uv1h_gr0_tlb_mmr_control_s {
972
-		unsigned long	index:12;			/* RW */
973
-		unsigned long	mem_sel:2;			/* RW */
974
-		unsigned long	rsvd_14_15:2;
975
-		unsigned long	auto_valid_en:1;		/* RW */
976
-		unsigned long	rsvd_17_19:3;
977
-		unsigned long	mmr_hash_index_en:1;		/* RW */
978
-		unsigned long	rsvd_21_29:9;
979
-		unsigned long	mmr_write:1;			/* WP */
980
-		unsigned long	mmr_read:1;			/* WP */
981
-		unsigned long	rsvd_32_47:16;
982
-		unsigned long	mmr_inj_con:1;			/* RW */
983
-		unsigned long	rsvd_49_51:3;
984
-		unsigned long	mmr_inj_tlbram:1;		/* RW */
985
-		unsigned long	rsvd_53:1;
986
-		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
987
-		unsigned long	rsvd_55:1;
988
-		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
989
-		unsigned long	rsvd_57_59:3;
990
-		unsigned long	mmr_inj_tlblruv:1;		/* RW */
991
-		unsigned long	rsvd_61_63:3;
992
-	} s1;
993
-	struct uvxh_gr0_tlb_mmr_control_s {
994
-		unsigned long	rsvd_0_15:16;
995
-		unsigned long	auto_valid_en:1;		/* RW */
996
-		unsigned long	rsvd_17_19:3;
997
-		unsigned long	mmr_hash_index_en:1;		/* RW */
998
-		unsigned long	rsvd_21_29:9;
999
-		unsigned long	mmr_write:1;			/* WP */
1000
-		unsigned long	mmr_read:1;			/* WP */
1001
-		unsigned long	mmr_op_done:1;			/* RW */
1002
-		unsigned long	rsvd_33_47:15;
1003
-		unsigned long	rsvd_48:1;
1004
-		unsigned long	rsvd_49_51:3;
1526
+	} s3;
1527
+
1528
+	/* UV2 unique struct */
1529
+	struct uv2h_event_occurred1_s {
1530
+		unsigned long	bau_data:1;			/* RW */
1531
+		unsigned long	power_management_req:1;		/* RW */
1532
+		unsigned long	message_accelerator_int0:1;	/* RW */
1533
+		unsigned long	message_accelerator_int1:1;	/* RW */
1534
+		unsigned long	message_accelerator_int2:1;	/* RW */
1535
+		unsigned long	message_accelerator_int3:1;	/* RW */
1536
+		unsigned long	message_accelerator_int4:1;	/* RW */
1537
+		unsigned long	message_accelerator_int5:1;	/* RW */
1538
+		unsigned long	message_accelerator_int6:1;	/* RW */
1539
+		unsigned long	message_accelerator_int7:1;	/* RW */
1540
+		unsigned long	message_accelerator_int8:1;	/* RW */
1541
+		unsigned long	message_accelerator_int9:1;	/* RW */
1542
+		unsigned long	message_accelerator_int10:1;	/* RW */
1543
+		unsigned long	message_accelerator_int11:1;	/* RW */
1544
+		unsigned long	message_accelerator_int12:1;	/* RW */
1545
+		unsigned long	message_accelerator_int13:1;	/* RW */
1546
+		unsigned long	message_accelerator_int14:1;	/* RW */
1547
+		unsigned long	message_accelerator_int15:1;	/* RW */
1548
+		unsigned long	gr0_tlb_int0:1;			/* RW */
1549
+		unsigned long	gr0_tlb_int1:1;			/* RW */
1550
+		unsigned long	gr0_tlb_int2:1;			/* RW */
1551
+		unsigned long	gr0_tlb_int3:1;			/* RW */
1552
+		unsigned long	gr0_tlb_int4:1;			/* RW */
1553
+		unsigned long	gr0_tlb_int5:1;			/* RW */
1554
+		unsigned long	gr0_tlb_int6:1;			/* RW */
1555
+		unsigned long	gr0_tlb_int7:1;			/* RW */
1556
+		unsigned long	gr0_tlb_int8:1;			/* RW */
1557
+		unsigned long	gr0_tlb_int9:1;			/* RW */
1558
+		unsigned long	gr0_tlb_int10:1;		/* RW */
1559
+		unsigned long	gr0_tlb_int11:1;		/* RW */
1560
+		unsigned long	gr0_tlb_int12:1;		/* RW */
1561
+		unsigned long	gr0_tlb_int13:1;		/* RW */
1562
+		unsigned long	gr0_tlb_int14:1;		/* RW */
1563
+		unsigned long	gr0_tlb_int15:1;		/* RW */
1564
+		unsigned long	gr1_tlb_int0:1;			/* RW */
1565
+		unsigned long	gr1_tlb_int1:1;			/* RW */
1566
+		unsigned long	gr1_tlb_int2:1;			/* RW */
1567
+		unsigned long	gr1_tlb_int3:1;			/* RW */
1568
+		unsigned long	gr1_tlb_int4:1;			/* RW */
1569
+		unsigned long	gr1_tlb_int5:1;			/* RW */
1570
+		unsigned long	gr1_tlb_int6:1;			/* RW */
1571
+		unsigned long	gr1_tlb_int7:1;			/* RW */
1572
+		unsigned long	gr1_tlb_int8:1;			/* RW */
1573
+		unsigned long	gr1_tlb_int9:1;			/* RW */
1574
+		unsigned long	gr1_tlb_int10:1;		/* RW */
1575
+		unsigned long	gr1_tlb_int11:1;		/* RW */
1576
+		unsigned long	gr1_tlb_int12:1;		/* RW */
1577
+		unsigned long	gr1_tlb_int13:1;		/* RW */
1578
+		unsigned long	gr1_tlb_int14:1;		/* RW */
1579
+		unsigned long	gr1_tlb_int15:1;		/* RW */
1580
+		unsigned long	rtc_interval_int:1;		/* RW */
1581
+		unsigned long	bau_dashboard_int:1;		/* RW */
10051582 		unsigned long	rsvd_52_63:12;
1006
-	} sx;
1007
-	struct uv2h_gr0_tlb_mmr_control_s {
1008
-		unsigned long	index:12;			/* RW */
1009
-		unsigned long	mem_sel:2;			/* RW */
1010
-		unsigned long	rsvd_14_15:2;
1011
-		unsigned long	auto_valid_en:1;		/* RW */
1012
-		unsigned long	rsvd_17_19:3;
1013
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1014
-		unsigned long	rsvd_21_29:9;
1015
-		unsigned long	mmr_write:1;			/* WP */
1016
-		unsigned long	mmr_read:1;			/* WP */
1017
-		unsigned long	mmr_op_done:1;			/* RW */
1018
-		unsigned long	rsvd_33_47:15;
1019
-		unsigned long	mmr_inj_con:1;			/* RW */
1020
-		unsigned long	rsvd_49_51:3;
1021
-		unsigned long	mmr_inj_tlbram:1;		/* RW */
1022
-		unsigned long	rsvd_53_63:11;
1023
-	} s2;
1024
-	struct uv3h_gr0_tlb_mmr_control_s {
1025
-		unsigned long	index:12;			/* RW */
1026
-		unsigned long	mem_sel:2;			/* RW */
1027
-		unsigned long	rsvd_14_15:2;
1028
-		unsigned long	auto_valid_en:1;		/* RW */
1029
-		unsigned long	rsvd_17_19:3;
1030
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1031
-		unsigned long	ecc_sel:1;			/* RW */
1032
-		unsigned long	rsvd_22_29:8;
1033
-		unsigned long	mmr_write:1;			/* WP */
1034
-		unsigned long	mmr_read:1;			/* WP */
1035
-		unsigned long	mmr_op_done:1;			/* RW */
1036
-		unsigned long	rsvd_33_47:15;
1037
-		unsigned long	undef_48:1;			/* Undefined */
1038
-		unsigned long	rsvd_49_51:3;
1039
-		unsigned long	undef_52:1;			/* Undefined */
1040
-		unsigned long	rsvd_53_63:11;
1041
-	} s3;
1042
-	struct uv4h_gr0_tlb_mmr_control_s {
1043
-		unsigned long	index:13;			/* RW */
1044
-		unsigned long	mem_sel:2;			/* RW */
1045
-		unsigned long	rsvd_15:1;
1046
-		unsigned long	auto_valid_en:1;		/* RW */
1047
-		unsigned long	rsvd_17_19:3;
1048
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1049
-		unsigned long	ecc_sel:1;			/* RW */
1050
-		unsigned long	rsvd_22_29:8;
1051
-		unsigned long	mmr_write:1;			/* WP */
1052
-		unsigned long	mmr_read:1;			/* WP */
1053
-		unsigned long	mmr_op_done:1;			/* RW */
1054
-		unsigned long	rsvd_33_47:15;
1055
-		unsigned long	undef_48:1;			/* Undefined */
1056
-		unsigned long	rsvd_49_51:3;
1057
-		unsigned long	rsvd_52_58:7;
1058
-		unsigned long	page_size:5;			/* RW */
1059
-	} s4;
1060
-};
1061
-
1062
-/* ========================================================================= */
1063
-/*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
1064
-/* ========================================================================= */
1065
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
1066
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1067
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1068
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL
1069
-#define UVH_GR0_TLB_MMR_READ_DATA_HI (					\
1070
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :			\
1071
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :			\
1072
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI :			\
1073
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI)
1074
-
1075
-#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1076
-
1077
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1078
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1079
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1080
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1081
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1082
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1083
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1084
-#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1085
-
1086
-#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1087
-
1088
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1089
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1090
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1091
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1092
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1093
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1094
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1095
-#define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1096
-
1097
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1098
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1099
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1100
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1101
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
1102
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1103
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1104
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1105
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1106
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1107
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
1108
-#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1109
-
1110
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1111
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT		34
1112
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		49
1113
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	51
1114
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	52
1115
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	53
1116
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1117
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x00000003ffffffffUL
1118
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK		0x0001fffc00000000UL
1119
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0006000000000000UL
1120
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0008000000000000UL
1121
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0010000000000000UL
1122
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0020000000000000UL
1123
-#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1124
-
1125
-
1126
-union uvh_gr0_tlb_mmr_read_data_hi_u {
1127
-	unsigned long	v;
1128
-	struct uv1h_gr0_tlb_mmr_read_data_hi_s {
1129
-		unsigned long	pfn:41;				/* RO */
1130
-		unsigned long	gaa:2;				/* RO */
1131
-		unsigned long	dirty:1;			/* RO */
1132
-		unsigned long	larger:1;			/* RO */
1133
-		unsigned long	rsvd_45_63:19;
1134
-	} s1;
1135
-	struct uv2h_gr0_tlb_mmr_read_data_hi_s {
1136
-		unsigned long	pfn:41;				/* RO */
1137
-		unsigned long	gaa:2;				/* RO */
1138
-		unsigned long	dirty:1;			/* RO */
1139
-		unsigned long	larger:1;			/* RO */
1140
-		unsigned long	rsvd_45_63:19;
1141
-	} s2;
1142
-	struct uv3h_gr0_tlb_mmr_read_data_hi_s {
1143
-		unsigned long	pfn:41;				/* RO */
1144
-		unsigned long	gaa:2;				/* RO */
1145
-		unsigned long	dirty:1;			/* RO */
1146
-		unsigned long	larger:1;			/* RO */
1147
-		unsigned long	aa_ext:1;			/* RO */
1148
-		unsigned long	undef_46_54:9;			/* Undefined */
1149
-		unsigned long	way_ecc:9;			/* RO */
1150
-	} s3;
1151
-	struct uv4h_gr0_tlb_mmr_read_data_hi_s {
1152
-		unsigned long	pfn:34;				/* RO */
1153
-		unsigned long	pnid:15;			/* RO */
1154
-		unsigned long	gaa:2;				/* RO */
1155
-		unsigned long	dirty:1;			/* RO */
1156
-		unsigned long	larger:1;			/* RO */
1157
-		unsigned long	aa_ext:1;			/* RO */
1158
-		unsigned long	undef_54:1;			/* Undefined */
1159
-		unsigned long	way_ecc:9;			/* RO */
1160
-	} s4;
1161
-};
1162
-
1163
-/* ========================================================================= */
1164
-/*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
1165
-/* ========================================================================= */
1166
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
1167
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1168
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1169
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL
1170
-#define UVH_GR0_TLB_MMR_READ_DATA_LO (					\
1171
-	is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :			\
1172
-	is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :			\
1173
-	is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO :			\
1174
-	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO)
1175
-
1176
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1177
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1178
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
1179
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1180
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1181
-#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL
1182
-
1183
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1184
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1185
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1186
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1187
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1188
-#define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1189
-
1190
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1191
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1192
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1193
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1194
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1195
-#define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1196
-
1197
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1198
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1199
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1200
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1201
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1202
-#define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1203
-
1204
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1205
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1206
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1207
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1208
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1209
-#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1210
-
1211
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1212
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1213
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1214
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1215
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1216
-#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1217
-
1218
-
1219
-union uvh_gr0_tlb_mmr_read_data_lo_u {
1220
-	unsigned long	v;
1221
-	struct uvh_gr0_tlb_mmr_read_data_lo_s {
1222
-		unsigned long	vpn:39;				/* RO */
1223
-		unsigned long	asid:24;			/* RO */
1224
-		unsigned long	valid:1;			/* RO */
1225
-	} s;
1226
-	struct uv1h_gr0_tlb_mmr_read_data_lo_s {
1227
-		unsigned long	vpn:39;				/* RO */
1228
-		unsigned long	asid:24;			/* RO */
1229
-		unsigned long	valid:1;			/* RO */
1230
-	} s1;
1231
-	struct uvxh_gr0_tlb_mmr_read_data_lo_s {
1232
-		unsigned long	vpn:39;				/* RO */
1233
-		unsigned long	asid:24;			/* RO */
1234
-		unsigned long	valid:1;			/* RO */
1235
-	} sx;
1236
-	struct uv2h_gr0_tlb_mmr_read_data_lo_s {
1237
-		unsigned long	vpn:39;				/* RO */
1238
-		unsigned long	asid:24;			/* RO */
1239
-		unsigned long	valid:1;			/* RO */
1240
-	} s2;
1241
-	struct uv3h_gr0_tlb_mmr_read_data_lo_s {
1242
-		unsigned long	vpn:39;				/* RO */
1243
-		unsigned long	asid:24;			/* RO */
1244
-		unsigned long	valid:1;			/* RO */
1245
-	} s3;
1246
-	struct uv4h_gr0_tlb_mmr_read_data_lo_s {
1247
-		unsigned long	vpn:39;				/* RO */
1248
-		unsigned long	asid:24;			/* RO */
1249
-		unsigned long	valid:1;			/* RO */
1250
-	} s4;
1251
-};
1252
-
1253
-/* ========================================================================= */
1254
-/*                         UVH_GR1_TLB_INT0_CONFIG                           */
1255
-/* ========================================================================= */
1256
-#define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1257
-#define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1258
-#define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1259
-#define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL
1260
-#define UVH_GR1_TLB_INT0_CONFIG (					\
1261
-	is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG :			\
1262
-	is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG :			\
1263
-	is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG :			\
1264
-	/*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG)
1265
-
1266
-#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT		0
1267
-#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT			8
1268
-#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT		11
1269
-#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT		12
1270
-#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT			13
1271
-#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT			15
1272
-#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT			16
1273
-#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT		32
1274
-#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
1275
-#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
1276
-#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
1277
-#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
1278
-#define UVH_GR1_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
1279
-#define UVH_GR1_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
1280
-#define UVH_GR1_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
1281
-#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
1282
-
1283
-
1284
-union uvh_gr1_tlb_int0_config_u {
1285
-	unsigned long	v;
1286
-	struct uvh_gr1_tlb_int0_config_s {
1287
-		unsigned long	vector_:8;			/* RW */
1288
-		unsigned long	dm:3;				/* RW */
1289
-		unsigned long	destmode:1;			/* RW */
1290
-		unsigned long	status:1;			/* RO */
1291
-		unsigned long	p:1;				/* RO */
1292
-		unsigned long	rsvd_14:1;
1293
-		unsigned long	t:1;				/* RO */
1294
-		unsigned long	m:1;				/* RW */
1295
-		unsigned long	rsvd_17_31:15;
1296
-		unsigned long	apic_id:32;			/* RW */
1297
-	} s;
1298
-};
1299
-
1300
-/* ========================================================================= */
1301
-/*                         UVH_GR1_TLB_INT1_CONFIG                           */
1302
-/* ========================================================================= */
1303
-#define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1304
-#define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1305
-#define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1306
-#define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL
1307
-#define UVH_GR1_TLB_INT1_CONFIG (					\
1308
-	is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG :			\
1309
-	is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG :			\
1310
-	is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG :			\
1311
-	/*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG)
1312
-
1313
-#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT		0
1314
-#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT			8
1315
-#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT		11
1316
-#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT		12
1317
-#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT			13
1318
-#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT			15
1319
-#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT			16
1320
-#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT		32
1321
-#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
1322
-#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
1323
-#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
1324
-#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
1325
-#define UVH_GR1_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
1326
-#define UVH_GR1_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
1327
-#define UVH_GR1_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
1328
-#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
1329
-
1330
-
1331
-union uvh_gr1_tlb_int1_config_u {
1332
-	unsigned long	v;
1333
-	struct uvh_gr1_tlb_int1_config_s {
1334
-		unsigned long	vector_:8;			/* RW */
1335
-		unsigned long	dm:3;				/* RW */
1336
-		unsigned long	destmode:1;			/* RW */
1337
-		unsigned long	status:1;			/* RO */
1338
-		unsigned long	p:1;				/* RO */
1339
-		unsigned long	rsvd_14:1;
1340
-		unsigned long	t:1;				/* RO */
1341
-		unsigned long	m:1;				/* RW */
1342
-		unsigned long	rsvd_17_31:15;
1343
-		unsigned long	apic_id:32;			/* RW */
1344
-	} s;
1345
-};
1346
-
1347
-/* ========================================================================= */
1348
-/*                         UVH_GR1_TLB_MMR_CONTROL                           */
1349
-/* ========================================================================= */
1350
-#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
1351
-#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
1352
-#define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
1353
-#define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL
1354
-#define UVH_GR1_TLB_MMR_CONTROL (					\
1355
-	is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :			\
1356
-	is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :			\
1357
-	is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL :			\
1358
-	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL)
1359
-
1360
-#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1361
-#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1362
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1363
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1364
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1365
-#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1366
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1367
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1368
-#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1369
-
1370
-#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1371
-#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1372
-#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1373
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1374
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1375
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1376
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
1377
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
1378
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
1379
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
1380
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
1381
-#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1382
-#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1383
-#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1384
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1385
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1386
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1387
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
1388
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
1389
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
1390
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
1391
-#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL
1392
-
1393
-#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1394
-#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1395
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1396
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1397
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1398
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1399
-#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1400
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1401
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1402
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1403
-#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1404
-
1405
-#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1406
-#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1407
-#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1408
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1409
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1410
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1411
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1412
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
1413
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
1414
-#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1415
-#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1416
-#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1417
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1418
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1419
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1420
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1421
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
1422
-#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
1423
-
1424
-#define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1425
-#define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1426
-#define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1427
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1428
-#define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
1429
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1430
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1431
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1432
-#define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1433
-#define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1434
-#define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1435
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1436
-#define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
1437
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1438
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1439
-#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1440
-
1441
-#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1442
-#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		13
1443
-#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1444
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1445
-#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
1446
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1447
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1448
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1449
-#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT		59
1450
-#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000001fffUL
1451
-#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000006000UL
1452
-#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1453
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1454
-#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
1455
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1456
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1457
-#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1458
-#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK		0xf800000000000000UL
1459
-
1460
-
1461
-union uvh_gr1_tlb_mmr_control_u {
1462
-	unsigned long	v;
1463
-	struct uvh_gr1_tlb_mmr_control_s {
1464
-		unsigned long	rsvd_0_15:16;
1465
-		unsigned long	auto_valid_en:1;		/* RW */
1466
-		unsigned long	rsvd_17_19:3;
1467
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1468
-		unsigned long	rsvd_21_29:9;
1469
-		unsigned long	mmr_write:1;			/* WP */
1470
-		unsigned long	mmr_read:1;			/* WP */
1471
-		unsigned long	rsvd_32_48:17;
1472
-		unsigned long	rsvd_49_51:3;
1473
-		unsigned long	rsvd_52_63:12;
1474
-	} s;
1475
-	struct uv1h_gr1_tlb_mmr_control_s {
1476
-		unsigned long	index:12;			/* RW */
1477
-		unsigned long	mem_sel:2;			/* RW */
1478
-		unsigned long	rsvd_14_15:2;
1479
-		unsigned long	auto_valid_en:1;		/* RW */
1480
-		unsigned long	rsvd_17_19:3;
1481
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1482
-		unsigned long	rsvd_21_29:9;
1483
-		unsigned long	mmr_write:1;			/* WP */
1484
-		unsigned long	mmr_read:1;			/* WP */
1485
-		unsigned long	rsvd_32_47:16;
1486
-		unsigned long	mmr_inj_con:1;			/* RW */
1487
-		unsigned long	rsvd_49_51:3;
1488
-		unsigned long	mmr_inj_tlbram:1;		/* RW */
1489
-		unsigned long	rsvd_53:1;
1490
-		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
1491
-		unsigned long	rsvd_55:1;
1492
-		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
1493
-		unsigned long	rsvd_57_59:3;
1494
-		unsigned long	mmr_inj_tlblruv:1;		/* RW */
1495
-		unsigned long	rsvd_61_63:3;
1496
-	} s1;
1497
-	struct uvxh_gr1_tlb_mmr_control_s {
1498
-		unsigned long	rsvd_0_15:16;
1499
-		unsigned long	auto_valid_en:1;		/* RW */
1500
-		unsigned long	rsvd_17_19:3;
1501
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1502
-		unsigned long	rsvd_21_29:9;
1503
-		unsigned long	mmr_write:1;			/* WP */
1504
-		unsigned long	mmr_read:1;			/* WP */
1505
-		unsigned long	mmr_op_done:1;			/* RW */
1506
-		unsigned long	rsvd_33_47:15;
1507
-		unsigned long	rsvd_48:1;
1508
-		unsigned long	rsvd_49_51:3;
1509
-		unsigned long	rsvd_52_63:12;
1510
-	} sx;
1511
-	struct uv2h_gr1_tlb_mmr_control_s {
1512
-		unsigned long	index:12;			/* RW */
1513
-		unsigned long	mem_sel:2;			/* RW */
1514
-		unsigned long	rsvd_14_15:2;
1515
-		unsigned long	auto_valid_en:1;		/* RW */
1516
-		unsigned long	rsvd_17_19:3;
1517
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1518
-		unsigned long	rsvd_21_29:9;
1519
-		unsigned long	mmr_write:1;			/* WP */
1520
-		unsigned long	mmr_read:1;			/* WP */
1521
-		unsigned long	mmr_op_done:1;			/* RW */
1522
-		unsigned long	rsvd_33_47:15;
1523
-		unsigned long	mmr_inj_con:1;			/* RW */
1524
-		unsigned long	rsvd_49_51:3;
1525
-		unsigned long	mmr_inj_tlbram:1;		/* RW */
1526
-		unsigned long	rsvd_53_63:11;
1527
-	} s2;
1528
-	struct uv3h_gr1_tlb_mmr_control_s {
1529
-		unsigned long	index:12;			/* RW */
1530
-		unsigned long	mem_sel:2;			/* RW */
1531
-		unsigned long	rsvd_14_15:2;
1532
-		unsigned long	auto_valid_en:1;		/* RW */
1533
-		unsigned long	rsvd_17_19:3;
1534
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1535
-		unsigned long	ecc_sel:1;			/* RW */
1536
-		unsigned long	rsvd_22_29:8;
1537
-		unsigned long	mmr_write:1;			/* WP */
1538
-		unsigned long	mmr_read:1;			/* WP */
1539
-		unsigned long	mmr_op_done:1;			/* RW */
1540
-		unsigned long	rsvd_33_47:15;
1541
-		unsigned long	undef_48:1;			/* Undefined */
1542
-		unsigned long	rsvd_49_51:3;
1543
-		unsigned long	undef_52:1;			/* Undefined */
1544
-		unsigned long	rsvd_53_63:11;
1545
-	} s3;
1546
-	struct uv4h_gr1_tlb_mmr_control_s {
1547
-		unsigned long	index:13;			/* RW */
1548
-		unsigned long	mem_sel:2;			/* RW */
1549
-		unsigned long	rsvd_15:1;
1550
-		unsigned long	auto_valid_en:1;		/* RW */
1551
-		unsigned long	rsvd_17_19:3;
1552
-		unsigned long	mmr_hash_index_en:1;		/* RW */
1553
-		unsigned long	ecc_sel:1;			/* RW */
1554
-		unsigned long	rsvd_22_29:8;
1555
-		unsigned long	mmr_write:1;			/* WP */
1556
-		unsigned long	mmr_read:1;			/* WP */
1557
-		unsigned long	mmr_op_done:1;			/* RW */
1558
-		unsigned long	rsvd_33_47:15;
1559
-		unsigned long	undef_48:1;			/* Undefined */
1560
-		unsigned long	rsvd_49_51:3;
1561
-		unsigned long	rsvd_52_58:7;
1562
-		unsigned long	page_size:5;			/* RW */
1563
-	} s4;
1564
-};
1565
-
1566
-/* ========================================================================= */
1567
-/*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
1568
-/* ========================================================================= */
1569
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
1570
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1571
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1572
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL
1573
-#define UVH_GR1_TLB_MMR_READ_DATA_HI (					\
1574
-	is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :			\
1575
-	is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :			\
1576
-	is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI :			\
1577
-	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI)
1578
-
1579
-#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1580
-
1581
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1582
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1583
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1584
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1585
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1586
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1587
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1588
-#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1589
-
1590
-#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1591
-
1592
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1593
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1594
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1595
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1596
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1597
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1598
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1599
-#define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1600
-
1601
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1602
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1603
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1604
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1605
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
1606
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1607
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1608
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1609
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1610
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1611
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
1612
-#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1613
-
1614
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1615
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT		34
1616
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		49
1617
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	51
1618
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	52
1619
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	53
1620
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1621
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x00000003ffffffffUL
1622
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK		0x0001fffc00000000UL
1623
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0006000000000000UL
1624
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0008000000000000UL
1625
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0010000000000000UL
1626
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0020000000000000UL
1627
-#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1628
-
1629
-
1630
-union uvh_gr1_tlb_mmr_read_data_hi_u {
1631
-	unsigned long	v;
1632
-	struct uv1h_gr1_tlb_mmr_read_data_hi_s {
1633
-		unsigned long	pfn:41;				/* RO */
1634
-		unsigned long	gaa:2;				/* RO */
1635
-		unsigned long	dirty:1;			/* RO */
1636
-		unsigned long	larger:1;			/* RO */
1637
-		unsigned long	rsvd_45_63:19;
1638
-	} s1;
1639
-	struct uv2h_gr1_tlb_mmr_read_data_hi_s {
1640
-		unsigned long	pfn:41;				/* RO */
1641
-		unsigned long	gaa:2;				/* RO */
1642
-		unsigned long	dirty:1;			/* RO */
1643
-		unsigned long	larger:1;			/* RO */
1644
-		unsigned long	rsvd_45_63:19;
1645
-	} s2;
1646
-	struct uv3h_gr1_tlb_mmr_read_data_hi_s {
1647
-		unsigned long	pfn:41;				/* RO */
1648
-		unsigned long	gaa:2;				/* RO */
1649
-		unsigned long	dirty:1;			/* RO */
1650
-		unsigned long	larger:1;			/* RO */
1651
-		unsigned long	aa_ext:1;			/* RO */
1652
-		unsigned long	undef_46_54:9;			/* Undefined */
1653
-		unsigned long	way_ecc:9;			/* RO */
1654
-	} s3;
1655
-	struct uv4h_gr1_tlb_mmr_read_data_hi_s {
1656
-		unsigned long	pfn:34;				/* RO */
1657
-		unsigned long	pnid:15;			/* RO */
1658
-		unsigned long	gaa:2;				/* RO */
1659
-		unsigned long	dirty:1;			/* RO */
1660
-		unsigned long	larger:1;			/* RO */
1661
-		unsigned long	aa_ext:1;			/* RO */
1662
-		unsigned long	undef_54:1;			/* Undefined */
1663
-		unsigned long	way_ecc:9;			/* RO */
1664
-	} s4;
1665
-};
1666
-
1667
-/* ========================================================================= */
1668
-/*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
1669
-/* ========================================================================= */
1670
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
1671
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1672
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1673
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL
1674
-#define UVH_GR1_TLB_MMR_READ_DATA_LO (					\
1675
-	is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :			\
1676
-	is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :			\
1677
-	is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO :			\
1678
-	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO)
1679
-
1680
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1681
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1682
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
1683
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1684
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1685
-#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL
1686
-
1687
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1688
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1689
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1690
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1691
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1692
-#define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1693
-
1694
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1695
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1696
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1697
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1698
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1699
-#define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1700
-
1701
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1702
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1703
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1704
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1705
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1706
-#define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1707
-
1708
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1709
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1710
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1711
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1712
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1713
-#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1714
-
1715
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1716
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1717
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1718
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1719
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1720
-#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1721
-
1722
-
1723
-union uvh_gr1_tlb_mmr_read_data_lo_u {
1724
-	unsigned long	v;
1725
-	struct uvh_gr1_tlb_mmr_read_data_lo_s {
1726
-		unsigned long	vpn:39;				/* RO */
1727
-		unsigned long	asid:24;			/* RO */
1728
-		unsigned long	valid:1;			/* RO */
1729
-	} s;
1730
-	struct uv1h_gr1_tlb_mmr_read_data_lo_s {
1731
-		unsigned long	vpn:39;				/* RO */
1732
-		unsigned long	asid:24;			/* RO */
1733
-		unsigned long	valid:1;			/* RO */
1734
-	} s1;
1735
-	struct uvxh_gr1_tlb_mmr_read_data_lo_s {
1736
-		unsigned long	vpn:39;				/* RO */
1737
-		unsigned long	asid:24;			/* RO */
1738
-		unsigned long	valid:1;			/* RO */
1739
-	} sx;
1740
-	struct uv2h_gr1_tlb_mmr_read_data_lo_s {
1741
-		unsigned long	vpn:39;				/* RO */
1742
-		unsigned long	asid:24;			/* RO */
1743
-		unsigned long	valid:1;			/* RO */
1744
-	} s2;
1745
-	struct uv3h_gr1_tlb_mmr_read_data_lo_s {
1746
-		unsigned long	vpn:39;				/* RO */
1747
-		unsigned long	asid:24;			/* RO */
1748
-		unsigned long	valid:1;			/* RO */
1749
-	} s3;
1750
-	struct uv4h_gr1_tlb_mmr_read_data_lo_s {
1751
-		unsigned long	vpn:39;				/* RO */
1752
-		unsigned long	asid:24;			/* RO */
1753
-		unsigned long	valid:1;			/* RO */
1754
-	} s4;
1755
-};
1756
-
1757
-/* ========================================================================= */
1758
-/*                               UVH_INT_CMPB                                */
1759
-/* ========================================================================= */
1760
-#define UVH_INT_CMPB 0x22080UL
1761
-
1762
-#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT		0
1763
-#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK		0x00ffffffffffffffUL
1764
-
1765
-
1766
-union uvh_int_cmpb_u {
1767
-	unsigned long	v;
1768
-	struct uvh_int_cmpb_s {
1769
-		unsigned long	real_time_cmpb:56;		/* RW */
1770
-		unsigned long	rsvd_56_63:8;
1771
-	} s;
1772
-};
1773
-
1774
-/* ========================================================================= */
1775
-/*                               UVH_INT_CMPC                                */
1776
-/* ========================================================================= */
1777
-#define UVH_INT_CMPC 0x22100UL
1778
-
1779
-
1780
-#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT		0
1781
-#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK		0x00ffffffffffffffUL
1782
-
1783
-#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT		0
1784
-#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK		0x00ffffffffffffffUL
1785
-
1786
-
1787
-union uvh_int_cmpc_u {
1788
-	unsigned long	v;
1789
-	struct uvh_int_cmpc_s {
1790
-		unsigned long	real_time_cmpc:56;		/* RW */
1791
-		unsigned long	rsvd_56_63:8;
1792
-	} s;
1793
-};
1794
-
1795
-/* ========================================================================= */
1796
-/*                               UVH_INT_CMPD                                */
1797
-/* ========================================================================= */
1798
-#define UVH_INT_CMPD 0x22180UL
1799
-
1800
-
1801
-#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT		0
1802
-#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK		0x00ffffffffffffffUL
1803
-
1804
-#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT		0
1805
-#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK		0x00ffffffffffffffUL
1806
-
1807
-
1808
-union uvh_int_cmpd_u {
1809
-	unsigned long	v;
1810
-	struct uvh_int_cmpd_s {
1811
-		unsigned long	real_time_cmpd:56;		/* RW */
1812
-		unsigned long	rsvd_56_63:8;
1813
-	} s;
1814
-};
1815
-
1816
-/* ========================================================================= */
1817
-/*                               UVH_IPI_INT                                 */
1818
-/* ========================================================================= */
1819
-#define UVH_IPI_INT 0x60500UL
1820
-
1821
-#define UV1H_IPI_INT_32 0x348
1822
-#define UV2H_IPI_INT_32 0x348
1823
-#define UV3H_IPI_INT_32 0x348
1824
-#define UV4H_IPI_INT_32 0x268
1825
-#define UVH_IPI_INT_32 (						\
1826
-	is_uv1_hub() ? UV1H_IPI_INT_32 :				\
1827
-	is_uv2_hub() ? UV2H_IPI_INT_32 :				\
1828
-	is_uv3_hub() ? UV3H_IPI_INT_32 :				\
1829
-	/*is_uv4_hub*/ UV4H_IPI_INT_32)
1830
-
1831
-#define UVH_IPI_INT_VECTOR_SHFT				0
1832
-#define UVH_IPI_INT_DELIVERY_MODE_SHFT			8
1833
-#define UVH_IPI_INT_DESTMODE_SHFT			11
1834
-#define UVH_IPI_INT_APIC_ID_SHFT			16
1835
-#define UVH_IPI_INT_SEND_SHFT				63
1836
-#define UVH_IPI_INT_VECTOR_MASK				0x00000000000000ffUL
1837
-#define UVH_IPI_INT_DELIVERY_MODE_MASK			0x0000000000000700UL
1838
-#define UVH_IPI_INT_DESTMODE_MASK			0x0000000000000800UL
1839
-#define UVH_IPI_INT_APIC_ID_MASK			0x0000ffffffff0000UL
1840
-#define UVH_IPI_INT_SEND_MASK				0x8000000000000000UL
1841
-
1842
-
1843
-union uvh_ipi_int_u {
1844
-	unsigned long	v;
1845
-	struct uvh_ipi_int_s {
1846
-		unsigned long	vector_:8;			/* RW */
1847
-		unsigned long	delivery_mode:3;		/* RW */
1848
-		unsigned long	destmode:1;			/* RW */
1849
-		unsigned long	rsvd_12_15:4;
1850
-		unsigned long	apic_id:32;			/* RW */
1851
-		unsigned long	rsvd_48_62:15;
1852
-		unsigned long	send:1;				/* WP */
1853
-	} s;
1854
-};
1855
-
1856
-/* ========================================================================= */
1857
-/*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
1858
-/* ========================================================================= */
1859
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1860
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1861
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1862
-#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST")
1863
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST (				\
1864
-	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1865
-	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1866
-	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1867
-	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST)
1868
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1869
-
1870
-
1871
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1872
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1873
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1874
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1875
-
1876
-
1877
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1878
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1879
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1880
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1881
-
1882
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1883
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1884
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1885
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1886
-
1887
-
1888
-union uvh_lb_bau_intd_payload_queue_first_u {
1889
-	unsigned long	v;
1890
-	struct uv1h_lb_bau_intd_payload_queue_first_s {
1891
-		unsigned long	rsvd_0_3:4;
1892
-		unsigned long	address:39;			/* RW */
1893
-		unsigned long	rsvd_43_48:6;
1894
-		unsigned long	node_id:14;			/* RW */
1895
-		unsigned long	rsvd_63:1;
1896
-	} s1;
1897
-	struct uv2h_lb_bau_intd_payload_queue_first_s {
1898
-		unsigned long	rsvd_0_3:4;
1899
-		unsigned long	address:39;			/* RW */
1900
-		unsigned long	rsvd_43_48:6;
1901
-		unsigned long	node_id:14;			/* RW */
1902
-		unsigned long	rsvd_63:1;
1903
-	} s2;
1904
-	struct uv3h_lb_bau_intd_payload_queue_first_s {
1905
-		unsigned long	rsvd_0_3:4;
1906
-		unsigned long	address:39;			/* RW */
1907
-		unsigned long	rsvd_43_48:6;
1908
-		unsigned long	node_id:14;			/* RW */
1909
-		unsigned long	rsvd_63:1;
1910
-	} s3;
1911
-};
1912
-
1913
-/* ========================================================================= */
1914
-/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
1915
-/* ========================================================================= */
1916
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1917
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1918
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1919
-#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST")
1920
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST (				\
1921
-	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1922
-	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1923
-	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1924
-	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST)
1925
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1926
-
1927
-
1928
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1929
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1930
-
1931
-
1932
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1933
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1934
-
1935
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1936
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1937
-
1938
-
1939
-union uvh_lb_bau_intd_payload_queue_last_u {
1940
-	unsigned long	v;
1941
-	struct uv1h_lb_bau_intd_payload_queue_last_s {
1942
-		unsigned long	rsvd_0_3:4;
1943
-		unsigned long	address:39;			/* RW */
1944
-		unsigned long	rsvd_43_63:21;
1945
-	} s1;
1946
-	struct uv2h_lb_bau_intd_payload_queue_last_s {
1947
-		unsigned long	rsvd_0_3:4;
1948
-		unsigned long	address:39;			/* RW */
1949
-		unsigned long	rsvd_43_63:21;
1950
-	} s2;
1951
-	struct uv3h_lb_bau_intd_payload_queue_last_s {
1952
-		unsigned long	rsvd_0_3:4;
1953
-		unsigned long	address:39;			/* RW */
1954
-		unsigned long	rsvd_43_63:21;
1955
-	} s3;
1956
-};
1957
-
1958
-/* ========================================================================= */
1959
-/*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
1960
-/* ========================================================================= */
1961
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1962
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1963
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1964
-#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL")
1965
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL (				\
1966
-	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1967
-	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1968
-	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1969
-	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL)
1970
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1971
-
1972
-
1973
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1974
-#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1975
-
1976
-
1977
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1978
-#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1979
-
1980
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1981
-#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1982
-
1983
-
1984
-union uvh_lb_bau_intd_payload_queue_tail_u {
1985
-	unsigned long	v;
1986
-	struct uv1h_lb_bau_intd_payload_queue_tail_s {
1987
-		unsigned long	rsvd_0_3:4;
1988
-		unsigned long	address:39;			/* RW */
1989
-		unsigned long	rsvd_43_63:21;
1990
-	} s1;
1991
-	struct uv2h_lb_bau_intd_payload_queue_tail_s {
1992
-		unsigned long	rsvd_0_3:4;
1993
-		unsigned long	address:39;			/* RW */
1994
-		unsigned long	rsvd_43_63:21;
1995
-	} s2;
1996
-	struct uv3h_lb_bau_intd_payload_queue_tail_s {
1997
-		unsigned long	rsvd_0_3:4;
1998
-		unsigned long	address:39;			/* RW */
1999
-		unsigned long	rsvd_43_63:21;
2000
-	} s3;
2001
-};
2002
-
2003
-/* ========================================================================= */
2004
-/*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
2005
-/* ========================================================================= */
2006
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2007
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2008
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2009
-#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE")
2010
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE (				\
2011
-	is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2012
-	is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2013
-	is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2014
-	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE)
2015
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
2016
-
2017
-
2018
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2019
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2020
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2021
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2022
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2023
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2024
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2025
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2026
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2027
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2028
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2029
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2030
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2031
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2032
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2033
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2034
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2035
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2036
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2037
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2038
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2039
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2040
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2041
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2042
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2043
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2044
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2045
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2046
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2047
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2048
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2049
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2050
-
2051
-
2052
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2053
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2054
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2055
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2056
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2057
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2058
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2059
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2060
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2061
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2062
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2063
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2064
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2065
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2066
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2067
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2068
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2069
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2070
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2071
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2072
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2073
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2074
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2075
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2076
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2077
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2078
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2079
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2080
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2081
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2082
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2083
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2084
-
2085
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2086
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2087
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2088
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2089
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2090
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2091
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2092
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2093
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2094
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2095
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2096
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2097
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2098
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2099
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2100
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2101
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2102
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2103
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2104
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2105
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2106
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2107
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2108
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2109
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2110
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2111
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2112
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2113
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2114
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2115
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2116
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2117
-
2118
-
2119
-union uvh_lb_bau_intd_software_acknowledge_u {
2120
-	unsigned long	v;
2121
-	struct uv1h_lb_bau_intd_software_acknowledge_s {
2122
-		unsigned long	pending_0:1;			/* RW, W1C */
2123
-		unsigned long	pending_1:1;			/* RW, W1C */
2124
-		unsigned long	pending_2:1;			/* RW, W1C */
2125
-		unsigned long	pending_3:1;			/* RW, W1C */
2126
-		unsigned long	pending_4:1;			/* RW, W1C */
2127
-		unsigned long	pending_5:1;			/* RW, W1C */
2128
-		unsigned long	pending_6:1;			/* RW, W1C */
2129
-		unsigned long	pending_7:1;			/* RW, W1C */
2130
-		unsigned long	timeout_0:1;			/* RW, W1C */
2131
-		unsigned long	timeout_1:1;			/* RW, W1C */
2132
-		unsigned long	timeout_2:1;			/* RW, W1C */
2133
-		unsigned long	timeout_3:1;			/* RW, W1C */
2134
-		unsigned long	timeout_4:1;			/* RW, W1C */
2135
-		unsigned long	timeout_5:1;			/* RW, W1C */
2136
-		unsigned long	timeout_6:1;			/* RW, W1C */
2137
-		unsigned long	timeout_7:1;			/* RW, W1C */
2138
-		unsigned long	rsvd_16_63:48;
2139
-	} s1;
2140
-	struct uv2h_lb_bau_intd_software_acknowledge_s {
2141
-		unsigned long	pending_0:1;			/* RW */
2142
-		unsigned long	pending_1:1;			/* RW */
2143
-		unsigned long	pending_2:1;			/* RW */
2144
-		unsigned long	pending_3:1;			/* RW */
2145
-		unsigned long	pending_4:1;			/* RW */
2146
-		unsigned long	pending_5:1;			/* RW */
2147
-		unsigned long	pending_6:1;			/* RW */
2148
-		unsigned long	pending_7:1;			/* RW */
2149
-		unsigned long	timeout_0:1;			/* RW */
2150
-		unsigned long	timeout_1:1;			/* RW */
2151
-		unsigned long	timeout_2:1;			/* RW */
2152
-		unsigned long	timeout_3:1;			/* RW */
2153
-		unsigned long	timeout_4:1;			/* RW */
2154
-		unsigned long	timeout_5:1;			/* RW */
2155
-		unsigned long	timeout_6:1;			/* RW */
2156
-		unsigned long	timeout_7:1;			/* RW */
2157
-		unsigned long	rsvd_16_63:48;
2158
-	} s2;
2159
-	struct uv3h_lb_bau_intd_software_acknowledge_s {
2160
-		unsigned long	pending_0:1;			/* RW */
2161
-		unsigned long	pending_1:1;			/* RW */
2162
-		unsigned long	pending_2:1;			/* RW */
2163
-		unsigned long	pending_3:1;			/* RW */
2164
-		unsigned long	pending_4:1;			/* RW */
2165
-		unsigned long	pending_5:1;			/* RW */
2166
-		unsigned long	pending_6:1;			/* RW */
2167
-		unsigned long	pending_7:1;			/* RW */
2168
-		unsigned long	timeout_0:1;			/* RW */
2169
-		unsigned long	timeout_1:1;			/* RW */
2170
-		unsigned long	timeout_2:1;			/* RW */
2171
-		unsigned long	timeout_3:1;			/* RW */
2172
-		unsigned long	timeout_4:1;			/* RW */
2173
-		unsigned long	timeout_5:1;			/* RW */
2174
-		unsigned long	timeout_6:1;			/* RW */
2175
-		unsigned long	timeout_7:1;			/* RW */
2176
-		unsigned long	rsvd_16_63:48;
2177
-	} s3;
2178
-};
2179
-
2180
-/* ========================================================================= */
2181
-/*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
2182
-/* ========================================================================= */
2183
-#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2184
-#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2185
-#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2186
-#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS")
2187
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS (			\
2188
-	is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2189
-	is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2190
-	is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2191
-	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS)
2192
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
2193
-
2194
-
2195
-/* ========================================================================= */
2196
-/*                         UVH_LB_BAU_MISC_CONTROL                           */
2197
-/* ========================================================================= */
2198
-#define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
2199
-#define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
2200
-#define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
2201
-#define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL
2202
-#define UVH_LB_BAU_MISC_CONTROL (					\
2203
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL :			\
2204
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL :			\
2205
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL :			\
2206
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL)
2207
-
2208
-#define UV1H_LB_BAU_MISC_CONTROL_32 0xa10
2209
-#define UV2H_LB_BAU_MISC_CONTROL_32 0xa10
2210
-#define UV3H_LB_BAU_MISC_CONTROL_32 0xa10
2211
-#define UV4H_LB_BAU_MISC_CONTROL_32 0xa18
2212
-#define UVH_LB_BAU_MISC_CONTROL_32 (					\
2213
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 :			\
2214
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 :			\
2215
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 :			\
2216
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32)
2217
-
2218
-#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2219
-#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2220
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2221
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2222
-#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2223
-#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2224
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2225
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2226
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2227
-#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2228
-#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2229
-#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2230
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2231
-#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2232
-#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2233
-#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2234
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2235
-#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2236
-#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2237
-#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2238
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2239
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2240
-#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2241
-#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2242
-#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2243
-#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2244
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2245
-#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2246
-
2247
-#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2248
-#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2249
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2250
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2251
-#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2252
-#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2253
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2254
-#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2255
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2256
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2257
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2258
-#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2259
-#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2260
-#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2261
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2262
-#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2263
-#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2264
-#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2265
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2266
-#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2267
-#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2268
-#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2269
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2270
-#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2271
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2272
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2273
-#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2274
-#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2275
-#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2276
-#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2277
-#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2278
-#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2279
-
2280
-#define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2281
-#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2282
-#define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2283
-#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2284
-#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2285
-#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2286
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2287
-#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2288
-#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2289
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2290
-#define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2291
-#define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2292
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2293
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2294
-#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2295
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2296
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2297
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2298
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2299
-#define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2300
-#define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2301
-#define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2302
-#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2303
-#define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2304
-#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2305
-#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2306
-#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2307
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2308
-#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2309
-#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2310
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2311
-#define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2312
-#define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2313
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2314
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2315
-#define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2316
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2317
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2318
-#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2319
-#define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2320
-#define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2321
-#define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2322
-
2323
-#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2324
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2325
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2326
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2327
-#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2328
-#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2329
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2330
-#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2331
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2332
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2333
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2334
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2335
-#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2336
-#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2337
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2338
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2339
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2340
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2341
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2342
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2343
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2344
-#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2345
-#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2346
-#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2347
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2348
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2349
-#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2350
-#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2351
-#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2352
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2353
-#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2354
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2355
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2356
-#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2357
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2358
-#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2359
-#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2360
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2361
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2362
-#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2363
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2364
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2365
-#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2366
-#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2367
-#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2368
-#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2369
-
2370
-#define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2371
-#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2372
-#define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2373
-#define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2374
-#define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2375
-#define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2376
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2377
-#define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2378
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2379
-#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2380
-#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2381
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2382
-#define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2383
-#define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2384
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2385
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2386
-#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2387
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2388
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2389
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2390
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2391
-#define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2392
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2393
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37
2394
-#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2395
-#define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2396
-#define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2397
-#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2398
-#define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2399
-#define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2400
-#define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2401
-#define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2402
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2403
-#define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2404
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2405
-#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2406
-#define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2407
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2408
-#define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2409
-#define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2410
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2411
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2412
-#define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2413
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2414
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2415
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2416
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2417
-#define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2418
-#define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2419
-#define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL
2420
-#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2421
-#define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2422
-
2423
-#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2424
-#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2425
-#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2426
-#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2427
-#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2428
-#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2429
-#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT	15
2430
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2431
-#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2432
-#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2433
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2434
-#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2435
-#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2436
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2437
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2438
-#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2439
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2440
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2441
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2442
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2443
-#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2444
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2445
-#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT	37
2446
-#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2447
-#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46
2448
-#define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2449
-#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2450
-#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2451
-#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2452
-#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2453
-#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2454
-#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2455
-#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK	0x00000000000f8000UL
2456
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2457
-#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2458
-#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2459
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2460
-#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2461
-#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2462
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2463
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2464
-#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2465
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2466
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2467
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2468
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2469
-#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2470
-#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2471
-#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK	0x0000002000000000UL
2472
-#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2473
-#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL
2474
-#define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2475
-
2476
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK	\
2477
-	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK")
2478
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK (	\
2479
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2480
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2481
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2482
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK)
2483
-#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT	\
2484
-	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT")
2485
-#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT (	\
2486
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2487
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2488
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2489
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT)
2490
-#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK	\
2491
-	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK")
2492
-#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK (	\
2493
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2494
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2495
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2496
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK)
2497
-#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT	\
2498
-	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT")
2499
-#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT (	\
2500
-	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2501
-	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2502
-	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2503
-	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT)
2504
-
2505
-union uvh_lb_bau_misc_control_u {
2506
-	unsigned long	v;
2507
-	struct uvh_lb_bau_misc_control_s {
2508
-		unsigned long	rejection_delay:8;		/* RW */
2509
-		unsigned long	apic_mode:1;			/* RW */
2510
-		unsigned long	force_broadcast:1;		/* RW */
2511
-		unsigned long	force_lock_nop:1;		/* RW */
2512
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2513
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2514
-		unsigned long	rsvd_15_19:5;
2515
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2516
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2517
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2518
-		unsigned long	suppress_dest_registration:1;	/* RW */
2519
-		unsigned long	programmed_initial_priority:3;	/* RW */
2520
-		unsigned long	use_incoming_priority:1;	/* RW */
2521
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2522
-		unsigned long	rsvd_29_47:19;
2523
-		unsigned long	fun:16;				/* RW */
2524
-	} s;
2525
-	struct uv1h_lb_bau_misc_control_s {
2526
-		unsigned long	rejection_delay:8;		/* RW */
2527
-		unsigned long	apic_mode:1;			/* RW */
2528
-		unsigned long	force_broadcast:1;		/* RW */
2529
-		unsigned long	force_lock_nop:1;		/* RW */
2530
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2531
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2532
-		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2533
-		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2534
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2535
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2536
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2537
-		unsigned long	suppress_dest_registration:1;	/* RW */
2538
-		unsigned long	programmed_initial_priority:3;	/* RW */
2539
-		unsigned long	use_incoming_priority:1;	/* RW */
2540
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2541
-		unsigned long	rsvd_29_47:19;
2542
-		unsigned long	fun:16;				/* RW */
2543
-	} s1;
2544
-	struct uvxh_lb_bau_misc_control_s {
2545
-		unsigned long	rejection_delay:8;		/* RW */
2546
-		unsigned long	apic_mode:1;			/* RW */
2547
-		unsigned long	force_broadcast:1;		/* RW */
2548
-		unsigned long	force_lock_nop:1;		/* RW */
2549
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2550
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2551
-		unsigned long	rsvd_15_19:5;
2552
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2553
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2554
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2555
-		unsigned long	suppress_dest_registration:1;	/* RW */
2556
-		unsigned long	programmed_initial_priority:3;	/* RW */
2557
-		unsigned long	use_incoming_priority:1;	/* RW */
2558
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2559
-		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2560
-		unsigned long	apic_mode_status:1;		/* RO */
2561
-		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2562
-		unsigned long	enable_lock_based_system_flush:1;/* RW */
2563
-		unsigned long	enable_extended_sb_status:1;	/* RW */
2564
-		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2565
-		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2566
-		unsigned long	rsvd_36_47:12;
2567
-		unsigned long	fun:16;				/* RW */
2568
-	} sx;
2569
-	struct uv2h_lb_bau_misc_control_s {
2570
-		unsigned long	rejection_delay:8;		/* RW */
2571
-		unsigned long	apic_mode:1;			/* RW */
2572
-		unsigned long	force_broadcast:1;		/* RW */
2573
-		unsigned long	force_lock_nop:1;		/* RW */
2574
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2575
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2576
-		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2577
-		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2578
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2579
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2580
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2581
-		unsigned long	suppress_dest_registration:1;	/* RW */
2582
-		unsigned long	programmed_initial_priority:3;	/* RW */
2583
-		unsigned long	use_incoming_priority:1;	/* RW */
2584
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2585
-		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2586
-		unsigned long	apic_mode_status:1;		/* RO */
2587
-		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2588
-		unsigned long	enable_lock_based_system_flush:1;/* RW */
2589
-		unsigned long	enable_extended_sb_status:1;	/* RW */
2590
-		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2591
-		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2592
-		unsigned long	rsvd_36_47:12;
2593
-		unsigned long	fun:16;				/* RW */
2594
-	} s2;
2595
-	struct uv3h_lb_bau_misc_control_s {
2596
-		unsigned long	rejection_delay:8;		/* RW */
2597
-		unsigned long	apic_mode:1;			/* RW */
2598
-		unsigned long	force_broadcast:1;		/* RW */
2599
-		unsigned long	force_lock_nop:1;		/* RW */
2600
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2601
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2602
-		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2603
-		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2604
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2605
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2606
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2607
-		unsigned long	suppress_dest_registration:1;	/* RW */
2608
-		unsigned long	programmed_initial_priority:3;	/* RW */
2609
-		unsigned long	use_incoming_priority:1;	/* RW */
2610
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2611
-		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2612
-		unsigned long	apic_mode_status:1;		/* RO */
2613
-		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2614
-		unsigned long	enable_lock_based_system_flush:1;/* RW */
2615
-		unsigned long	enable_extended_sb_status:1;	/* RW */
2616
-		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2617
-		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2618
-		unsigned long	suppress_quiesce_msgs_to_qpi:1;	/* RW */
2619
-		unsigned long	enable_intd_prefetch_hint:1;	/* RW */
2620
-		unsigned long	thread_kill_timebase:8;		/* RW */
2621
-		unsigned long	rsvd_46_47:2;
2622
-		unsigned long	fun:16;				/* RW */
2623
-	} s3;
2624
-	struct uv4h_lb_bau_misc_control_s {
2625
-		unsigned long	rejection_delay:8;		/* RW */
2626
-		unsigned long	apic_mode:1;			/* RW */
2627
-		unsigned long	force_broadcast:1;		/* RW */
2628
-		unsigned long	force_lock_nop:1;		/* RW */
2629
-		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2630
-		unsigned long	descriptor_fetch_mode:1;	/* RW */
2631
-		unsigned long	rsvd_15_19:5;
2632
-		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2633
-		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2634
-		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2635
-		unsigned long	suppress_dest_registration:1;	/* RW */
2636
-		unsigned long	programmed_initial_priority:3;	/* RW */
2637
-		unsigned long	use_incoming_priority:1;	/* RW */
2638
-		unsigned long	enable_programmed_initial_priority:1;/* RW */
2639
-		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2640
-		unsigned long	apic_mode_status:1;		/* RO */
2641
-		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2642
-		unsigned long	enable_lock_based_system_flush:1;/* RW */
2643
-		unsigned long	enable_extended_sb_status:1;	/* RW */
2644
-		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2645
-		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2646
-		unsigned long	suppress_quiesce_msgs_to_qpi:1;	/* RW */
2647
-		unsigned long	rsvd_37:1;
2648
-		unsigned long	thread_kill_timebase:8;		/* RW */
2649
-		unsigned long	address_interleave_select:1;	/* RW */
2650
-		unsigned long	rsvd_47:1;
2651
-		unsigned long	fun:16;				/* RW */
2652
-	} s4;
2653
-};
2654
-
2655
-/* ========================================================================= */
2656
-/*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
2657
-/* ========================================================================= */
2658
-#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2659
-#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2660
-#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2661
-#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL
2662
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL (				\
2663
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2664
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2665
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2666
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL)
2667
-
2668
-#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2669
-#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2670
-#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2671
-#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8
2672
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 (				\
2673
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2674
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2675
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2676
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32)
2677
-
2678
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT	0
2679
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT	62
2680
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT	63
2681
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK	0x000000000000003fUL
2682
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK	0x4000000000000000UL
2683
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK	0x8000000000000000UL
2684
-
2685
-
2686
-union uvh_lb_bau_sb_activation_control_u {
2687
-	unsigned long	v;
2688
-	struct uvh_lb_bau_sb_activation_control_s {
2689
-		unsigned long	index:6;			/* RW */
2690
-		unsigned long	rsvd_6_61:56;
2691
-		unsigned long	push:1;				/* WP */
2692
-		unsigned long	init:1;				/* WP */
2693
-	} s;
2694
-};
2695
-
2696
-/* ========================================================================= */
2697
-/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
2698
-/* ========================================================================= */
2699
-#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2700
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2701
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2702
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL
2703
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 (				\
2704
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2705
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2706
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2707
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0)
2708
-
2709
-#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2710
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2711
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2712
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0
2713
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 (				\
2714
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2715
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2716
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2717
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32)
2718
-
2719
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT	0
2720
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK	0xffffffffffffffffUL
2721
-
2722
-
2723
-union uvh_lb_bau_sb_activation_status_0_u {
2724
-	unsigned long	v;
2725
-	struct uvh_lb_bau_sb_activation_status_0_s {
2726
-		unsigned long	status:64;			/* RW */
2727
-	} s;
2728
-};
2729
-
2730
-/* ========================================================================= */
2731
-/*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
2732
-/* ========================================================================= */
2733
-#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2734
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2735
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2736
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL
2737
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 (				\
2738
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2739
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2740
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2741
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1)
2742
-
2743
-#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2744
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2745
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2746
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8
2747
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 (				\
2748
-	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2749
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2750
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2751
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32)
2752
-
2753
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT	0
2754
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK	0xffffffffffffffffUL
2755
-
2756
-
2757
-union uvh_lb_bau_sb_activation_status_1_u {
2758
-	unsigned long	v;
2759
-	struct uvh_lb_bau_sb_activation_status_1_s {
2760
-		unsigned long	status:64;			/* RW */
2761
-	} s;
2762
-};
2763
-
2764
-/* ========================================================================= */
2765
-/*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
2766
-/* ========================================================================= */
2767
-#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2768
-#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2769
-#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2770
-#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL
2771
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE (					\
2772
-	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2773
-	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2774
-	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2775
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE)
2776
-
2777
-#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2778
-#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2779
-#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2780
-#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0
2781
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 (				\
2782
-	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2783
-	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2784
-	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2785
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32)
2786
-
2787
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT	12
2788
-
2789
-#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2790
-#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2791
-#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2792
-
2793
-#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2794
-#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2795
-#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2796
-
2797
-#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2798
-#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2799
-#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2800
-
2801
-#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2802
-#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL
2803
-#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2804
-
2805
-#define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	53
2806
-#define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000ffffffffff000UL
2807
-#define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0xffe0000000000000UL
2808
-
2809
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT (			\
2810
-	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2811
-	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2812
-	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2813
-	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2814
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT)
2815
-
2816
-#define UVH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK (			\
2817
-	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2818
-	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2819
-	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2820
-	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2821
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK)
2822
-
2823
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK (			\
2824
-	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2825
-	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2826
-	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2827
-	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2828
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK)
2829
-
2830
-/* ========================================================================= */
2831
-/*                               UVH_NODE_ID                                 */
2832
-/* ========================================================================= */
2833
-#define UVH_NODE_ID 0x0UL
2834
-#define UV1H_NODE_ID 0x0UL
2835
-#define UV2H_NODE_ID 0x0UL
2836
-#define UV3H_NODE_ID 0x0UL
2837
-#define UV4H_NODE_ID 0x0UL
2838
-
2839
-#define UVH_NODE_ID_FORCE1_SHFT				0
2840
-#define UVH_NODE_ID_MANUFACTURER_SHFT			1
2841
-#define UVH_NODE_ID_PART_NUMBER_SHFT			12
2842
-#define UVH_NODE_ID_REVISION_SHFT			28
2843
-#define UVH_NODE_ID_NODE_ID_SHFT			32
2844
-#define UVH_NODE_ID_FORCE1_MASK				0x0000000000000001UL
2845
-#define UVH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2846
-#define UVH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2847
-#define UVH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2848
-#define UVH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2849
-
2850
-#define UV1H_NODE_ID_FORCE1_SHFT			0
2851
-#define UV1H_NODE_ID_MANUFACTURER_SHFT			1
2852
-#define UV1H_NODE_ID_PART_NUMBER_SHFT			12
2853
-#define UV1H_NODE_ID_REVISION_SHFT			28
2854
-#define UV1H_NODE_ID_NODE_ID_SHFT			32
2855
-#define UV1H_NODE_ID_NODES_PER_BIT_SHFT			48
2856
-#define UV1H_NODE_ID_NI_PORT_SHFT			56
2857
-#define UV1H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2858
-#define UV1H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2859
-#define UV1H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2860
-#define UV1H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2861
-#define UV1H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2862
-#define UV1H_NODE_ID_NODES_PER_BIT_MASK			0x007f000000000000UL
2863
-#define UV1H_NODE_ID_NI_PORT_MASK			0x0f00000000000000UL
2864
-
2865
-#define UVXH_NODE_ID_FORCE1_SHFT			0
2866
-#define UVXH_NODE_ID_MANUFACTURER_SHFT			1
2867
-#define UVXH_NODE_ID_PART_NUMBER_SHFT			12
2868
-#define UVXH_NODE_ID_REVISION_SHFT			28
2869
-#define UVXH_NODE_ID_NODE_ID_SHFT			32
2870
-#define UVXH_NODE_ID_NODES_PER_BIT_SHFT			50
2871
-#define UVXH_NODE_ID_NI_PORT_SHFT			57
2872
-#define UVXH_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2873
-#define UVXH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2874
-#define UVXH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2875
-#define UVXH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2876
-#define UVXH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2877
-#define UVXH_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2878
-#define UVXH_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2879
-
2880
-#define UV2H_NODE_ID_FORCE1_SHFT			0
2881
-#define UV2H_NODE_ID_MANUFACTURER_SHFT			1
2882
-#define UV2H_NODE_ID_PART_NUMBER_SHFT			12
2883
-#define UV2H_NODE_ID_REVISION_SHFT			28
2884
-#define UV2H_NODE_ID_NODE_ID_SHFT			32
2885
-#define UV2H_NODE_ID_NODES_PER_BIT_SHFT			50
2886
-#define UV2H_NODE_ID_NI_PORT_SHFT			57
2887
-#define UV2H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2888
-#define UV2H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2889
-#define UV2H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2890
-#define UV2H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2891
-#define UV2H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2892
-#define UV2H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2893
-#define UV2H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2894
-
2895
-#define UV3H_NODE_ID_FORCE1_SHFT			0
2896
-#define UV3H_NODE_ID_MANUFACTURER_SHFT			1
2897
-#define UV3H_NODE_ID_PART_NUMBER_SHFT			12
2898
-#define UV3H_NODE_ID_REVISION_SHFT			28
2899
-#define UV3H_NODE_ID_NODE_ID_SHFT			32
2900
-#define UV3H_NODE_ID_ROUTER_SELECT_SHFT			48
2901
-#define UV3H_NODE_ID_RESERVED_2_SHFT			49
2902
-#define UV3H_NODE_ID_NODES_PER_BIT_SHFT			50
2903
-#define UV3H_NODE_ID_NI_PORT_SHFT			57
2904
-#define UV3H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2905
-#define UV3H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2906
-#define UV3H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2907
-#define UV3H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2908
-#define UV3H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2909
-#define UV3H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2910
-#define UV3H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2911
-#define UV3H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2912
-#define UV3H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2913
-
2914
-#define UV4H_NODE_ID_FORCE1_SHFT			0
2915
-#define UV4H_NODE_ID_MANUFACTURER_SHFT			1
2916
-#define UV4H_NODE_ID_PART_NUMBER_SHFT			12
2917
-#define UV4H_NODE_ID_REVISION_SHFT			28
2918
-#define UV4H_NODE_ID_NODE_ID_SHFT			32
2919
-#define UV4H_NODE_ID_ROUTER_SELECT_SHFT			48
2920
-#define UV4H_NODE_ID_RESERVED_2_SHFT			49
2921
-#define UV4H_NODE_ID_NODES_PER_BIT_SHFT			50
2922
-#define UV4H_NODE_ID_NI_PORT_SHFT			57
2923
-#define UV4H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2924
-#define UV4H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2925
-#define UV4H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2926
-#define UV4H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2927
-#define UV4H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2928
-#define UV4H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2929
-#define UV4H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2930
-#define UV4H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2931
-#define UV4H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2932
-
2933
-
2934
-union uvh_node_id_u {
2935
-	unsigned long	v;
2936
-	struct uvh_node_id_s {
2937
-		unsigned long	force1:1;			/* RO */
2938
-		unsigned long	manufacturer:11;		/* RO */
2939
-		unsigned long	part_number:16;			/* RO */
2940
-		unsigned long	revision:4;			/* RO */
2941
-		unsigned long	node_id:15;			/* RW */
2942
-		unsigned long	rsvd_47_63:17;
2943
-	} s;
2944
-	struct uv1h_node_id_s {
2945
-		unsigned long	force1:1;			/* RO */
2946
-		unsigned long	manufacturer:11;		/* RO */
2947
-		unsigned long	part_number:16;			/* RO */
2948
-		unsigned long	revision:4;			/* RO */
2949
-		unsigned long	node_id:15;			/* RW */
2950
-		unsigned long	rsvd_47:1;
2951
-		unsigned long	nodes_per_bit:7;		/* RW */
2952
-		unsigned long	rsvd_55:1;
2953
-		unsigned long	ni_port:4;			/* RO */
2954
-		unsigned long	rsvd_60_63:4;
2955
-	} s1;
2956
-	struct uvxh_node_id_s {
2957
-		unsigned long	force1:1;			/* RO */
2958
-		unsigned long	manufacturer:11;		/* RO */
2959
-		unsigned long	part_number:16;			/* RO */
2960
-		unsigned long	revision:4;			/* RO */
2961
-		unsigned long	node_id:15;			/* RW */
2962
-		unsigned long	rsvd_47_49:3;
2963
-		unsigned long	nodes_per_bit:7;		/* RO */
2964
-		unsigned long	ni_port:5;			/* RO */
2965
-		unsigned long	rsvd_62_63:2;
2966
-	} sx;
2967
-	struct uv2h_node_id_s {
2968
-		unsigned long	force1:1;			/* RO */
2969
-		unsigned long	manufacturer:11;		/* RO */
2970
-		unsigned long	part_number:16;			/* RO */
2971
-		unsigned long	revision:4;			/* RO */
2972
-		unsigned long	node_id:15;			/* RW */
2973
-		unsigned long	rsvd_47_49:3;
2974
-		unsigned long	nodes_per_bit:7;		/* RO */
2975
-		unsigned long	ni_port:5;			/* RO */
2976
-		unsigned long	rsvd_62_63:2;
2977
-	} s2;
2978
-	struct uv3h_node_id_s {
2979
-		unsigned long	force1:1;			/* RO */
2980
-		unsigned long	manufacturer:11;		/* RO */
2981
-		unsigned long	part_number:16;			/* RO */
2982
-		unsigned long	revision:4;			/* RO */
2983
-		unsigned long	node_id:15;			/* RW */
2984
-		unsigned long	rsvd_47:1;
2985
-		unsigned long	router_select:1;		/* RO */
2986
-		unsigned long	rsvd_49:1;
2987
-		unsigned long	nodes_per_bit:7;		/* RO */
2988
-		unsigned long	ni_port:5;			/* RO */
2989
-		unsigned long	rsvd_62_63:2;
2990
-	} s3;
2991
-	struct uv4h_node_id_s {
2992
-		unsigned long	force1:1;			/* RO */
2993
-		unsigned long	manufacturer:11;		/* RO */
2994
-		unsigned long	part_number:16;			/* RO */
2995
-		unsigned long	revision:4;			/* RO */
2996
-		unsigned long	node_id:15;			/* RW */
2997
-		unsigned long	rsvd_47:1;
2998
-		unsigned long	router_select:1;		/* RO */
2999
-		unsigned long	rsvd_49:1;
3000
-		unsigned long	nodes_per_bit:7;		/* RO */
3001
-		unsigned long	ni_port:5;			/* RO */
3002
-		unsigned long	rsvd_62_63:2;
3003
-	} s4;
3004
-};
3005
-
3006
-/* ========================================================================= */
3007
-/*                          UVH_NODE_PRESENT_TABLE                           */
3008
-/* ========================================================================= */
3009
-#define UVH_NODE_PRESENT_TABLE 0x1400UL
3010
-
3011
-#define UV1H_NODE_PRESENT_TABLE_DEPTH 16
3012
-#define UV2H_NODE_PRESENT_TABLE_DEPTH 16
3013
-#define UV3H_NODE_PRESENT_TABLE_DEPTH 16
3014
-#define UV4H_NODE_PRESENT_TABLE_DEPTH 4
3015
-#define UVH_NODE_PRESENT_TABLE_DEPTH (					\
3016
-	is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH :			\
3017
-	is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH :			\
3018
-	is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH :			\
3019
-	/*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH)
3020
-
3021
-#define UVH_NODE_PRESENT_TABLE_NODES_SHFT		0
3022
-#define UVH_NODE_PRESENT_TABLE_NODES_MASK		0xffffffffffffffffUL
3023
-
3024
-
3025
-union uvh_node_present_table_u {
3026
-	unsigned long	v;
3027
-	struct uvh_node_present_table_s {
3028
-		unsigned long	nodes:64;			/* RW */
3029
-	} s;
3030
-};
3031
-
3032
-/* ========================================================================= */
3033
-/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
3034
-/* ========================================================================= */
3035
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3036
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3037
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3038
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL
3039
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR (			\
3040
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3041
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3042
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3043
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR)
3044
-
3045
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3046
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3047
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3048
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3049
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3050
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3051
-
3052
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3053
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3054
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3055
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3056
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3057
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3058
-
3059
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3060
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3061
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3062
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3063
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3064
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3065
-
3066
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3067
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3068
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3069
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3070
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3071
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3072
-
3073
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3074
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3075
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3076
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3077
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3078
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3079
-
3080
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3081
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3082
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3083
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3084
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3085
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3086
-
3087
-
3088
-union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
3089
-	unsigned long	v;
3090
-	struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
3091
-		unsigned long	rsvd_0_23:24;
3092
-		unsigned long	base:8;				/* RW */
3093
-		unsigned long	rsvd_32_47:16;
3094
-		unsigned long	m_alias:5;			/* RW */
3095
-		unsigned long	rsvd_53_62:10;
3096
-		unsigned long	enable:1;			/* RW */
3097
-	} s;
3098
-	struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s {
3099
-		unsigned long	rsvd_0_23:24;
3100
-		unsigned long	base:8;				/* RW */
3101
-		unsigned long	rsvd_32_47:16;
3102
-		unsigned long	m_alias:5;			/* RW */
3103
-		unsigned long	rsvd_53_62:10;
3104
-		unsigned long	enable:1;			/* RW */
3105
-	} s1;
3106
-	struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s {
3107
-		unsigned long	rsvd_0_23:24;
3108
-		unsigned long	base:8;				/* RW */
3109
-		unsigned long	rsvd_32_47:16;
3110
-		unsigned long	m_alias:5;			/* RW */
3111
-		unsigned long	rsvd_53_62:10;
3112
-		unsigned long	enable:1;			/* RW */
3113
-	} sx;
3114
-	struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s {
3115
-		unsigned long	rsvd_0_23:24;
3116
-		unsigned long	base:8;				/* RW */
3117
-		unsigned long	rsvd_32_47:16;
3118
-		unsigned long	m_alias:5;			/* RW */
3119
-		unsigned long	rsvd_53_62:10;
3120
-		unsigned long	enable:1;			/* RW */
3121
-	} s2;
3122
-	struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s {
3123
-		unsigned long	rsvd_0_23:24;
3124
-		unsigned long	base:8;				/* RW */
3125
-		unsigned long	rsvd_32_47:16;
3126
-		unsigned long	m_alias:5;			/* RW */
3127
-		unsigned long	rsvd_53_62:10;
3128
-		unsigned long	enable:1;			/* RW */
3129
-	} s3;
3130
-	struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s {
3131
-		unsigned long	rsvd_0_23:24;
3132
-		unsigned long	base:8;				/* RW */
3133
-		unsigned long	rsvd_32_47:16;
3134
-		unsigned long	m_alias:5;			/* RW */
3135
-		unsigned long	rsvd_53_62:10;
3136
-		unsigned long	enable:1;			/* RW */
3137
-	} s4;
3138
-};
3139
-
3140
-/* ========================================================================= */
3141
-/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
3142
-/* ========================================================================= */
3143
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3144
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3145
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3146
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL
3147
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR (			\
3148
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3149
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3150
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3151
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR)
3152
-
3153
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3154
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3155
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3156
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3157
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3158
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3159
-
3160
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3161
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3162
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3163
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3164
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3165
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3166
-
3167
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3168
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3169
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3170
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3171
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3172
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3173
-
3174
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3175
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3176
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3177
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3178
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3179
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3180
-
3181
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3182
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3183
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3184
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3185
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3186
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3187
-
3188
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3189
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3190
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3191
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3192
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3193
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3194
-
3195
-
3196
-union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
3197
-	unsigned long	v;
3198
-	struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
3199
-		unsigned long	rsvd_0_23:24;
3200
-		unsigned long	base:8;				/* RW */
3201
-		unsigned long	rsvd_32_47:16;
3202
-		unsigned long	m_alias:5;			/* RW */
3203
-		unsigned long	rsvd_53_62:10;
3204
-		unsigned long	enable:1;			/* RW */
3205
-	} s;
3206
-	struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s {
3207
-		unsigned long	rsvd_0_23:24;
3208
-		unsigned long	base:8;				/* RW */
3209
-		unsigned long	rsvd_32_47:16;
3210
-		unsigned long	m_alias:5;			/* RW */
3211
-		unsigned long	rsvd_53_62:10;
3212
-		unsigned long	enable:1;			/* RW */
3213
-	} s1;
3214
-	struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s {
3215
-		unsigned long	rsvd_0_23:24;
3216
-		unsigned long	base:8;				/* RW */
3217
-		unsigned long	rsvd_32_47:16;
3218
-		unsigned long	m_alias:5;			/* RW */
3219
-		unsigned long	rsvd_53_62:10;
3220
-		unsigned long	enable:1;			/* RW */
3221
-	} sx;
3222
-	struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s {
3223
-		unsigned long	rsvd_0_23:24;
3224
-		unsigned long	base:8;				/* RW */
3225
-		unsigned long	rsvd_32_47:16;
3226
-		unsigned long	m_alias:5;			/* RW */
3227
-		unsigned long	rsvd_53_62:10;
3228
-		unsigned long	enable:1;			/* RW */
3229
-	} s2;
3230
-	struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s {
3231
-		unsigned long	rsvd_0_23:24;
3232
-		unsigned long	base:8;				/* RW */
3233
-		unsigned long	rsvd_32_47:16;
3234
-		unsigned long	m_alias:5;			/* RW */
3235
-		unsigned long	rsvd_53_62:10;
3236
-		unsigned long	enable:1;			/* RW */
3237
-	} s3;
3238
-	struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s {
3239
-		unsigned long	rsvd_0_23:24;
3240
-		unsigned long	base:8;				/* RW */
3241
-		unsigned long	rsvd_32_47:16;
3242
-		unsigned long	m_alias:5;			/* RW */
3243
-		unsigned long	rsvd_53_62:10;
3244
-		unsigned long	enable:1;			/* RW */
3245
-	} s4;
3246
-};
3247
-
3248
-/* ========================================================================= */
3249
-/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
3250
-/* ========================================================================= */
3251
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3252
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3253
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3254
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL
3255
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR (			\
3256
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3257
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3258
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3259
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR)
3260
-
3261
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3262
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3263
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3264
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3265
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3266
-#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3267
-
3268
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3269
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3270
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3271
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3272
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3273
-#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3274
-
3275
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3276
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3277
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3278
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3279
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3280
-#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3281
-
3282
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3283
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3284
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3285
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3286
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3287
-#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3288
-
3289
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3290
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3291
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3292
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3293
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3294
-#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3295
-
3296
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3297
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3298
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3299
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3300
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3301
-#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3302
-
3303
-
3304
-union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
3305
-	unsigned long	v;
3306
-	struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
3307
-		unsigned long	rsvd_0_23:24;
3308
-		unsigned long	base:8;				/* RW */
3309
-		unsigned long	rsvd_32_47:16;
3310
-		unsigned long	m_alias:5;			/* RW */
3311
-		unsigned long	rsvd_53_62:10;
3312
-		unsigned long	enable:1;			/* RW */
3313
-	} s;
3314
-	struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s {
3315
-		unsigned long	rsvd_0_23:24;
3316
-		unsigned long	base:8;				/* RW */
3317
-		unsigned long	rsvd_32_47:16;
3318
-		unsigned long	m_alias:5;			/* RW */
3319
-		unsigned long	rsvd_53_62:10;
3320
-		unsigned long	enable:1;			/* RW */
3321
-	} s1;
3322
-	struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s {
3323
-		unsigned long	rsvd_0_23:24;
3324
-		unsigned long	base:8;				/* RW */
3325
-		unsigned long	rsvd_32_47:16;
3326
-		unsigned long	m_alias:5;			/* RW */
3327
-		unsigned long	rsvd_53_62:10;
3328
-		unsigned long	enable:1;			/* RW */
3329
-	} sx;
3330
-	struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s {
3331
-		unsigned long	rsvd_0_23:24;
3332
-		unsigned long	base:8;				/* RW */
3333
-		unsigned long	rsvd_32_47:16;
3334
-		unsigned long	m_alias:5;			/* RW */
3335
-		unsigned long	rsvd_53_62:10;
3336
-		unsigned long	enable:1;			/* RW */
3337
-	} s2;
3338
-	struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s {
3339
-		unsigned long	rsvd_0_23:24;
3340
-		unsigned long	base:8;				/* RW */
3341
-		unsigned long	rsvd_32_47:16;
3342
-		unsigned long	m_alias:5;			/* RW */
3343
-		unsigned long	rsvd_53_62:10;
3344
-		unsigned long	enable:1;			/* RW */
3345
-	} s3;
3346
-	struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s {
3347
-		unsigned long	rsvd_0_23:24;
3348
-		unsigned long	base:8;				/* RW */
3349
-		unsigned long	rsvd_32_47:16;
3350
-		unsigned long	m_alias:5;			/* RW */
3351
-		unsigned long	rsvd_53_62:10;
3352
-		unsigned long	enable:1;			/* RW */
3353
-	} s4;
3354
-};
3355
-
3356
-/* ========================================================================= */
3357
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
3358
-/* ========================================================================= */
3359
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3360
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3361
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3362
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL
3363
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR (			\
3364
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3365
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3366
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3367
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR)
3368
-
3369
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3370
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3371
-
3372
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3373
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3374
-
3375
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3376
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3377
-
3378
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3379
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3380
-
3381
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3382
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3383
-
3384
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3385
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3386
-
3387
-
3388
-union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
3389
-	unsigned long	v;
3390
-	struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
3391
-		unsigned long	rsvd_0_23:24;
3392
-		unsigned long	dest_base:22;			/* RW */
3393
-		unsigned long	rsvd_46_63:18;
3394
-	} s;
3395
-	struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s {
3396
-		unsigned long	rsvd_0_23:24;
3397
-		unsigned long	dest_base:22;			/* RW */
3398
-		unsigned long	rsvd_46_63:18;
3399
-	} s1;
3400
-	struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s {
3401
-		unsigned long	rsvd_0_23:24;
3402
-		unsigned long	dest_base:22;			/* RW */
3403
-		unsigned long	rsvd_46_63:18;
3404
-	} sx;
3405
-	struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s {
3406
-		unsigned long	rsvd_0_23:24;
3407
-		unsigned long	dest_base:22;			/* RW */
3408
-		unsigned long	rsvd_46_63:18;
3409
-	} s2;
3410
-	struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s {
3411
-		unsigned long	rsvd_0_23:24;
3412
-		unsigned long	dest_base:22;			/* RW */
3413
-		unsigned long	rsvd_46_63:18;
3414
-	} s3;
3415
-	struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s {
3416
-		unsigned long	rsvd_0_23:24;
3417
-		unsigned long	dest_base:22;			/* RW */
3418
-		unsigned long	rsvd_46_63:18;
3419
-	} s4;
3420
-};
3421
-
3422
-/* ========================================================================= */
3423
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
3424
-/* ========================================================================= */
3425
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3426
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3427
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3428
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL
3429
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR (			\
3430
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3431
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3432
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3433
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR)
3434
-
3435
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3436
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3437
-
3438
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3439
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3440
-
3441
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3442
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3443
-
3444
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3445
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3446
-
3447
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3448
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3449
-
3450
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3451
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3452
-
3453
-
3454
-union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
3455
-	unsigned long	v;
3456
-	struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
3457
-		unsigned long	rsvd_0_23:24;
3458
-		unsigned long	dest_base:22;			/* RW */
3459
-		unsigned long	rsvd_46_63:18;
3460
-	} s;
3461
-	struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s {
3462
-		unsigned long	rsvd_0_23:24;
3463
-		unsigned long	dest_base:22;			/* RW */
3464
-		unsigned long	rsvd_46_63:18;
3465
-	} s1;
3466
-	struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s {
3467
-		unsigned long	rsvd_0_23:24;
3468
-		unsigned long	dest_base:22;			/* RW */
3469
-		unsigned long	rsvd_46_63:18;
3470
-	} sx;
3471
-	struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s {
3472
-		unsigned long	rsvd_0_23:24;
3473
-		unsigned long	dest_base:22;			/* RW */
3474
-		unsigned long	rsvd_46_63:18;
3475
-	} s2;
3476
-	struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s {
3477
-		unsigned long	rsvd_0_23:24;
3478
-		unsigned long	dest_base:22;			/* RW */
3479
-		unsigned long	rsvd_46_63:18;
3480
-	} s3;
3481
-	struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s {
3482
-		unsigned long	rsvd_0_23:24;
3483
-		unsigned long	dest_base:22;			/* RW */
3484
-		unsigned long	rsvd_46_63:18;
3485
-	} s4;
3486
-};
3487
-
3488
-/* ========================================================================= */
3489
-/*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
3490
-/* ========================================================================= */
3491
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3492
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3493
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3494
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL
3495
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR (			\
3496
-	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3497
-	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3498
-	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3499
-	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR)
3500
-
3501
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3502
-#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3503
-
3504
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3505
-#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3506
-
3507
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3508
-#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3509
-
3510
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3511
-#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3512
-
3513
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3514
-#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3515
-
3516
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3517
-#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3518
-
3519
-
3520
-union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
3521
-	unsigned long	v;
3522
-	struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
3523
-		unsigned long	rsvd_0_23:24;
3524
-		unsigned long	dest_base:22;			/* RW */
3525
-		unsigned long	rsvd_46_63:18;
3526
-	} s;
3527
-	struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s {
3528
-		unsigned long	rsvd_0_23:24;
3529
-		unsigned long	dest_base:22;			/* RW */
3530
-		unsigned long	rsvd_46_63:18;
3531
-	} s1;
3532
-	struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s {
3533
-		unsigned long	rsvd_0_23:24;
3534
-		unsigned long	dest_base:22;			/* RW */
3535
-		unsigned long	rsvd_46_63:18;
3536
-	} sx;
3537
-	struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s {
3538
-		unsigned long	rsvd_0_23:24;
3539
-		unsigned long	dest_base:22;			/* RW */
3540
-		unsigned long	rsvd_46_63:18;
3541
-	} s2;
3542
-	struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s {
3543
-		unsigned long	rsvd_0_23:24;
3544
-		unsigned long	dest_base:22;			/* RW */
3545
-		unsigned long	rsvd_46_63:18;
3546
-	} s3;
3547
-	struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s {
3548
-		unsigned long	rsvd_0_23:24;
3549
-		unsigned long	dest_base:22;			/* RW */
3550
-		unsigned long	rsvd_46_63:18;
3551
-	} s4;
3552
-};
3553
-
3554
-/* ========================================================================= */
3555
-/*                          UVH_RH_GAM_CONFIG_MMR                            */
3556
-/* ========================================================================= */
3557
-#define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
3558
-#define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
3559
-#define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
3560
-#define UV4H_RH_GAM_CONFIG_MMR 0x480000UL
3561
-#define UVH_RH_GAM_CONFIG_MMR (						\
3562
-	is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR :				\
3563
-	is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR :				\
3564
-	is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR :				\
3565
-	/*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR)
3566
-
3567
-#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3568
-#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3569
-
3570
-#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3571
-#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3572
-#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT		12
3573
-#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3574
-#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3575
-#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK		0x0000000000001000UL
3576
-
3577
-#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3578
-#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3579
-
3580
-#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3581
-#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3582
-#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3583
-#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3584
-
3585
-#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3586
-#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3587
-#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3588
-#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3589
-
3590
-#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3591
-#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3592
-
3593
-
3594
-union uvh_rh_gam_config_mmr_u {
3595
-	unsigned long	v;
3596
-	struct uvh_rh_gam_config_mmr_s {
3597
-		unsigned long	rsvd_0_5:6;
3598
-		unsigned long	n_skt:4;			/* RW */
3599
-		unsigned long	rsvd_10_63:54;
3600
-	} s;
3601
-	struct uv1h_rh_gam_config_mmr_s {
3602
-		unsigned long	m_skt:6;			/* RW */
3603
-		unsigned long	n_skt:4;			/* RW */
3604
-		unsigned long	rsvd_10_11:2;
3605
-		unsigned long	mmiol_cfg:1;			/* RW */
3606
-		unsigned long	rsvd_13_63:51;
3607
-	} s1;
3608
-	struct uvxh_rh_gam_config_mmr_s {
3609
-		unsigned long	rsvd_0_5:6;
3610
-		unsigned long	n_skt:4;			/* RW */
3611
-		unsigned long	rsvd_10_63:54;
3612
-	} sx;
3613
-	struct uv2h_rh_gam_config_mmr_s {
3614
-		unsigned long	m_skt:6;			/* RW */
3615
-		unsigned long	n_skt:4;			/* RW */
3616
-		unsigned long	rsvd_10_63:54;
3617
-	} s2;
3618
-	struct uv3h_rh_gam_config_mmr_s {
3619
-		unsigned long	m_skt:6;			/* RW */
3620
-		unsigned long	n_skt:4;			/* RW */
3621
-		unsigned long	rsvd_10_63:54;
3622
-	} s3;
3623
-	struct uv4h_rh_gam_config_mmr_s {
3624
-		unsigned long	rsvd_0_5:6;
3625
-		unsigned long	n_skt:4;			/* RW */
3626
-		unsigned long	rsvd_10_63:54;
3627
-	} s4;
3628
-};
3629
-
3630
-/* ========================================================================= */
3631
-/*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
3632
-/* ========================================================================= */
3633
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3634
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3635
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3636
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL
3637
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR (				\
3638
-	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3639
-	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3640
-	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3641
-	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR)
3642
-
3643
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3644
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3645
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3646
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3647
-
3648
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3649
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT	48
3650
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3651
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3652
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3653
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK	0x0001000000000000UL
3654
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3655
-#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3656
-
3657
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3658
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3659
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3660
-#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3661
-
3662
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3663
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3664
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3665
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3666
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3667
-#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3668
-
3669
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3670
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3671
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT	62
3672
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3673
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3674
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3675
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK	0x4000000000000000UL
3676
-#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3677
-
3678
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	26
3679
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3680
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3681
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
3682
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3683
-#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3684
-
3685
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK (			\
3686
-	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3687
-	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3688
-	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3689
-	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK)
3690
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT (			\
3691
-	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3692
-	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3693
-	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3694
-	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT)
3695
-
3696
-union uvh_rh_gam_gru_overlay_config_mmr_u {
3697
-	unsigned long	v;
3698
-	struct uvh_rh_gam_gru_overlay_config_mmr_s {
3699
-		unsigned long	rsvd_0_51:52;
3700
-		unsigned long	n_gru:4;			/* RW */
3701
-		unsigned long	rsvd_56_62:7;
3702
-		unsigned long	enable:1;			/* RW */
3703
-	} s;
3704
-	struct uv1h_rh_gam_gru_overlay_config_mmr_s {
3705
-		unsigned long	rsvd_0_27:28;
3706
-		unsigned long	base:18;			/* RW */
3707
-		unsigned long	rsvd_46_47:2;
3708
-		unsigned long	gr4:1;				/* RW */
3709
-		unsigned long	rsvd_49_51:3;
3710
-		unsigned long	n_gru:4;			/* RW */
3711
-		unsigned long	rsvd_56_62:7;
3712
-		unsigned long	enable:1;			/* RW */
3713
-	} s1;
3714
-	struct uvxh_rh_gam_gru_overlay_config_mmr_s {
3715
-		unsigned long	rsvd_0_45:46;
3716
-		unsigned long	rsvd_46_51:6;
3717
-		unsigned long	n_gru:4;			/* RW */
3718
-		unsigned long	rsvd_56_62:7;
3719
-		unsigned long	enable:1;			/* RW */
3720
-	} sx;
3721
-	struct uv2h_rh_gam_gru_overlay_config_mmr_s {
3722
-		unsigned long	rsvd_0_27:28;
3723
-		unsigned long	base:18;			/* RW */
3724
-		unsigned long	rsvd_46_51:6;
3725
-		unsigned long	n_gru:4;			/* RW */
3726
-		unsigned long	rsvd_56_62:7;
3727
-		unsigned long	enable:1;			/* RW */
3728
-	} s2;
3729
-	struct uv3h_rh_gam_gru_overlay_config_mmr_s {
3730
-		unsigned long	rsvd_0_27:28;
3731
-		unsigned long	base:18;			/* RW */
3732
-		unsigned long	rsvd_46_51:6;
3733
-		unsigned long	n_gru:4;			/* RW */
3734
-		unsigned long	rsvd_56_61:6;
3735
-		unsigned long	mode:1;				/* RW */
3736
-		unsigned long	enable:1;			/* RW */
3737
-	} s3;
3738
-	struct uv4h_rh_gam_gru_overlay_config_mmr_s {
3739
-		unsigned long	rsvd_0_24:25;
3740
-		unsigned long	undef_25:1;			/* Undefined */
3741
-		unsigned long	base:20;			/* RW */
3742
-		unsigned long	rsvd_46_51:6;
3743
-		unsigned long	n_gru:4;			/* RW */
3744
-		unsigned long	rsvd_56_62:7;
3745
-		unsigned long	enable:1;			/* RW */
3746
-	} s4;
3747
-};
3748
-
3749
-/* ========================================================================= */
3750
-/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                    */
3751
-/* ========================================================================= */
3752
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3753
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3754
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
3755
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL
3756
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR (				\
3757
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3758
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3759
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3760
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR)
3761
-
3762
-
3763
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT	26
3764
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT	46
3765
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3766
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK	0x00003ffffc000000UL
3767
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK	0x000fc00000000000UL
3768
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3769
-
3770
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT	26
3771
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT	46
3772
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3773
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK	0x00003ffffc000000UL
3774
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK	0x000fc00000000000UL
3775
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3776
-
3777
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 52
3778
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x000ffffffc000000UL
3779
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x03f0000000000000UL
3780
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3781
-
3782
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT (		\
3783
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3784
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3785
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT)
3786
-
3787
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK (		\
3788
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3789
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3790
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK)
3791
-
3792
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK (		\
3793
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3794
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3795
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
3796
-
3797
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK (		\
3798
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3799
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3800
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)
3801
-
3802
-union uvh_rh_gam_mmioh_overlay_config0_mmr_u {
3803
-	unsigned long	v;
3804
-	struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
3805
-		unsigned long	rsvd_0_25:26;
3806
-		unsigned long	base:20;			/* RW */
3807
-		unsigned long	m_io:6;				/* RW */
3808
-		unsigned long	n_io:4;
3809
-		unsigned long	rsvd_56_62:7;
3810
-		unsigned long	enable:1;			/* RW */
3811
-	} s3;
3812
-	struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s {
3813
-		unsigned long	rsvd_0_25:26;
3814
-		unsigned long	base:20;			/* RW */
3815
-		unsigned long	m_io:6;				/* RW */
3816
-		unsigned long	n_io:4;
3817
-		unsigned long	rsvd_56_62:7;
3818
-		unsigned long	enable:1;			/* RW */
3819
-	} s4;
3820
-	struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s {
3821
-		unsigned long	rsvd_0_25:26;
3822
-		unsigned long	base:26;			/* RW */
3823
-		unsigned long	m_io:6;				/* RW */
3824
-		unsigned long	n_io:4;
3825
-		unsigned long	undef_62:1;			/* Undefined */
3826
-		unsigned long	enable:1;			/* RW */
3827
-	} s4a;
3828
-};
3829
-
3830
-/* ========================================================================= */
3831
-/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR                    */
3832
-/* ========================================================================= */
3833
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3834
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3835
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1603000UL
3836
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL
3837
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR (				\
3838
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3839
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3840
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3841
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR)
3842
-
3843
-
3844
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT	26
3845
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT	46
3846
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3847
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK	0x00003ffffc000000UL
3848
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK	0x000fc00000000000UL
3849
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3850
-
3851
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT	26
3852
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT	46
3853
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3854
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK	0x00003ffffc000000UL
3855
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK	0x000fc00000000000UL
3856
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3857
-
3858
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 52
3859
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x000ffffffc000000UL
3860
-#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x03f0000000000000UL
3861
-
3862
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT (		\
3863
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3864
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3865
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT)
3866
-
3867
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK (		\
3868
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3869
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3870
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK)
3871
-
3872
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK (		\
3873
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3874
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3875
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
3876
-
3877
-union uvh_rh_gam_mmioh_overlay_config1_mmr_u {
3878
-	unsigned long	v;
3879
-	struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
3880
-		unsigned long	rsvd_0_25:26;
3881
-		unsigned long	base:20;			/* RW */
3882
-		unsigned long	m_io:6;				/* RW */
3883
-		unsigned long	n_io:4;
3884
-		unsigned long	rsvd_56_62:7;
3885
-		unsigned long	enable:1;			/* RW */
3886
-	} s3;
3887
-	struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s {
3888
-		unsigned long	rsvd_0_25:26;
3889
-		unsigned long	base:20;			/* RW */
3890
-		unsigned long	m_io:6;				/* RW */
3891
-		unsigned long	n_io:4;
3892
-		unsigned long	rsvd_56_62:7;
3893
-		unsigned long	enable:1;			/* RW */
3894
-	} s4;
3895
-	struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s {
3896
-		unsigned long	rsvd_0_25:26;
3897
-		unsigned long	base:26;			/* RW */
3898
-		unsigned long	m_io:6;				/* RW */
3899
-		unsigned long	n_io:4;
3900
-		unsigned long	undef_62:1;			/* Undefined */
3901
-		unsigned long	enable:1;			/* RW */
3902
-	} s4a;
3903
-};
3904
-
3905
-/* ========================================================================= */
3906
-/*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
3907
-/* ========================================================================= */
3908
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3909
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3910
-#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3911
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3912
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR (				\
3913
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3914
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3915
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3916
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
3917
-
3918
-
3919
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	30
3920
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
3921
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
3922
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3923
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003fffc0000000UL
3924
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
3925
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
3926
-#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3927
-
3928
-
3929
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	27
3930
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
3931
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
3932
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3933
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff8000000UL
3934
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
3935
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
3936
-#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3937
-
3938
-
3939
-union uvh_rh_gam_mmioh_overlay_config_mmr_u {
3940
-	unsigned long	v;
3941
-	struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
3942
-		unsigned long	rsvd_0_29:30;
3943
-		unsigned long	base:16;			/* RW */
3944
-		unsigned long	m_io:6;				/* RW */
3945
-		unsigned long	n_io:4;				/* RW */
3946
-		unsigned long	rsvd_56_62:7;
3947
-		unsigned long	enable:1;			/* RW */
3948
-	} s1;
3949
-	struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
3950
-		unsigned long	rsvd_0_26:27;
3951
-		unsigned long	base:19;			/* RW */
3952
-		unsigned long	m_io:6;				/* RW */
3953
-		unsigned long	n_io:4;				/* RW */
3954
-		unsigned long	rsvd_56_62:7;
3955
-		unsigned long	enable:1;			/* RW */
39561583 	} s2;
39571584 };
39581585 
39591586 /* ========================================================================= */
3960
-/*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR                    */
1587
+/*                        UVH_EVENT_OCCURRED1_ALIAS                          */
39611588 /* ========================================================================= */
3962
-#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3963
-#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3964
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL
3965
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL
3966
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR (				\
3967
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3968
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3969
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3970
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR)
3971
-
3972
-#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3973
-#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3974
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3975
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3976
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH (			\
3977
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3978
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3979
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3980
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH)
3981
-
3982
-
3983
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3984
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3985
-
3986
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3987
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3988
-
3989
-#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000000fffUL
3990
-
3991
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK (		\
3992
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3993
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3994
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK)
3995
-
3996
-union uvh_rh_gam_mmioh_redirect_config0_mmr_u {
3997
-	unsigned long	v;
3998
-	struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
3999
-		unsigned long	nasid:15;			/* RW */
4000
-		unsigned long	rsvd_15_63:49;
4001
-	} s3;
4002
-	struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s {
4003
-		unsigned long	nasid:15;			/* RW */
4004
-		unsigned long	rsvd_15_63:49;
4005
-	} s4;
4006
-	struct uv4ah_rh_gam_mmioh_redirect_config0_mmr_s {
4007
-		unsigned long	nasid:12;			/* RW */
4008
-		unsigned long	rsvd_12_63:52;
4009
-	} s4a;
4010
-};
4011
-
4012
-/* ========================================================================= */
4013
-/*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR                    */
4014
-/* ========================================================================= */
4015
-#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4016
-#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4017
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL
4018
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL
4019
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR (				\
4020
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4021
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4022
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4023
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR)
4024
-
4025
-#define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4026
-#define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4027
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4028
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4029
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH (			\
4030
-	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4031
-	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4032
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4033
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH)
4034
-
4035
-
4036
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4037
-#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4038
-
4039
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4040
-#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4041
-
4042
-#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000000fffUL
4043
-
4044
-#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK (		\
4045
-	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4046
-	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4047
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK)
4048
-
4049
-union uvh_rh_gam_mmioh_redirect_config1_mmr_u {
4050
-	unsigned long	v;
4051
-	struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
4052
-		unsigned long	nasid:15;			/* RW */
4053
-		unsigned long	rsvd_15_63:49;
4054
-	} s3;
4055
-	struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s {
4056
-		unsigned long	nasid:15;			/* RW */
4057
-		unsigned long	rsvd_15_63:49;
4058
-	} s4;
4059
-	struct uv4ah_rh_gam_mmioh_redirect_config1_mmr_s {
4060
-		unsigned long	nasid:12;			/* RW */
4061
-		unsigned long	rsvd_12_63:52;
4062
-	} s4a;
4063
-};
4064
-
4065
-/* ========================================================================= */
4066
-/*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
4067
-/* ========================================================================= */
4068
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4069
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4070
-#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4071
-#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL
4072
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR (				\
4073
-	is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4074
-	is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4075
-	is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4076
-	/*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR)
4077
-
4078
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4079
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4080
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4081
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4082
-
4083
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4084
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
4085
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4086
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4087
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
4088
-#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4089
-
4090
-#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4091
-#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4092
-#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4093
-#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4094
-
4095
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4096
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4097
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4098
-#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4099
-
4100
-#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4101
-#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4102
-#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4103
-#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4104
-
4105
-#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4106
-#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4107
-#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4108
-#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4109
-
4110
-
4111
-union uvh_rh_gam_mmr_overlay_config_mmr_u {
4112
-	unsigned long	v;
4113
-	struct uvh_rh_gam_mmr_overlay_config_mmr_s {
4114
-		unsigned long	rsvd_0_25:26;
4115
-		unsigned long	base:20;			/* RW */
4116
-		unsigned long	rsvd_46_62:17;
4117
-		unsigned long	enable:1;			/* RW */
4118
-	} s;
4119
-	struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
4120
-		unsigned long	rsvd_0_25:26;
4121
-		unsigned long	base:20;			/* RW */
4122
-		unsigned long	dual_hub:1;			/* RW */
4123
-		unsigned long	rsvd_47_62:16;
4124
-		unsigned long	enable:1;			/* RW */
4125
-	} s1;
4126
-	struct uvxh_rh_gam_mmr_overlay_config_mmr_s {
4127
-		unsigned long	rsvd_0_25:26;
4128
-		unsigned long	base:20;			/* RW */
4129
-		unsigned long	rsvd_46_62:17;
4130
-		unsigned long	enable:1;			/* RW */
4131
-	} sx;
4132
-	struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
4133
-		unsigned long	rsvd_0_25:26;
4134
-		unsigned long	base:20;			/* RW */
4135
-		unsigned long	rsvd_46_62:17;
4136
-		unsigned long	enable:1;			/* RW */
4137
-	} s2;
4138
-	struct uv3h_rh_gam_mmr_overlay_config_mmr_s {
4139
-		unsigned long	rsvd_0_25:26;
4140
-		unsigned long	base:20;			/* RW */
4141
-		unsigned long	rsvd_46_62:17;
4142
-		unsigned long	enable:1;			/* RW */
4143
-	} s3;
4144
-	struct uv4h_rh_gam_mmr_overlay_config_mmr_s {
4145
-		unsigned long	rsvd_0_25:26;
4146
-		unsigned long	base:20;			/* RW */
4147
-		unsigned long	rsvd_46_62:17;
4148
-		unsigned long	enable:1;			/* RW */
4149
-	} s4;
4150
-};
4151
-
4152
-/* ========================================================================= */
4153
-/*                                 UVH_RTC                                   */
4154
-/* ========================================================================= */
4155
-#define UV1H_RTC 0x340000UL
4156
-#define UV2H_RTC 0x340000UL
4157
-#define UV3H_RTC 0x340000UL
4158
-#define UV4H_RTC 0xe0000UL
4159
-#define UVH_RTC (							\
4160
-	is_uv1_hub() ? UV1H_RTC :					\
4161
-	is_uv2_hub() ? UV2H_RTC :					\
4162
-	is_uv3_hub() ? UV3H_RTC :					\
4163
-	/*is_uv4_hub*/ UV4H_RTC)
4164
-
4165
-#define UVH_RTC_REAL_TIME_CLOCK_SHFT			0
4166
-#define UVH_RTC_REAL_TIME_CLOCK_MASK			0x00ffffffffffffffUL
4167
-
4168
-
4169
-union uvh_rtc_u {
4170
-	unsigned long	v;
4171
-	struct uvh_rtc_s {
4172
-		unsigned long	real_time_clock:56;		/* RW */
4173
-		unsigned long	rsvd_56_63:8;
4174
-	} s;
4175
-};
4176
-
4177
-/* ========================================================================= */
4178
-/*                           UVH_RTC1_INT_CONFIG                             */
4179
-/* ========================================================================= */
4180
-#define UVH_RTC1_INT_CONFIG 0x615c0UL
4181
-
4182
-#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT			0
4183
-#define UVH_RTC1_INT_CONFIG_DM_SHFT			8
4184
-#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT		11
4185
-#define UVH_RTC1_INT_CONFIG_STATUS_SHFT			12
4186
-#define UVH_RTC1_INT_CONFIG_P_SHFT			13
4187
-#define UVH_RTC1_INT_CONFIG_T_SHFT			15
4188
-#define UVH_RTC1_INT_CONFIG_M_SHFT			16
4189
-#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT		32
4190
-#define UVH_RTC1_INT_CONFIG_VECTOR_MASK			0x00000000000000ffUL
4191
-#define UVH_RTC1_INT_CONFIG_DM_MASK			0x0000000000000700UL
4192
-#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK		0x0000000000000800UL
4193
-#define UVH_RTC1_INT_CONFIG_STATUS_MASK			0x0000000000001000UL
4194
-#define UVH_RTC1_INT_CONFIG_P_MASK			0x0000000000002000UL
4195
-#define UVH_RTC1_INT_CONFIG_T_MASK			0x0000000000008000UL
4196
-#define UVH_RTC1_INT_CONFIG_M_MASK			0x0000000000010000UL
4197
-#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
4198
-
4199
-
4200
-union uvh_rtc1_int_config_u {
4201
-	unsigned long	v;
4202
-	struct uvh_rtc1_int_config_s {
4203
-		unsigned long	vector_:8;			/* RW */
4204
-		unsigned long	dm:3;				/* RW */
4205
-		unsigned long	destmode:1;			/* RW */
4206
-		unsigned long	status:1;			/* RO */
4207
-		unsigned long	p:1;				/* RO */
4208
-		unsigned long	rsvd_14:1;
4209
-		unsigned long	t:1;				/* RO */
4210
-		unsigned long	m:1;				/* RW */
4211
-		unsigned long	rsvd_17_31:15;
4212
-		unsigned long	apic_id:32;			/* RW */
4213
-	} s;
4214
-};
4215
-
4216
-/* ========================================================================= */
4217
-/*                               UVH_SCRATCH5                                */
4218
-/* ========================================================================= */
4219
-#define UV1H_SCRATCH5 0x2d0200UL
4220
-#define UV2H_SCRATCH5 0x2d0200UL
4221
-#define UV3H_SCRATCH5 0x2d0200UL
4222
-#define UV4H_SCRATCH5 0xb0200UL
4223
-#define UVH_SCRATCH5 (							\
4224
-	is_uv1_hub() ? UV1H_SCRATCH5 :					\
4225
-	is_uv2_hub() ? UV2H_SCRATCH5 :					\
4226
-	is_uv3_hub() ? UV3H_SCRATCH5 :					\
4227
-	/*is_uv4_hub*/ UV4H_SCRATCH5)
4228
-
4229
-#define UV1H_SCRATCH5_32 0x778
4230
-#define UV2H_SCRATCH5_32 0x778
4231
-#define UV3H_SCRATCH5_32 0x778
4232
-#define UV4H_SCRATCH5_32 0x798
4233
-#define UVH_SCRATCH5_32 (						\
4234
-	is_uv1_hub() ? UV1H_SCRATCH5_32 :				\
4235
-	is_uv2_hub() ? UV2H_SCRATCH5_32 :				\
4236
-	is_uv3_hub() ? UV3H_SCRATCH5_32 :				\
4237
-	/*is_uv4_hub*/ UV4H_SCRATCH5_32)
4238
-
4239
-#define UVH_SCRATCH5_SCRATCH5_SHFT			0
4240
-#define UVH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4241
-
4242
-
4243
-union uvh_scratch5_u {
4244
-	unsigned long	v;
4245
-	struct uvh_scratch5_s {
4246
-		unsigned long	scratch5:64;			/* RW, W1CS */
4247
-	} s;
4248
-};
4249
-
4250
-/* ========================================================================= */
4251
-/*                            UVH_SCRATCH5_ALIAS                             */
4252
-/* ========================================================================= */
4253
-#define UV1H_SCRATCH5_ALIAS 0x2d0208UL
4254
-#define UV2H_SCRATCH5_ALIAS 0x2d0208UL
4255
-#define UV3H_SCRATCH5_ALIAS 0x2d0208UL
4256
-#define UV4H_SCRATCH5_ALIAS 0xb0208UL
4257
-#define UVH_SCRATCH5_ALIAS (						\
4258
-	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS :				\
4259
-	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS :				\
4260
-	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS :				\
4261
-	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS)
4262
-
4263
-#define UV1H_SCRATCH5_ALIAS_32 0x780
4264
-#define UV2H_SCRATCH5_ALIAS_32 0x780
4265
-#define UV3H_SCRATCH5_ALIAS_32 0x780
4266
-#define UV4H_SCRATCH5_ALIAS_32 0x7a0
4267
-#define UVH_SCRATCH5_ALIAS_32 (						\
4268
-	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 :				\
4269
-	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 :				\
4270
-	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 :				\
4271
-	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32)
1589
+#define UVH_EVENT_OCCURRED1_ALIAS 0x70088UL
42721590 
42731591 
42741592 /* ========================================================================= */
4275
-/*                           UVH_SCRATCH5_ALIAS_2                            */
1593
+/*                           UVH_EVENT_OCCURRED2                             */
42761594 /* ========================================================================= */
4277
-#define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL
4278
-#define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
4279
-#define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
4280
-#define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
4281
-#define UVH_SCRATCH5_ALIAS_2 (						\
4282
-	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 :				\
4283
-	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 :				\
4284
-	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 :				\
4285
-	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2)
4286
-#define UVH_SCRATCH5_ALIAS_2_32 0x788
1595
+#define UVH_EVENT_OCCURRED2 0x70100UL
42871596 
42881597 
4289
-/* ========================================================================= */
4290
-/*                          UVXH_EVENT_OCCURRED2                             */
4291
-/* ========================================================================= */
4292
-#define UVXH_EVENT_OCCURRED2 0x70100UL
42931598 
4294
-#define UV2H_EVENT_OCCURRED2_32 0xb68
4295
-#define UV3H_EVENT_OCCURRED2_32 0xb68
4296
-#define UV4H_EVENT_OCCURRED2_32 0x608
4297
-#define UVH_EVENT_OCCURRED2_32 (					\
4298
-	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 :			\
4299
-	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 :			\
4300
-	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32)
1599
+/* UVYH common defines */
1600
+#define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT	0
1601
+#define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK	0x0000000000000001UL
1602
+#define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT	1
1603
+#define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK	0x0000000000000002UL
1604
+#define UVYH_EVENT_OCCURRED2_RTC_0_SHFT			2
1605
+#define UVYH_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000004UL
1606
+#define UVYH_EVENT_OCCURRED2_RTC_1_SHFT			3
1607
+#define UVYH_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000008UL
1608
+#define UVYH_EVENT_OCCURRED2_RTC_2_SHFT			4
1609
+#define UVYH_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000010UL
1610
+#define UVYH_EVENT_OCCURRED2_RTC_3_SHFT			5
1611
+#define UVYH_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000020UL
1612
+#define UVYH_EVENT_OCCURRED2_RTC_4_SHFT			6
1613
+#define UVYH_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000040UL
1614
+#define UVYH_EVENT_OCCURRED2_RTC_5_SHFT			7
1615
+#define UVYH_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000080UL
1616
+#define UVYH_EVENT_OCCURRED2_RTC_6_SHFT			8
1617
+#define UVYH_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000100UL
1618
+#define UVYH_EVENT_OCCURRED2_RTC_7_SHFT			9
1619
+#define UVYH_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000200UL
1620
+#define UVYH_EVENT_OCCURRED2_RTC_8_SHFT			10
1621
+#define UVYH_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000400UL
1622
+#define UVYH_EVENT_OCCURRED2_RTC_9_SHFT			11
1623
+#define UVYH_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000800UL
1624
+#define UVYH_EVENT_OCCURRED2_RTC_10_SHFT		12
1625
+#define UVYH_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000001000UL
1626
+#define UVYH_EVENT_OCCURRED2_RTC_11_SHFT		13
1627
+#define UVYH_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000002000UL
1628
+#define UVYH_EVENT_OCCURRED2_RTC_12_SHFT		14
1629
+#define UVYH_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000004000UL
1630
+#define UVYH_EVENT_OCCURRED2_RTC_13_SHFT		15
1631
+#define UVYH_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000008000UL
1632
+#define UVYH_EVENT_OCCURRED2_RTC_14_SHFT		16
1633
+#define UVYH_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000010000UL
1634
+#define UVYH_EVENT_OCCURRED2_RTC_15_SHFT		17
1635
+#define UVYH_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000020000UL
1636
+#define UVYH_EVENT_OCCURRED2_RTC_16_SHFT		18
1637
+#define UVYH_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000040000UL
1638
+#define UVYH_EVENT_OCCURRED2_RTC_17_SHFT		19
1639
+#define UVYH_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000080000UL
1640
+#define UVYH_EVENT_OCCURRED2_RTC_18_SHFT		20
1641
+#define UVYH_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000100000UL
1642
+#define UVYH_EVENT_OCCURRED2_RTC_19_SHFT		21
1643
+#define UVYH_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000200000UL
1644
+#define UVYH_EVENT_OCCURRED2_RTC_20_SHFT		22
1645
+#define UVYH_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000400000UL
1646
+#define UVYH_EVENT_OCCURRED2_RTC_21_SHFT		23
1647
+#define UVYH_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000800000UL
1648
+#define UVYH_EVENT_OCCURRED2_RTC_22_SHFT		24
1649
+#define UVYH_EVENT_OCCURRED2_RTC_22_MASK		0x0000000001000000UL
1650
+#define UVYH_EVENT_OCCURRED2_RTC_23_SHFT		25
1651
+#define UVYH_EVENT_OCCURRED2_RTC_23_MASK		0x0000000002000000UL
1652
+#define UVYH_EVENT_OCCURRED2_RTC_24_SHFT		26
1653
+#define UVYH_EVENT_OCCURRED2_RTC_24_MASK		0x0000000004000000UL
1654
+#define UVYH_EVENT_OCCURRED2_RTC_25_SHFT		27
1655
+#define UVYH_EVENT_OCCURRED2_RTC_25_MASK		0x0000000008000000UL
1656
+#define UVYH_EVENT_OCCURRED2_RTC_26_SHFT		28
1657
+#define UVYH_EVENT_OCCURRED2_RTC_26_MASK		0x0000000010000000UL
1658
+#define UVYH_EVENT_OCCURRED2_RTC_27_SHFT		29
1659
+#define UVYH_EVENT_OCCURRED2_RTC_27_MASK		0x0000000020000000UL
1660
+#define UVYH_EVENT_OCCURRED2_RTC_28_SHFT		30
1661
+#define UVYH_EVENT_OCCURRED2_RTC_28_MASK		0x0000000040000000UL
1662
+#define UVYH_EVENT_OCCURRED2_RTC_29_SHFT		31
1663
+#define UVYH_EVENT_OCCURRED2_RTC_29_MASK		0x0000000080000000UL
1664
+#define UVYH_EVENT_OCCURRED2_RTC_30_SHFT		32
1665
+#define UVYH_EVENT_OCCURRED2_RTC_30_MASK		0x0000000100000000UL
1666
+#define UVYH_EVENT_OCCURRED2_RTC_31_SHFT		33
1667
+#define UVYH_EVENT_OCCURRED2_RTC_31_MASK		0x0000000200000000UL
43011668 
4302
-
4303
-#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT			0
4304
-#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT			1
4305
-#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT			2
4306
-#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT			3
4307
-#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT			4
4308
-#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT			5
4309
-#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT			6
4310
-#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT			7
4311
-#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT			8
4312
-#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT			9
4313
-#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT		10
4314
-#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT		11
4315
-#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT		12
4316
-#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT		13
4317
-#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT		14
4318
-#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT		15
4319
-#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT		16
4320
-#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT		17
4321
-#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT		18
4322
-#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT		19
4323
-#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT		20
4324
-#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT		21
4325
-#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT		22
4326
-#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT		23
4327
-#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT		24
4328
-#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT		25
4329
-#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT		26
4330
-#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT		27
4331
-#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT		28
4332
-#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT		29
4333
-#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT		30
4334
-#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT		31
4335
-#define UV2H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
4336
-#define UV2H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
4337
-#define UV2H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
4338
-#define UV2H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
4339
-#define UV2H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
4340
-#define UV2H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
4341
-#define UV2H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
4342
-#define UV2H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
4343
-#define UV2H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
4344
-#define UV2H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
4345
-#define UV2H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
4346
-#define UV2H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
4347
-#define UV2H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
4348
-#define UV2H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
4349
-#define UV2H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
4350
-#define UV2H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
4351
-#define UV2H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
4352
-#define UV2H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
4353
-#define UV2H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
4354
-#define UV2H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
4355
-#define UV2H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
4356
-#define UV2H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
4357
-#define UV2H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
4358
-#define UV2H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
4359
-#define UV2H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
4360
-#define UV2H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
4361
-#define UV2H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
4362
-#define UV2H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
4363
-#define UV2H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
4364
-#define UV2H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
4365
-#define UV2H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
4366
-#define UV2H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
4367
-
4368
-#define UV3H_EVENT_OCCURRED2_RTC_0_SHFT			0
4369
-#define UV3H_EVENT_OCCURRED2_RTC_1_SHFT			1
4370
-#define UV3H_EVENT_OCCURRED2_RTC_2_SHFT			2
4371
-#define UV3H_EVENT_OCCURRED2_RTC_3_SHFT			3
4372
-#define UV3H_EVENT_OCCURRED2_RTC_4_SHFT			4
4373
-#define UV3H_EVENT_OCCURRED2_RTC_5_SHFT			5
4374
-#define UV3H_EVENT_OCCURRED2_RTC_6_SHFT			6
4375
-#define UV3H_EVENT_OCCURRED2_RTC_7_SHFT			7
4376
-#define UV3H_EVENT_OCCURRED2_RTC_8_SHFT			8
4377
-#define UV3H_EVENT_OCCURRED2_RTC_9_SHFT			9
4378
-#define UV3H_EVENT_OCCURRED2_RTC_10_SHFT		10
4379
-#define UV3H_EVENT_OCCURRED2_RTC_11_SHFT		11
4380
-#define UV3H_EVENT_OCCURRED2_RTC_12_SHFT		12
4381
-#define UV3H_EVENT_OCCURRED2_RTC_13_SHFT		13
4382
-#define UV3H_EVENT_OCCURRED2_RTC_14_SHFT		14
4383
-#define UV3H_EVENT_OCCURRED2_RTC_15_SHFT		15
4384
-#define UV3H_EVENT_OCCURRED2_RTC_16_SHFT		16
4385
-#define UV3H_EVENT_OCCURRED2_RTC_17_SHFT		17
4386
-#define UV3H_EVENT_OCCURRED2_RTC_18_SHFT		18
4387
-#define UV3H_EVENT_OCCURRED2_RTC_19_SHFT		19
4388
-#define UV3H_EVENT_OCCURRED2_RTC_20_SHFT		20
4389
-#define UV3H_EVENT_OCCURRED2_RTC_21_SHFT		21
4390
-#define UV3H_EVENT_OCCURRED2_RTC_22_SHFT		22
4391
-#define UV3H_EVENT_OCCURRED2_RTC_23_SHFT		23
4392
-#define UV3H_EVENT_OCCURRED2_RTC_24_SHFT		24
4393
-#define UV3H_EVENT_OCCURRED2_RTC_25_SHFT		25
4394
-#define UV3H_EVENT_OCCURRED2_RTC_26_SHFT		26
4395
-#define UV3H_EVENT_OCCURRED2_RTC_27_SHFT		27
4396
-#define UV3H_EVENT_OCCURRED2_RTC_28_SHFT		28
4397
-#define UV3H_EVENT_OCCURRED2_RTC_29_SHFT		29
4398
-#define UV3H_EVENT_OCCURRED2_RTC_30_SHFT		30
4399
-#define UV3H_EVENT_OCCURRED2_RTC_31_SHFT		31
4400
-#define UV3H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
4401
-#define UV3H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
4402
-#define UV3H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
4403
-#define UV3H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
4404
-#define UV3H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
4405
-#define UV3H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
4406
-#define UV3H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
4407
-#define UV3H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
4408
-#define UV3H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
4409
-#define UV3H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
4410
-#define UV3H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
4411
-#define UV3H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
4412
-#define UV3H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
4413
-#define UV3H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
4414
-#define UV3H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
4415
-#define UV3H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
4416
-#define UV3H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
4417
-#define UV3H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
4418
-#define UV3H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
4419
-#define UV3H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
4420
-#define UV3H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
4421
-#define UV3H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
4422
-#define UV3H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
4423
-#define UV3H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
4424
-#define UV3H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
4425
-#define UV3H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
4426
-#define UV3H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
4427
-#define UV3H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
4428
-#define UV3H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
4429
-#define UV3H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
4430
-#define UV3H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
4431
-#define UV3H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
4432
-
1669
+/* UV4 unique defines */
44331670 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
4434
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
4435
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
4436
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
4437
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
4438
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
4439
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
4440
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
4441
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
4442
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
4443
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
4444
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
4445
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
4446
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
4447
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
4448
-#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
4449
-#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT	16
4450
-#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT	17
4451
-#define UV4H_EVENT_OCCURRED2_RTC_0_SHFT			18
4452
-#define UV4H_EVENT_OCCURRED2_RTC_1_SHFT			19
4453
-#define UV4H_EVENT_OCCURRED2_RTC_2_SHFT			20
4454
-#define UV4H_EVENT_OCCURRED2_RTC_3_SHFT			21
4455
-#define UV4H_EVENT_OCCURRED2_RTC_4_SHFT			22
4456
-#define UV4H_EVENT_OCCURRED2_RTC_5_SHFT			23
4457
-#define UV4H_EVENT_OCCURRED2_RTC_6_SHFT			24
4458
-#define UV4H_EVENT_OCCURRED2_RTC_7_SHFT			25
4459
-#define UV4H_EVENT_OCCURRED2_RTC_8_SHFT			26
4460
-#define UV4H_EVENT_OCCURRED2_RTC_9_SHFT			27
4461
-#define UV4H_EVENT_OCCURRED2_RTC_10_SHFT		28
4462
-#define UV4H_EVENT_OCCURRED2_RTC_11_SHFT		29
4463
-#define UV4H_EVENT_OCCURRED2_RTC_12_SHFT		30
4464
-#define UV4H_EVENT_OCCURRED2_RTC_13_SHFT		31
4465
-#define UV4H_EVENT_OCCURRED2_RTC_14_SHFT		32
4466
-#define UV4H_EVENT_OCCURRED2_RTC_15_SHFT		33
4467
-#define UV4H_EVENT_OCCURRED2_RTC_16_SHFT		34
4468
-#define UV4H_EVENT_OCCURRED2_RTC_17_SHFT		35
4469
-#define UV4H_EVENT_OCCURRED2_RTC_18_SHFT		36
4470
-#define UV4H_EVENT_OCCURRED2_RTC_19_SHFT		37
4471
-#define UV4H_EVENT_OCCURRED2_RTC_20_SHFT		38
4472
-#define UV4H_EVENT_OCCURRED2_RTC_21_SHFT		39
4473
-#define UV4H_EVENT_OCCURRED2_RTC_22_SHFT		40
4474
-#define UV4H_EVENT_OCCURRED2_RTC_23_SHFT		41
4475
-#define UV4H_EVENT_OCCURRED2_RTC_24_SHFT		42
4476
-#define UV4H_EVENT_OCCURRED2_RTC_25_SHFT		43
4477
-#define UV4H_EVENT_OCCURRED2_RTC_26_SHFT		44
4478
-#define UV4H_EVENT_OCCURRED2_RTC_27_SHFT		45
4479
-#define UV4H_EVENT_OCCURRED2_RTC_28_SHFT		46
4480
-#define UV4H_EVENT_OCCURRED2_RTC_29_SHFT		47
4481
-#define UV4H_EVENT_OCCURRED2_RTC_30_SHFT		48
4482
-#define UV4H_EVENT_OCCURRED2_RTC_31_SHFT		49
44831671 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
1672
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
44841673 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
1674
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
44851675 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
1676
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
44861677 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
1678
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
44871679 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
1680
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
44881681 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
1682
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
44891683 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
1684
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
44901685 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
1686
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
44911687 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
1688
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
44921689 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
1690
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
44931691 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
1692
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
44941693 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
1694
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
44951695 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
1696
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
44961697 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
1698
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
44971699 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
1700
+#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
44981701 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
1702
+#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT	16
44991703 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK	0x0000000000010000UL
1704
+#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT	17
45001705 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK	0x0000000000020000UL
1706
+#define UV4H_EVENT_OCCURRED2_RTC_0_SHFT			18
45011707 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000040000UL
1708
+#define UV4H_EVENT_OCCURRED2_RTC_1_SHFT			19
45021709 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000080000UL
1710
+#define UV4H_EVENT_OCCURRED2_RTC_2_SHFT			20
45031711 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000100000UL
1712
+#define UV4H_EVENT_OCCURRED2_RTC_3_SHFT			21
45041713 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000200000UL
1714
+#define UV4H_EVENT_OCCURRED2_RTC_4_SHFT			22
45051715 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000400000UL
1716
+#define UV4H_EVENT_OCCURRED2_RTC_5_SHFT			23
45061717 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000800000UL
1718
+#define UV4H_EVENT_OCCURRED2_RTC_6_SHFT			24
45071719 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000001000000UL
1720
+#define UV4H_EVENT_OCCURRED2_RTC_7_SHFT			25
45081721 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000002000000UL
1722
+#define UV4H_EVENT_OCCURRED2_RTC_8_SHFT			26
45091723 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000004000000UL
1724
+#define UV4H_EVENT_OCCURRED2_RTC_9_SHFT			27
45101725 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000008000000UL
1726
+#define UV4H_EVENT_OCCURRED2_RTC_10_SHFT		28
45111727 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000010000000UL
1728
+#define UV4H_EVENT_OCCURRED2_RTC_11_SHFT		29
45121729 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000020000000UL
1730
+#define UV4H_EVENT_OCCURRED2_RTC_12_SHFT		30
45131731 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000040000000UL
1732
+#define UV4H_EVENT_OCCURRED2_RTC_13_SHFT		31
45141733 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000080000000UL
1734
+#define UV4H_EVENT_OCCURRED2_RTC_14_SHFT		32
45151735 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000100000000UL
1736
+#define UV4H_EVENT_OCCURRED2_RTC_15_SHFT		33
45161737 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000200000000UL
1738
+#define UV4H_EVENT_OCCURRED2_RTC_16_SHFT		34
45171739 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000400000000UL
1740
+#define UV4H_EVENT_OCCURRED2_RTC_17_SHFT		35
45181741 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000800000000UL
1742
+#define UV4H_EVENT_OCCURRED2_RTC_18_SHFT		36
45191743 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK		0x0000001000000000UL
1744
+#define UV4H_EVENT_OCCURRED2_RTC_19_SHFT		37
45201745 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK		0x0000002000000000UL
1746
+#define UV4H_EVENT_OCCURRED2_RTC_20_SHFT		38
45211747 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK		0x0000004000000000UL
1748
+#define UV4H_EVENT_OCCURRED2_RTC_21_SHFT		39
45221749 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK		0x0000008000000000UL
1750
+#define UV4H_EVENT_OCCURRED2_RTC_22_SHFT		40
45231751 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK		0x0000010000000000UL
1752
+#define UV4H_EVENT_OCCURRED2_RTC_23_SHFT		41
45241753 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK		0x0000020000000000UL
1754
+#define UV4H_EVENT_OCCURRED2_RTC_24_SHFT		42
45251755 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK		0x0000040000000000UL
1756
+#define UV4H_EVENT_OCCURRED2_RTC_25_SHFT		43
45261757 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK		0x0000080000000000UL
1758
+#define UV4H_EVENT_OCCURRED2_RTC_26_SHFT		44
45271759 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK		0x0000100000000000UL
1760
+#define UV4H_EVENT_OCCURRED2_RTC_27_SHFT		45
45281761 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK		0x0000200000000000UL
1762
+#define UV4H_EVENT_OCCURRED2_RTC_28_SHFT		46
45291763 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK		0x0000400000000000UL
1764
+#define UV4H_EVENT_OCCURRED2_RTC_29_SHFT		47
45301765 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK		0x0000800000000000UL
1766
+#define UV4H_EVENT_OCCURRED2_RTC_30_SHFT		48
45311767 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK		0x0001000000000000UL
1768
+#define UV4H_EVENT_OCCURRED2_RTC_31_SHFT		49
45321769 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK		0x0002000000000000UL
45331770 
4534
-#define UVXH_EVENT_OCCURRED2_RTC_1_MASK (				\
4535
-	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK :		\
4536
-	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK :		\
4537
-	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK)
1771
+/* UV3 unique defines */
1772
+#define UV3H_EVENT_OCCURRED2_RTC_0_SHFT			0
1773
+#define UV3H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
1774
+#define UV3H_EVENT_OCCURRED2_RTC_1_SHFT			1
1775
+#define UV3H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
1776
+#define UV3H_EVENT_OCCURRED2_RTC_2_SHFT			2
1777
+#define UV3H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
1778
+#define UV3H_EVENT_OCCURRED2_RTC_3_SHFT			3
1779
+#define UV3H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
1780
+#define UV3H_EVENT_OCCURRED2_RTC_4_SHFT			4
1781
+#define UV3H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
1782
+#define UV3H_EVENT_OCCURRED2_RTC_5_SHFT			5
1783
+#define UV3H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
1784
+#define UV3H_EVENT_OCCURRED2_RTC_6_SHFT			6
1785
+#define UV3H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
1786
+#define UV3H_EVENT_OCCURRED2_RTC_7_SHFT			7
1787
+#define UV3H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
1788
+#define UV3H_EVENT_OCCURRED2_RTC_8_SHFT			8
1789
+#define UV3H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
1790
+#define UV3H_EVENT_OCCURRED2_RTC_9_SHFT			9
1791
+#define UV3H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
1792
+#define UV3H_EVENT_OCCURRED2_RTC_10_SHFT		10
1793
+#define UV3H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
1794
+#define UV3H_EVENT_OCCURRED2_RTC_11_SHFT		11
1795
+#define UV3H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
1796
+#define UV3H_EVENT_OCCURRED2_RTC_12_SHFT		12
1797
+#define UV3H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
1798
+#define UV3H_EVENT_OCCURRED2_RTC_13_SHFT		13
1799
+#define UV3H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
1800
+#define UV3H_EVENT_OCCURRED2_RTC_14_SHFT		14
1801
+#define UV3H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
1802
+#define UV3H_EVENT_OCCURRED2_RTC_15_SHFT		15
1803
+#define UV3H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
1804
+#define UV3H_EVENT_OCCURRED2_RTC_16_SHFT		16
1805
+#define UV3H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
1806
+#define UV3H_EVENT_OCCURRED2_RTC_17_SHFT		17
1807
+#define UV3H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
1808
+#define UV3H_EVENT_OCCURRED2_RTC_18_SHFT		18
1809
+#define UV3H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
1810
+#define UV3H_EVENT_OCCURRED2_RTC_19_SHFT		19
1811
+#define UV3H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
1812
+#define UV3H_EVENT_OCCURRED2_RTC_20_SHFT		20
1813
+#define UV3H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
1814
+#define UV3H_EVENT_OCCURRED2_RTC_21_SHFT		21
1815
+#define UV3H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
1816
+#define UV3H_EVENT_OCCURRED2_RTC_22_SHFT		22
1817
+#define UV3H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
1818
+#define UV3H_EVENT_OCCURRED2_RTC_23_SHFT		23
1819
+#define UV3H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
1820
+#define UV3H_EVENT_OCCURRED2_RTC_24_SHFT		24
1821
+#define UV3H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
1822
+#define UV3H_EVENT_OCCURRED2_RTC_25_SHFT		25
1823
+#define UV3H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
1824
+#define UV3H_EVENT_OCCURRED2_RTC_26_SHFT		26
1825
+#define UV3H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
1826
+#define UV3H_EVENT_OCCURRED2_RTC_27_SHFT		27
1827
+#define UV3H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
1828
+#define UV3H_EVENT_OCCURRED2_RTC_28_SHFT		28
1829
+#define UV3H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
1830
+#define UV3H_EVENT_OCCURRED2_RTC_29_SHFT		29
1831
+#define UV3H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
1832
+#define UV3H_EVENT_OCCURRED2_RTC_30_SHFT		30
1833
+#define UV3H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
1834
+#define UV3H_EVENT_OCCURRED2_RTC_31_SHFT		31
1835
+#define UV3H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
45381836 
4539
-union uvh_event_occurred2_u {
1837
+/* UV2 unique defines */
1838
+#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT			0
1839
+#define UV2H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
1840
+#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT			1
1841
+#define UV2H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
1842
+#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT			2
1843
+#define UV2H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
1844
+#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT			3
1845
+#define UV2H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
1846
+#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT			4
1847
+#define UV2H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
1848
+#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT			5
1849
+#define UV2H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
1850
+#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT			6
1851
+#define UV2H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
1852
+#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT			7
1853
+#define UV2H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
1854
+#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT			8
1855
+#define UV2H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
1856
+#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT			9
1857
+#define UV2H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
1858
+#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT		10
1859
+#define UV2H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
1860
+#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT		11
1861
+#define UV2H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
1862
+#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT		12
1863
+#define UV2H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
1864
+#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT		13
1865
+#define UV2H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
1866
+#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT		14
1867
+#define UV2H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
1868
+#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT		15
1869
+#define UV2H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
1870
+#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT		16
1871
+#define UV2H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
1872
+#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT		17
1873
+#define UV2H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
1874
+#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT		18
1875
+#define UV2H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
1876
+#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT		19
1877
+#define UV2H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
1878
+#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT		20
1879
+#define UV2H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
1880
+#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT		21
1881
+#define UV2H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
1882
+#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT		22
1883
+#define UV2H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
1884
+#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT		23
1885
+#define UV2H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
1886
+#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT		24
1887
+#define UV2H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
1888
+#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT		25
1889
+#define UV2H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
1890
+#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT		26
1891
+#define UV2H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
1892
+#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT		27
1893
+#define UV2H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
1894
+#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT		28
1895
+#define UV2H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
1896
+#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT		29
1897
+#define UV2H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
1898
+#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT		30
1899
+#define UV2H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
1900
+#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT		31
1901
+#define UV2H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
1902
+
1903
+#define UVH_EVENT_OCCURRED2_RTC_1_MASK (				\
1904
+	is_uv(UV5) ? 0x0000000000000008UL :				\
1905
+	is_uv(UV4) ? 0x0000000000080000UL :				\
1906
+	is_uv(UV3) ? 0x0000000000000002UL :				\
1907
+	is_uv(UV2) ? 0x0000000000000002UL :				\
1908
+	0)
1909
+#define UVH_EVENT_OCCURRED2_RTC_1_SHFT (				\
1910
+	is_uv(UV5) ? 3 :						\
1911
+	is_uv(UV4) ? 19 :						\
1912
+	is_uv(UV3) ? 1 :						\
1913
+	is_uv(UV2) ? 1 :						\
1914
+	-1)
1915
+
1916
+union uvyh_event_occurred2_u {
45401917 	unsigned long	v;
4541
-	struct uv2h_event_occurred2_s {
1918
+
1919
+	/* UVYH common struct */
1920
+	struct uvyh_event_occurred2_s {
1921
+		unsigned long	rtc_interval_int:1;		/* RW */
1922
+		unsigned long	bau_dashboard_int:1;		/* RW */
45421923 		unsigned long	rtc_0:1;			/* RW */
45431924 		unsigned long	rtc_1:1;			/* RW */
45441925 		unsigned long	rtc_2:1;			/* RW */
....@@ -4571,9 +1952,13 @@
45711952 		unsigned long	rtc_29:1;			/* RW */
45721953 		unsigned long	rtc_30:1;			/* RW */
45731954 		unsigned long	rtc_31:1;			/* RW */
4574
-		unsigned long	rsvd_32_63:32;
4575
-	} s2;
4576
-	struct uv3h_event_occurred2_s {
1955
+		unsigned long	rsvd_34_63:30;
1956
+	} sy;
1957
+
1958
+	/* UV5 unique struct */
1959
+	struct uv5h_event_occurred2_s {
1960
+		unsigned long	rtc_interval_int:1;		/* RW */
1961
+		unsigned long	bau_dashboard_int:1;		/* RW */
45771962 		unsigned long	rtc_0:1;			/* RW */
45781963 		unsigned long	rtc_1:1;			/* RW */
45791964 		unsigned long	rtc_2:1;			/* RW */
....@@ -4606,8 +1991,10 @@
46061991 		unsigned long	rtc_29:1;			/* RW */
46071992 		unsigned long	rtc_30:1;			/* RW */
46081993 		unsigned long	rtc_31:1;			/* RW */
4609
-		unsigned long	rsvd_32_63:32;
4610
-	} s3;
1994
+		unsigned long	rsvd_34_63:30;
1995
+	} s5;
1996
+
1997
+	/* UV4 unique struct */
46111998 	struct uv4h_event_occurred2_s {
46121999 		unsigned long	message_accelerator_int0:1;	/* RW */
46132000 		unsigned long	message_accelerator_int1:1;	/* RW */
....@@ -4661,168 +2048,2590 @@
46612048 		unsigned long	rtc_31:1;			/* RW */
46622049 		unsigned long	rsvd_50_63:14;
46632050 	} s4;
4664
-};
46652051 
4666
-/* ========================================================================= */
4667
-/*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
4668
-/* ========================================================================= */
4669
-#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
4670
-
4671
-#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
4672
-#define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70
4673
-#define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610
4674
-#define UVH_EVENT_OCCURRED2_ALIAS_32 (					\
4675
-	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 :			\
4676
-	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 :			\
4677
-	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32)
4678
-
4679
-
4680
-/* ========================================================================= */
4681
-/*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
4682
-/* ========================================================================= */
4683
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4684
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4685
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL
4686
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 (				\
4687
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 :		\
4688
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 :		\
4689
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2)
4690
-
4691
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4692
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4693
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10
4694
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 (				\
4695
-	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :		\
4696
-	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :		\
4697
-	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32)
4698
-
4699
-#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4700
-#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4701
-
4702
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4703
-#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4704
-
4705
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4706
-#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4707
-
4708
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4709
-#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4710
-
4711
-
4712
-union uvxh_lb_bau_sb_activation_status_2_u {
4713
-	unsigned long	v;
4714
-	struct uvxh_lb_bau_sb_activation_status_2_s {
4715
-		unsigned long	aux_error:64;			/* RW */
4716
-	} sx;
4717
-	struct uv2h_lb_bau_sb_activation_status_2_s {
4718
-		unsigned long	aux_error:64;			/* RW */
4719
-	} s2;
4720
-	struct uv3h_lb_bau_sb_activation_status_2_s {
4721
-		unsigned long	aux_error:64;			/* RW */
4722
-	} s3;
4723
-	struct uv4h_lb_bau_sb_activation_status_2_s {
4724
-		unsigned long	aux_error:64;			/* RW */
4725
-	} s4;
4726
-};
4727
-
4728
-/* ========================================================================= */
4729
-/*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
4730
-/* ========================================================================= */
4731
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK		0x320130UL
4732
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32		0x9f0
4733
-
4734
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
4735
-#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
4736
-
4737
-union uv1h_lb_target_physical_apic_id_mask_u {
4738
-	unsigned long	v;
4739
-	struct uv1h_lb_target_physical_apic_id_mask_s {
4740
-		unsigned long	bit_enables:32;			/* RW */
2052
+	/* UV3 unique struct */
2053
+	struct uv3h_event_occurred2_s {
2054
+		unsigned long	rtc_0:1;			/* RW */
2055
+		unsigned long	rtc_1:1;			/* RW */
2056
+		unsigned long	rtc_2:1;			/* RW */
2057
+		unsigned long	rtc_3:1;			/* RW */
2058
+		unsigned long	rtc_4:1;			/* RW */
2059
+		unsigned long	rtc_5:1;			/* RW */
2060
+		unsigned long	rtc_6:1;			/* RW */
2061
+		unsigned long	rtc_7:1;			/* RW */
2062
+		unsigned long	rtc_8:1;			/* RW */
2063
+		unsigned long	rtc_9:1;			/* RW */
2064
+		unsigned long	rtc_10:1;			/* RW */
2065
+		unsigned long	rtc_11:1;			/* RW */
2066
+		unsigned long	rtc_12:1;			/* RW */
2067
+		unsigned long	rtc_13:1;			/* RW */
2068
+		unsigned long	rtc_14:1;			/* RW */
2069
+		unsigned long	rtc_15:1;			/* RW */
2070
+		unsigned long	rtc_16:1;			/* RW */
2071
+		unsigned long	rtc_17:1;			/* RW */
2072
+		unsigned long	rtc_18:1;			/* RW */
2073
+		unsigned long	rtc_19:1;			/* RW */
2074
+		unsigned long	rtc_20:1;			/* RW */
2075
+		unsigned long	rtc_21:1;			/* RW */
2076
+		unsigned long	rtc_22:1;			/* RW */
2077
+		unsigned long	rtc_23:1;			/* RW */
2078
+		unsigned long	rtc_24:1;			/* RW */
2079
+		unsigned long	rtc_25:1;			/* RW */
2080
+		unsigned long	rtc_26:1;			/* RW */
2081
+		unsigned long	rtc_27:1;			/* RW */
2082
+		unsigned long	rtc_28:1;			/* RW */
2083
+		unsigned long	rtc_29:1;			/* RW */
2084
+		unsigned long	rtc_30:1;			/* RW */
2085
+		unsigned long	rtc_31:1;			/* RW */
47412086 		unsigned long	rsvd_32_63:32;
4742
-	} s1;
2087
+	} s3;
2088
+
2089
+	/* UV2 unique struct */
2090
+	struct uv2h_event_occurred2_s {
2091
+		unsigned long	rtc_0:1;			/* RW */
2092
+		unsigned long	rtc_1:1;			/* RW */
2093
+		unsigned long	rtc_2:1;			/* RW */
2094
+		unsigned long	rtc_3:1;			/* RW */
2095
+		unsigned long	rtc_4:1;			/* RW */
2096
+		unsigned long	rtc_5:1;			/* RW */
2097
+		unsigned long	rtc_6:1;			/* RW */
2098
+		unsigned long	rtc_7:1;			/* RW */
2099
+		unsigned long	rtc_8:1;			/* RW */
2100
+		unsigned long	rtc_9:1;			/* RW */
2101
+		unsigned long	rtc_10:1;			/* RW */
2102
+		unsigned long	rtc_11:1;			/* RW */
2103
+		unsigned long	rtc_12:1;			/* RW */
2104
+		unsigned long	rtc_13:1;			/* RW */
2105
+		unsigned long	rtc_14:1;			/* RW */
2106
+		unsigned long	rtc_15:1;			/* RW */
2107
+		unsigned long	rtc_16:1;			/* RW */
2108
+		unsigned long	rtc_17:1;			/* RW */
2109
+		unsigned long	rtc_18:1;			/* RW */
2110
+		unsigned long	rtc_19:1;			/* RW */
2111
+		unsigned long	rtc_20:1;			/* RW */
2112
+		unsigned long	rtc_21:1;			/* RW */
2113
+		unsigned long	rtc_22:1;			/* RW */
2114
+		unsigned long	rtc_23:1;			/* RW */
2115
+		unsigned long	rtc_24:1;			/* RW */
2116
+		unsigned long	rtc_25:1;			/* RW */
2117
+		unsigned long	rtc_26:1;			/* RW */
2118
+		unsigned long	rtc_27:1;			/* RW */
2119
+		unsigned long	rtc_28:1;			/* RW */
2120
+		unsigned long	rtc_29:1;			/* RW */
2121
+		unsigned long	rtc_30:1;			/* RW */
2122
+		unsigned long	rtc_31:1;			/* RW */
2123
+		unsigned long	rsvd_32_63:32;
2124
+	} s2;
47432125 };
47442126 
47452127 /* ========================================================================= */
4746
-/*                          UV3H_GR0_GAM_GR_CONFIG                           */
2128
+/*                        UVH_EVENT_OCCURRED2_ALIAS                          */
47472129 /* ========================================================================= */
4748
-#define UV3H_GR0_GAM_GR_CONFIG				0xc00028UL
2130
+#define UVH_EVENT_OCCURRED2_ALIAS 0x70108UL
47492131 
2132
+
2133
+/* ========================================================================= */
2134
+/*                         UVH_EXTIO_INT0_BROADCAST                          */
2135
+/* ========================================================================= */
2136
+#define UVH_EXTIO_INT0_BROADCAST 0x61448UL
2137
+
2138
+/* UVH common defines*/
2139
+#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT		0
2140
+#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK		0x0000000000000001UL
2141
+
2142
+
2143
+union uvh_extio_int0_broadcast_u {
2144
+	unsigned long	v;
2145
+
2146
+	/* UVH common struct */
2147
+	struct uvh_extio_int0_broadcast_s {
2148
+		unsigned long	enable:1;			/* RW */
2149
+		unsigned long	rsvd_1_63:63;
2150
+	} s;
2151
+
2152
+	/* UV5 unique struct */
2153
+	struct uv5h_extio_int0_broadcast_s {
2154
+		unsigned long	enable:1;			/* RW */
2155
+		unsigned long	rsvd_1_63:63;
2156
+	} s5;
2157
+
2158
+	/* UV4 unique struct */
2159
+	struct uv4h_extio_int0_broadcast_s {
2160
+		unsigned long	enable:1;			/* RW */
2161
+		unsigned long	rsvd_1_63:63;
2162
+	} s4;
2163
+
2164
+	/* UV3 unique struct */
2165
+	struct uv3h_extio_int0_broadcast_s {
2166
+		unsigned long	enable:1;			/* RW */
2167
+		unsigned long	rsvd_1_63:63;
2168
+	} s3;
2169
+
2170
+	/* UV2 unique struct */
2171
+	struct uv2h_extio_int0_broadcast_s {
2172
+		unsigned long	enable:1;			/* RW */
2173
+		unsigned long	rsvd_1_63:63;
2174
+	} s2;
2175
+};
2176
+
2177
+/* ========================================================================= */
2178
+/*                          UVH_GR0_GAM_GR_CONFIG                            */
2179
+/* ========================================================================= */
2180
+#define UVH_GR0_GAM_GR_CONFIG (						\
2181
+	is_uv(UV5) ? 0x600028UL :					\
2182
+	is_uv(UV4) ? 0x600028UL :					\
2183
+	is_uv(UV3) ? 0xc00028UL :					\
2184
+	is_uv(UV2) ? 0xc00028UL :					\
2185
+	0)
2186
+
2187
+
2188
+
2189
+/* UVYH common defines */
2190
+#define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT		10
2191
+#define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_MASK		0x0000000000000400UL
2192
+
2193
+/* UV4 unique defines */
2194
+#define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT		10
2195
+#define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK		0x0000000000000400UL
2196
+
2197
+/* UV3 unique defines */
47502198 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT		0
4751
-#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT		10
47522199 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK		0x000000000000003fUL
2200
+#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT		10
47532201 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK		0x0000000000000400UL
47542202 
4755
-union uv3h_gr0_gam_gr_config_u {
2203
+/* UV2 unique defines */
2204
+#define UV2H_GR0_GAM_GR_CONFIG_N_GR_SHFT		0
2205
+#define UV2H_GR0_GAM_GR_CONFIG_N_GR_MASK		0x000000000000000fUL
2206
+
2207
+
2208
+union uvyh_gr0_gam_gr_config_u {
47562209 	unsigned long	v;
2210
+
2211
+	/* UVYH common struct */
2212
+	struct uvyh_gr0_gam_gr_config_s {
2213
+		unsigned long	rsvd_0_9:10;
2214
+		unsigned long	subspace:1;			/* RW */
2215
+		unsigned long	rsvd_11_63:53;
2216
+	} sy;
2217
+
2218
+	/* UV5 unique struct */
2219
+	struct uv5h_gr0_gam_gr_config_s {
2220
+		unsigned long	rsvd_0_9:10;
2221
+		unsigned long	subspace:1;			/* RW */
2222
+		unsigned long	rsvd_11_63:53;
2223
+	} s5;
2224
+
2225
+	/* UV4 unique struct */
2226
+	struct uv4h_gr0_gam_gr_config_s {
2227
+		unsigned long	rsvd_0_9:10;
2228
+		unsigned long	subspace:1;			/* RW */
2229
+		unsigned long	rsvd_11_63:53;
2230
+	} s4;
2231
+
2232
+	/* UV3 unique struct */
47572233 	struct uv3h_gr0_gam_gr_config_s {
47582234 		unsigned long	m_skt:6;			/* RW */
47592235 		unsigned long	undef_6_9:4;			/* Undefined */
47602236 		unsigned long	subspace:1;			/* RW */
47612237 		unsigned long	reserved:53;
47622238 	} s3;
2239
+
2240
+	/* UV2 unique struct */
2241
+	struct uv2h_gr0_gam_gr_config_s {
2242
+		unsigned long	n_gr:4;				/* RW */
2243
+		unsigned long	reserved:60;
2244
+	} s2;
47632245 };
47642246 
47652247 /* ========================================================================= */
4766
-/*                       UV4H_LB_PROC_INTD_QUEUE_FIRST                       */
2248
+/*                         UVH_GR0_TLB_INT0_CONFIG                           */
47672249 /* ========================================================================= */
4768
-#define UV4H_LB_PROC_INTD_QUEUE_FIRST			0xa4100UL
2250
+#define UVH_GR0_TLB_INT0_CONFIG (					\
2251
+	is_uv(UV4) ? 0x61b00UL :					\
2252
+	is_uv(UV3) ? 0x61b00UL :					\
2253
+	is_uv(UV2) ? 0x61b00UL :					\
2254
+	uv_undefined("UVH_GR0_TLB_INT0_CONFIG"))
47692255 
4770
-#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6
4771
-#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL
47722256 
4773
-union uv4h_lb_proc_intd_queue_first_u {
2257
+/* UVXH common defines */
2258
+#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT		0
2259
+#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
2260
+#define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT		8
2261
+#define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK		0x0000000000000700UL
2262
+#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT		11
2263
+#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
2264
+#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT		12
2265
+#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
2266
+#define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT			13
2267
+#define UVXH_GR0_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
2268
+#define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT			15
2269
+#define UVXH_GR0_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
2270
+#define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT			16
2271
+#define UVXH_GR0_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
2272
+#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT		32
2273
+#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
2274
+
2275
+
2276
+union uvh_gr0_tlb_int0_config_u {
47742277 	unsigned long	v;
4775
-	struct uv4h_lb_proc_intd_queue_first_s {
2278
+
2279
+	/* UVH common struct */
2280
+	struct uvh_gr0_tlb_int0_config_s {
2281
+		unsigned long	vector_:8;			/* RW */
2282
+		unsigned long	dm:3;				/* RW */
2283
+		unsigned long	destmode:1;			/* RW */
2284
+		unsigned long	status:1;			/* RO */
2285
+		unsigned long	p:1;				/* RO */
2286
+		unsigned long	rsvd_14:1;
2287
+		unsigned long	t:1;				/* RO */
2288
+		unsigned long	m:1;				/* RW */
2289
+		unsigned long	rsvd_17_31:15;
2290
+		unsigned long	apic_id:32;			/* RW */
2291
+	} s;
2292
+
2293
+	/* UVXH common struct */
2294
+	struct uvxh_gr0_tlb_int0_config_s {
2295
+		unsigned long	vector_:8;			/* RW */
2296
+		unsigned long	dm:3;				/* RW */
2297
+		unsigned long	destmode:1;			/* RW */
2298
+		unsigned long	status:1;			/* RO */
2299
+		unsigned long	p:1;				/* RO */
2300
+		unsigned long	rsvd_14:1;
2301
+		unsigned long	t:1;				/* RO */
2302
+		unsigned long	m:1;				/* RW */
2303
+		unsigned long	rsvd_17_31:15;
2304
+		unsigned long	apic_id:32;			/* RW */
2305
+	} sx;
2306
+
2307
+	/* UV4 unique struct */
2308
+	struct uv4h_gr0_tlb_int0_config_s {
2309
+		unsigned long	vector_:8;			/* RW */
2310
+		unsigned long	dm:3;				/* RW */
2311
+		unsigned long	destmode:1;			/* RW */
2312
+		unsigned long	status:1;			/* RO */
2313
+		unsigned long	p:1;				/* RO */
2314
+		unsigned long	rsvd_14:1;
2315
+		unsigned long	t:1;				/* RO */
2316
+		unsigned long	m:1;				/* RW */
2317
+		unsigned long	rsvd_17_31:15;
2318
+		unsigned long	apic_id:32;			/* RW */
2319
+	} s4;
2320
+
2321
+	/* UV3 unique struct */
2322
+	struct uv3h_gr0_tlb_int0_config_s {
2323
+		unsigned long	vector_:8;			/* RW */
2324
+		unsigned long	dm:3;				/* RW */
2325
+		unsigned long	destmode:1;			/* RW */
2326
+		unsigned long	status:1;			/* RO */
2327
+		unsigned long	p:1;				/* RO */
2328
+		unsigned long	rsvd_14:1;
2329
+		unsigned long	t:1;				/* RO */
2330
+		unsigned long	m:1;				/* RW */
2331
+		unsigned long	rsvd_17_31:15;
2332
+		unsigned long	apic_id:32;			/* RW */
2333
+	} s3;
2334
+
2335
+	/* UV2 unique struct */
2336
+	struct uv2h_gr0_tlb_int0_config_s {
2337
+		unsigned long	vector_:8;			/* RW */
2338
+		unsigned long	dm:3;				/* RW */
2339
+		unsigned long	destmode:1;			/* RW */
2340
+		unsigned long	status:1;			/* RO */
2341
+		unsigned long	p:1;				/* RO */
2342
+		unsigned long	rsvd_14:1;
2343
+		unsigned long	t:1;				/* RO */
2344
+		unsigned long	m:1;				/* RW */
2345
+		unsigned long	rsvd_17_31:15;
2346
+		unsigned long	apic_id:32;			/* RW */
2347
+	} s2;
2348
+};
2349
+
2350
+/* ========================================================================= */
2351
+/*                         UVH_GR0_TLB_INT1_CONFIG                           */
2352
+/* ========================================================================= */
2353
+#define UVH_GR0_TLB_INT1_CONFIG (					\
2354
+	is_uv(UV4) ? 0x61b40UL :					\
2355
+	is_uv(UV3) ? 0x61b40UL :					\
2356
+	is_uv(UV2) ? 0x61b40UL :					\
2357
+	uv_undefined("UVH_GR0_TLB_INT1_CONFIG"))
2358
+
2359
+
2360
+/* UVXH common defines */
2361
+#define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT		0
2362
+#define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
2363
+#define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT		8
2364
+#define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK		0x0000000000000700UL
2365
+#define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT		11
2366
+#define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
2367
+#define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT		12
2368
+#define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
2369
+#define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT			13
2370
+#define UVXH_GR0_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
2371
+#define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT			15
2372
+#define UVXH_GR0_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
2373
+#define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT			16
2374
+#define UVXH_GR0_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
2375
+#define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT		32
2376
+#define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
2377
+
2378
+
2379
+union uvh_gr0_tlb_int1_config_u {
2380
+	unsigned long	v;
2381
+
2382
+	/* UVH common struct */
2383
+	struct uvh_gr0_tlb_int1_config_s {
2384
+		unsigned long	vector_:8;			/* RW */
2385
+		unsigned long	dm:3;				/* RW */
2386
+		unsigned long	destmode:1;			/* RW */
2387
+		unsigned long	status:1;			/* RO */
2388
+		unsigned long	p:1;				/* RO */
2389
+		unsigned long	rsvd_14:1;
2390
+		unsigned long	t:1;				/* RO */
2391
+		unsigned long	m:1;				/* RW */
2392
+		unsigned long	rsvd_17_31:15;
2393
+		unsigned long	apic_id:32;			/* RW */
2394
+	} s;
2395
+
2396
+	/* UVXH common struct */
2397
+	struct uvxh_gr0_tlb_int1_config_s {
2398
+		unsigned long	vector_:8;			/* RW */
2399
+		unsigned long	dm:3;				/* RW */
2400
+		unsigned long	destmode:1;			/* RW */
2401
+		unsigned long	status:1;			/* RO */
2402
+		unsigned long	p:1;				/* RO */
2403
+		unsigned long	rsvd_14:1;
2404
+		unsigned long	t:1;				/* RO */
2405
+		unsigned long	m:1;				/* RW */
2406
+		unsigned long	rsvd_17_31:15;
2407
+		unsigned long	apic_id:32;			/* RW */
2408
+	} sx;
2409
+
2410
+	/* UV4 unique struct */
2411
+	struct uv4h_gr0_tlb_int1_config_s {
2412
+		unsigned long	vector_:8;			/* RW */
2413
+		unsigned long	dm:3;				/* RW */
2414
+		unsigned long	destmode:1;			/* RW */
2415
+		unsigned long	status:1;			/* RO */
2416
+		unsigned long	p:1;				/* RO */
2417
+		unsigned long	rsvd_14:1;
2418
+		unsigned long	t:1;				/* RO */
2419
+		unsigned long	m:1;				/* RW */
2420
+		unsigned long	rsvd_17_31:15;
2421
+		unsigned long	apic_id:32;			/* RW */
2422
+	} s4;
2423
+
2424
+	/* UV3 unique struct */
2425
+	struct uv3h_gr0_tlb_int1_config_s {
2426
+		unsigned long	vector_:8;			/* RW */
2427
+		unsigned long	dm:3;				/* RW */
2428
+		unsigned long	destmode:1;			/* RW */
2429
+		unsigned long	status:1;			/* RO */
2430
+		unsigned long	p:1;				/* RO */
2431
+		unsigned long	rsvd_14:1;
2432
+		unsigned long	t:1;				/* RO */
2433
+		unsigned long	m:1;				/* RW */
2434
+		unsigned long	rsvd_17_31:15;
2435
+		unsigned long	apic_id:32;			/* RW */
2436
+	} s3;
2437
+
2438
+	/* UV2 unique struct */
2439
+	struct uv2h_gr0_tlb_int1_config_s {
2440
+		unsigned long	vector_:8;			/* RW */
2441
+		unsigned long	dm:3;				/* RW */
2442
+		unsigned long	destmode:1;			/* RW */
2443
+		unsigned long	status:1;			/* RO */
2444
+		unsigned long	p:1;				/* RO */
2445
+		unsigned long	rsvd_14:1;
2446
+		unsigned long	t:1;				/* RO */
2447
+		unsigned long	m:1;				/* RW */
2448
+		unsigned long	rsvd_17_31:15;
2449
+		unsigned long	apic_id:32;			/* RW */
2450
+	} s2;
2451
+};
2452
+
2453
+/* ========================================================================= */
2454
+/*                         UVH_GR1_TLB_INT0_CONFIG                           */
2455
+/* ========================================================================= */
2456
+#define UVH_GR1_TLB_INT0_CONFIG (					\
2457
+	is_uv(UV4) ? 0x62100UL :					\
2458
+	is_uv(UV3) ? 0x61f00UL :					\
2459
+	is_uv(UV2) ? 0x61f00UL :					\
2460
+	uv_undefined("UVH_GR1_TLB_INT0_CONFIG"))
2461
+
2462
+
2463
+/* UVXH common defines */
2464
+#define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT		0
2465
+#define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
2466
+#define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT		8
2467
+#define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK		0x0000000000000700UL
2468
+#define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT		11
2469
+#define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
2470
+#define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT		12
2471
+#define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
2472
+#define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT			13
2473
+#define UVXH_GR1_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
2474
+#define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT			15
2475
+#define UVXH_GR1_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
2476
+#define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT			16
2477
+#define UVXH_GR1_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
2478
+#define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT		32
2479
+#define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
2480
+
2481
+
2482
+union uvh_gr1_tlb_int0_config_u {
2483
+	unsigned long	v;
2484
+
2485
+	/* UVH common struct */
2486
+	struct uvh_gr1_tlb_int0_config_s {
2487
+		unsigned long	vector_:8;			/* RW */
2488
+		unsigned long	dm:3;				/* RW */
2489
+		unsigned long	destmode:1;			/* RW */
2490
+		unsigned long	status:1;			/* RO */
2491
+		unsigned long	p:1;				/* RO */
2492
+		unsigned long	rsvd_14:1;
2493
+		unsigned long	t:1;				/* RO */
2494
+		unsigned long	m:1;				/* RW */
2495
+		unsigned long	rsvd_17_31:15;
2496
+		unsigned long	apic_id:32;			/* RW */
2497
+	} s;
2498
+
2499
+	/* UVXH common struct */
2500
+	struct uvxh_gr1_tlb_int0_config_s {
2501
+		unsigned long	vector_:8;			/* RW */
2502
+		unsigned long	dm:3;				/* RW */
2503
+		unsigned long	destmode:1;			/* RW */
2504
+		unsigned long	status:1;			/* RO */
2505
+		unsigned long	p:1;				/* RO */
2506
+		unsigned long	rsvd_14:1;
2507
+		unsigned long	t:1;				/* RO */
2508
+		unsigned long	m:1;				/* RW */
2509
+		unsigned long	rsvd_17_31:15;
2510
+		unsigned long	apic_id:32;			/* RW */
2511
+	} sx;
2512
+
2513
+	/* UV4 unique struct */
2514
+	struct uv4h_gr1_tlb_int0_config_s {
2515
+		unsigned long	vector_:8;			/* RW */
2516
+		unsigned long	dm:3;				/* RW */
2517
+		unsigned long	destmode:1;			/* RW */
2518
+		unsigned long	status:1;			/* RO */
2519
+		unsigned long	p:1;				/* RO */
2520
+		unsigned long	rsvd_14:1;
2521
+		unsigned long	t:1;				/* RO */
2522
+		unsigned long	m:1;				/* RW */
2523
+		unsigned long	rsvd_17_31:15;
2524
+		unsigned long	apic_id:32;			/* RW */
2525
+	} s4;
2526
+
2527
+	/* UV3 unique struct */
2528
+	struct uv3h_gr1_tlb_int0_config_s {
2529
+		unsigned long	vector_:8;			/* RW */
2530
+		unsigned long	dm:3;				/* RW */
2531
+		unsigned long	destmode:1;			/* RW */
2532
+		unsigned long	status:1;			/* RO */
2533
+		unsigned long	p:1;				/* RO */
2534
+		unsigned long	rsvd_14:1;
2535
+		unsigned long	t:1;				/* RO */
2536
+		unsigned long	m:1;				/* RW */
2537
+		unsigned long	rsvd_17_31:15;
2538
+		unsigned long	apic_id:32;			/* RW */
2539
+	} s3;
2540
+
2541
+	/* UV2 unique struct */
2542
+	struct uv2h_gr1_tlb_int0_config_s {
2543
+		unsigned long	vector_:8;			/* RW */
2544
+		unsigned long	dm:3;				/* RW */
2545
+		unsigned long	destmode:1;			/* RW */
2546
+		unsigned long	status:1;			/* RO */
2547
+		unsigned long	p:1;				/* RO */
2548
+		unsigned long	rsvd_14:1;
2549
+		unsigned long	t:1;				/* RO */
2550
+		unsigned long	m:1;				/* RW */
2551
+		unsigned long	rsvd_17_31:15;
2552
+		unsigned long	apic_id:32;			/* RW */
2553
+	} s2;
2554
+};
2555
+
2556
+/* ========================================================================= */
2557
+/*                         UVH_GR1_TLB_INT1_CONFIG                           */
2558
+/* ========================================================================= */
2559
+#define UVH_GR1_TLB_INT1_CONFIG (					\
2560
+	is_uv(UV4) ? 0x62140UL :					\
2561
+	is_uv(UV3) ? 0x61f40UL :					\
2562
+	is_uv(UV2) ? 0x61f40UL :					\
2563
+	uv_undefined("UVH_GR1_TLB_INT1_CONFIG"))
2564
+
2565
+
2566
+/* UVXH common defines */
2567
+#define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT		0
2568
+#define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
2569
+#define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT		8
2570
+#define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK		0x0000000000000700UL
2571
+#define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT		11
2572
+#define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
2573
+#define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT		12
2574
+#define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
2575
+#define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT			13
2576
+#define UVXH_GR1_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
2577
+#define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT			15
2578
+#define UVXH_GR1_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
2579
+#define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT			16
2580
+#define UVXH_GR1_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
2581
+#define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT		32
2582
+#define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
2583
+
2584
+
2585
+union uvh_gr1_tlb_int1_config_u {
2586
+	unsigned long	v;
2587
+
2588
+	/* UVH common struct */
2589
+	struct uvh_gr1_tlb_int1_config_s {
2590
+		unsigned long	vector_:8;			/* RW */
2591
+		unsigned long	dm:3;				/* RW */
2592
+		unsigned long	destmode:1;			/* RW */
2593
+		unsigned long	status:1;			/* RO */
2594
+		unsigned long	p:1;				/* RO */
2595
+		unsigned long	rsvd_14:1;
2596
+		unsigned long	t:1;				/* RO */
2597
+		unsigned long	m:1;				/* RW */
2598
+		unsigned long	rsvd_17_31:15;
2599
+		unsigned long	apic_id:32;			/* RW */
2600
+	} s;
2601
+
2602
+	/* UVXH common struct */
2603
+	struct uvxh_gr1_tlb_int1_config_s {
2604
+		unsigned long	vector_:8;			/* RW */
2605
+		unsigned long	dm:3;				/* RW */
2606
+		unsigned long	destmode:1;			/* RW */
2607
+		unsigned long	status:1;			/* RO */
2608
+		unsigned long	p:1;				/* RO */
2609
+		unsigned long	rsvd_14:1;
2610
+		unsigned long	t:1;				/* RO */
2611
+		unsigned long	m:1;				/* RW */
2612
+		unsigned long	rsvd_17_31:15;
2613
+		unsigned long	apic_id:32;			/* RW */
2614
+	} sx;
2615
+
2616
+	/* UV4 unique struct */
2617
+	struct uv4h_gr1_tlb_int1_config_s {
2618
+		unsigned long	vector_:8;			/* RW */
2619
+		unsigned long	dm:3;				/* RW */
2620
+		unsigned long	destmode:1;			/* RW */
2621
+		unsigned long	status:1;			/* RO */
2622
+		unsigned long	p:1;				/* RO */
2623
+		unsigned long	rsvd_14:1;
2624
+		unsigned long	t:1;				/* RO */
2625
+		unsigned long	m:1;				/* RW */
2626
+		unsigned long	rsvd_17_31:15;
2627
+		unsigned long	apic_id:32;			/* RW */
2628
+	} s4;
2629
+
2630
+	/* UV3 unique struct */
2631
+	struct uv3h_gr1_tlb_int1_config_s {
2632
+		unsigned long	vector_:8;			/* RW */
2633
+		unsigned long	dm:3;				/* RW */
2634
+		unsigned long	destmode:1;			/* RW */
2635
+		unsigned long	status:1;			/* RO */
2636
+		unsigned long	p:1;				/* RO */
2637
+		unsigned long	rsvd_14:1;
2638
+		unsigned long	t:1;				/* RO */
2639
+		unsigned long	m:1;				/* RW */
2640
+		unsigned long	rsvd_17_31:15;
2641
+		unsigned long	apic_id:32;			/* RW */
2642
+	} s3;
2643
+
2644
+	/* UV2 unique struct */
2645
+	struct uv2h_gr1_tlb_int1_config_s {
2646
+		unsigned long	vector_:8;			/* RW */
2647
+		unsigned long	dm:3;				/* RW */
2648
+		unsigned long	destmode:1;			/* RW */
2649
+		unsigned long	status:1;			/* RO */
2650
+		unsigned long	p:1;				/* RO */
2651
+		unsigned long	rsvd_14:1;
2652
+		unsigned long	t:1;				/* RO */
2653
+		unsigned long	m:1;				/* RW */
2654
+		unsigned long	rsvd_17_31:15;
2655
+		unsigned long	apic_id:32;			/* RW */
2656
+	} s2;
2657
+};
2658
+
2659
+/* ========================================================================= */
2660
+/*                               UVH_INT_CMPB                                */
2661
+/* ========================================================================= */
2662
+#define UVH_INT_CMPB 0x22080UL
2663
+
2664
+/* UVH common defines*/
2665
+#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT		0
2666
+#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK		0x00ffffffffffffffUL
2667
+
2668
+
2669
+union uvh_int_cmpb_u {
2670
+	unsigned long	v;
2671
+
2672
+	/* UVH common struct */
2673
+	struct uvh_int_cmpb_s {
2674
+		unsigned long	real_time_cmpb:56;		/* RW */
2675
+		unsigned long	rsvd_56_63:8;
2676
+	} s;
2677
+
2678
+	/* UV5 unique struct */
2679
+	struct uv5h_int_cmpb_s {
2680
+		unsigned long	real_time_cmpb:56;		/* RW */
2681
+		unsigned long	rsvd_56_63:8;
2682
+	} s5;
2683
+
2684
+	/* UV4 unique struct */
2685
+	struct uv4h_int_cmpb_s {
2686
+		unsigned long	real_time_cmpb:56;		/* RW */
2687
+		unsigned long	rsvd_56_63:8;
2688
+	} s4;
2689
+
2690
+	/* UV3 unique struct */
2691
+	struct uv3h_int_cmpb_s {
2692
+		unsigned long	real_time_cmpb:56;		/* RW */
2693
+		unsigned long	rsvd_56_63:8;
2694
+	} s3;
2695
+
2696
+	/* UV2 unique struct */
2697
+	struct uv2h_int_cmpb_s {
2698
+		unsigned long	real_time_cmpb:56;		/* RW */
2699
+		unsigned long	rsvd_56_63:8;
2700
+	} s2;
2701
+};
2702
+
2703
+/* ========================================================================= */
2704
+/*                               UVH_IPI_INT                                 */
2705
+/* ========================================================================= */
2706
+#define UVH_IPI_INT 0x60500UL
2707
+
2708
+/* UVH common defines*/
2709
+#define UVH_IPI_INT_VECTOR_SHFT				0
2710
+#define UVH_IPI_INT_VECTOR_MASK				0x00000000000000ffUL
2711
+#define UVH_IPI_INT_DELIVERY_MODE_SHFT			8
2712
+#define UVH_IPI_INT_DELIVERY_MODE_MASK			0x0000000000000700UL
2713
+#define UVH_IPI_INT_DESTMODE_SHFT			11
2714
+#define UVH_IPI_INT_DESTMODE_MASK			0x0000000000000800UL
2715
+#define UVH_IPI_INT_APIC_ID_SHFT			16
2716
+#define UVH_IPI_INT_APIC_ID_MASK			0x0000ffffffff0000UL
2717
+#define UVH_IPI_INT_SEND_SHFT				63
2718
+#define UVH_IPI_INT_SEND_MASK				0x8000000000000000UL
2719
+
2720
+
2721
+union uvh_ipi_int_u {
2722
+	unsigned long	v;
2723
+
2724
+	/* UVH common struct */
2725
+	struct uvh_ipi_int_s {
2726
+		unsigned long	vector_:8;			/* RW */
2727
+		unsigned long	delivery_mode:3;		/* RW */
2728
+		unsigned long	destmode:1;			/* RW */
2729
+		unsigned long	rsvd_12_15:4;
2730
+		unsigned long	apic_id:32;			/* RW */
2731
+		unsigned long	rsvd_48_62:15;
2732
+		unsigned long	send:1;				/* WP */
2733
+	} s;
2734
+
2735
+	/* UV5 unique struct */
2736
+	struct uv5h_ipi_int_s {
2737
+		unsigned long	vector_:8;			/* RW */
2738
+		unsigned long	delivery_mode:3;		/* RW */
2739
+		unsigned long	destmode:1;			/* RW */
2740
+		unsigned long	rsvd_12_15:4;
2741
+		unsigned long	apic_id:32;			/* RW */
2742
+		unsigned long	rsvd_48_62:15;
2743
+		unsigned long	send:1;				/* WP */
2744
+	} s5;
2745
+
2746
+	/* UV4 unique struct */
2747
+	struct uv4h_ipi_int_s {
2748
+		unsigned long	vector_:8;			/* RW */
2749
+		unsigned long	delivery_mode:3;		/* RW */
2750
+		unsigned long	destmode:1;			/* RW */
2751
+		unsigned long	rsvd_12_15:4;
2752
+		unsigned long	apic_id:32;			/* RW */
2753
+		unsigned long	rsvd_48_62:15;
2754
+		unsigned long	send:1;				/* WP */
2755
+	} s4;
2756
+
2757
+	/* UV3 unique struct */
2758
+	struct uv3h_ipi_int_s {
2759
+		unsigned long	vector_:8;			/* RW */
2760
+		unsigned long	delivery_mode:3;		/* RW */
2761
+		unsigned long	destmode:1;			/* RW */
2762
+		unsigned long	rsvd_12_15:4;
2763
+		unsigned long	apic_id:32;			/* RW */
2764
+		unsigned long	rsvd_48_62:15;
2765
+		unsigned long	send:1;				/* WP */
2766
+	} s3;
2767
+
2768
+	/* UV2 unique struct */
2769
+	struct uv2h_ipi_int_s {
2770
+		unsigned long	vector_:8;			/* RW */
2771
+		unsigned long	delivery_mode:3;		/* RW */
2772
+		unsigned long	destmode:1;			/* RW */
2773
+		unsigned long	rsvd_12_15:4;
2774
+		unsigned long	apic_id:32;			/* RW */
2775
+		unsigned long	rsvd_48_62:15;
2776
+		unsigned long	send:1;				/* WP */
2777
+	} s2;
2778
+};
2779
+
2780
+/* ========================================================================= */
2781
+/*                               UVH_NODE_ID                                 */
2782
+/* ========================================================================= */
2783
+#define UVH_NODE_ID 0x0UL
2784
+
2785
+/* UVH common defines*/
2786
+#define UVH_NODE_ID_FORCE1_SHFT				0
2787
+#define UVH_NODE_ID_FORCE1_MASK				0x0000000000000001UL
2788
+#define UVH_NODE_ID_MANUFACTURER_SHFT			1
2789
+#define UVH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2790
+#define UVH_NODE_ID_PART_NUMBER_SHFT			12
2791
+#define UVH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2792
+#define UVH_NODE_ID_REVISION_SHFT			28
2793
+#define UVH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2794
+#define UVH_NODE_ID_NODE_ID_SHFT			32
2795
+#define UVH_NODE_ID_NI_PORT_SHFT			57
2796
+
2797
+/* UVXH common defines */
2798
+#define UVXH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2799
+#define UVXH_NODE_ID_NODES_PER_BIT_SHFT			50
2800
+#define UVXH_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2801
+#define UVXH_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2802
+
2803
+/* UVYH common defines */
2804
+#define UVYH_NODE_ID_NODE_ID_MASK			0x0000007f00000000UL
2805
+#define UVYH_NODE_ID_NI_PORT_MASK			0x7e00000000000000UL
2806
+
2807
+/* UV4 unique defines */
2808
+#define UV4H_NODE_ID_ROUTER_SELECT_SHFT			48
2809
+#define UV4H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2810
+#define UV4H_NODE_ID_RESERVED_2_SHFT			49
2811
+#define UV4H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2812
+
2813
+/* UV3 unique defines */
2814
+#define UV3H_NODE_ID_ROUTER_SELECT_SHFT			48
2815
+#define UV3H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2816
+#define UV3H_NODE_ID_RESERVED_2_SHFT			49
2817
+#define UV3H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2818
+
2819
+
2820
+union uvh_node_id_u {
2821
+	unsigned long	v;
2822
+
2823
+	/* UVH common struct */
2824
+	struct uvh_node_id_s {
2825
+		unsigned long	force1:1;			/* RO */
2826
+		unsigned long	manufacturer:11;		/* RO */
2827
+		unsigned long	part_number:16;			/* RO */
2828
+		unsigned long	revision:4;			/* RO */
2829
+		unsigned long	rsvd_32_63:32;
2830
+	} s;
2831
+
2832
+	/* UVXH common struct */
2833
+	struct uvxh_node_id_s {
2834
+		unsigned long	force1:1;			/* RO */
2835
+		unsigned long	manufacturer:11;		/* RO */
2836
+		unsigned long	part_number:16;			/* RO */
2837
+		unsigned long	revision:4;			/* RO */
2838
+		unsigned long	node_id:15;			/* RW */
2839
+		unsigned long	rsvd_47_49:3;
2840
+		unsigned long	nodes_per_bit:7;		/* RO */
2841
+		unsigned long	ni_port:5;			/* RO */
2842
+		unsigned long	rsvd_62_63:2;
2843
+	} sx;
2844
+
2845
+	/* UVYH common struct */
2846
+	struct uvyh_node_id_s {
2847
+		unsigned long	force1:1;			/* RO */
2848
+		unsigned long	manufacturer:11;		/* RO */
2849
+		unsigned long	part_number:16;			/* RO */
2850
+		unsigned long	revision:4;			/* RO */
2851
+		unsigned long	node_id:7;			/* RW */
2852
+		unsigned long	rsvd_39_56:18;
2853
+		unsigned long	ni_port:6;			/* RO */
2854
+		unsigned long	rsvd_63:1;
2855
+	} sy;
2856
+
2857
+	/* UV5 unique struct */
2858
+	struct uv5h_node_id_s {
2859
+		unsigned long	force1:1;			/* RO */
2860
+		unsigned long	manufacturer:11;		/* RO */
2861
+		unsigned long	part_number:16;			/* RO */
2862
+		unsigned long	revision:4;			/* RO */
2863
+		unsigned long	node_id:7;			/* RW */
2864
+		unsigned long	rsvd_39_56:18;
2865
+		unsigned long	ni_port:6;			/* RO */
2866
+		unsigned long	rsvd_63:1;
2867
+	} s5;
2868
+
2869
+	/* UV4 unique struct */
2870
+	struct uv4h_node_id_s {
2871
+		unsigned long	force1:1;			/* RO */
2872
+		unsigned long	manufacturer:11;		/* RO */
2873
+		unsigned long	part_number:16;			/* RO */
2874
+		unsigned long	revision:4;			/* RO */
2875
+		unsigned long	node_id:15;			/* RW */
2876
+		unsigned long	rsvd_47:1;
2877
+		unsigned long	router_select:1;		/* RO */
2878
+		unsigned long	rsvd_49:1;
2879
+		unsigned long	nodes_per_bit:7;		/* RO */
2880
+		unsigned long	ni_port:5;			/* RO */
2881
+		unsigned long	rsvd_62_63:2;
2882
+	} s4;
2883
+
2884
+	/* UV3 unique struct */
2885
+	struct uv3h_node_id_s {
2886
+		unsigned long	force1:1;			/* RO */
2887
+		unsigned long	manufacturer:11;		/* RO */
2888
+		unsigned long	part_number:16;			/* RO */
2889
+		unsigned long	revision:4;			/* RO */
2890
+		unsigned long	node_id:15;			/* RW */
2891
+		unsigned long	rsvd_47:1;
2892
+		unsigned long	router_select:1;		/* RO */
2893
+		unsigned long	rsvd_49:1;
2894
+		unsigned long	nodes_per_bit:7;		/* RO */
2895
+		unsigned long	ni_port:5;			/* RO */
2896
+		unsigned long	rsvd_62_63:2;
2897
+	} s3;
2898
+
2899
+	/* UV2 unique struct */
2900
+	struct uv2h_node_id_s {
2901
+		unsigned long	force1:1;			/* RO */
2902
+		unsigned long	manufacturer:11;		/* RO */
2903
+		unsigned long	part_number:16;			/* RO */
2904
+		unsigned long	revision:4;			/* RO */
2905
+		unsigned long	node_id:15;			/* RW */
2906
+		unsigned long	rsvd_47_49:3;
2907
+		unsigned long	nodes_per_bit:7;		/* RO */
2908
+		unsigned long	ni_port:5;			/* RO */
2909
+		unsigned long	rsvd_62_63:2;
2910
+	} s2;
2911
+};
2912
+
2913
+/* ========================================================================= */
2914
+/*                            UVH_NODE_PRESENT_0                             */
2915
+/* ========================================================================= */
2916
+#define UVH_NODE_PRESENT_0 (						\
2917
+	is_uv(UV5) ? 0x1400UL :						\
2918
+	0)
2919
+
2920
+
2921
+/* UVYH common defines */
2922
+#define UVYH_NODE_PRESENT_0_NODES_SHFT			0
2923
+#define UVYH_NODE_PRESENT_0_NODES_MASK			0xffffffffffffffffUL
2924
+
2925
+
2926
+union uvh_node_present_0_u {
2927
+	unsigned long	v;
2928
+
2929
+	/* UVH common struct */
2930
+	struct uvh_node_present_0_s {
2931
+		unsigned long	nodes:64;			/* RW */
2932
+	} s;
2933
+
2934
+	/* UVYH common struct */
2935
+	struct uvyh_node_present_0_s {
2936
+		unsigned long	nodes:64;			/* RW */
2937
+	} sy;
2938
+
2939
+	/* UV5 unique struct */
2940
+	struct uv5h_node_present_0_s {
2941
+		unsigned long	nodes:64;			/* RW */
2942
+	} s5;
2943
+};
2944
+
2945
+/* ========================================================================= */
2946
+/*                            UVH_NODE_PRESENT_1                             */
2947
+/* ========================================================================= */
2948
+#define UVH_NODE_PRESENT_1 (						\
2949
+	is_uv(UV5) ? 0x1408UL :						\
2950
+	0)
2951
+
2952
+
2953
+/* UVYH common defines */
2954
+#define UVYH_NODE_PRESENT_1_NODES_SHFT			0
2955
+#define UVYH_NODE_PRESENT_1_NODES_MASK			0xffffffffffffffffUL
2956
+
2957
+
2958
+union uvh_node_present_1_u {
2959
+	unsigned long	v;
2960
+
2961
+	/* UVH common struct */
2962
+	struct uvh_node_present_1_s {
2963
+		unsigned long	nodes:64;			/* RW */
2964
+	} s;
2965
+
2966
+	/* UVYH common struct */
2967
+	struct uvyh_node_present_1_s {
2968
+		unsigned long	nodes:64;			/* RW */
2969
+	} sy;
2970
+
2971
+	/* UV5 unique struct */
2972
+	struct uv5h_node_present_1_s {
2973
+		unsigned long	nodes:64;			/* RW */
2974
+	} s5;
2975
+};
2976
+
2977
+/* ========================================================================= */
2978
+/*                          UVH_NODE_PRESENT_TABLE                           */
2979
+/* ========================================================================= */
2980
+#define UVH_NODE_PRESENT_TABLE (					\
2981
+	is_uv(UV4) ? 0x1400UL :						\
2982
+	is_uv(UV3) ? 0x1400UL :						\
2983
+	is_uv(UV2) ? 0x1400UL :						\
2984
+	0)
2985
+
2986
+#define UVH_NODE_PRESENT_TABLE_DEPTH (					\
2987
+	is_uv(UV4) ? 4 :						\
2988
+	is_uv(UV3) ? 16 :						\
2989
+	is_uv(UV2) ? 16 :						\
2990
+	0)
2991
+
2992
+
2993
+/* UVXH common defines */
2994
+#define UVXH_NODE_PRESENT_TABLE_NODES_SHFT		0
2995
+#define UVXH_NODE_PRESENT_TABLE_NODES_MASK		0xffffffffffffffffUL
2996
+
2997
+
2998
+union uvh_node_present_table_u {
2999
+	unsigned long	v;
3000
+
3001
+	/* UVH common struct */
3002
+	struct uvh_node_present_table_s {
3003
+		unsigned long	nodes:64;			/* RW */
3004
+	} s;
3005
+
3006
+	/* UVXH common struct */
3007
+	struct uvxh_node_present_table_s {
3008
+		unsigned long	nodes:64;			/* RW */
3009
+	} sx;
3010
+
3011
+	/* UV4 unique struct */
3012
+	struct uv4h_node_present_table_s {
3013
+		unsigned long	nodes:64;			/* RW */
3014
+	} s4;
3015
+
3016
+	/* UV3 unique struct */
3017
+	struct uv3h_node_present_table_s {
3018
+		unsigned long	nodes:64;			/* RW */
3019
+	} s3;
3020
+
3021
+	/* UV2 unique struct */
3022
+	struct uv2h_node_present_table_s {
3023
+		unsigned long	nodes:64;			/* RW */
3024
+	} s2;
3025
+};
3026
+
3027
+/* ========================================================================= */
3028
+/*                       UVH_RH10_GAM_ADDR_MAP_CONFIG                        */
3029
+/* ========================================================================= */
3030
+#define UVH_RH10_GAM_ADDR_MAP_CONFIG (					\
3031
+	is_uv(UV5) ? 0x470000UL :					\
3032
+	0)
3033
+
3034
+
3035
+/* UVYH common defines */
3036
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT	6
3037
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_MASK	0x00000000000001c0UL
3038
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_SHFT	12
3039
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_MASK	0x0000000000001000UL
3040
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_SHFT 16
3041
+#define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_MASK 0x00000000000f0000UL
3042
+
3043
+
3044
+union uvh_rh10_gam_addr_map_config_u {
3045
+	unsigned long	v;
3046
+
3047
+	/* UVH common struct */
3048
+	struct uvh_rh10_gam_addr_map_config_s {
47763049 		unsigned long	undef_0_5:6;			/* Undefined */
4777
-		unsigned long	first_payload_address:40;	/* RW */
4778
-	} s4;
3050
+		unsigned long	n_skt:3;			/* RW */
3051
+		unsigned long	undef_9_11:3;			/* Undefined */
3052
+		unsigned long	ls_enable:1;			/* RW */
3053
+		unsigned long	undef_13_15:3;			/* Undefined */
3054
+		unsigned long	mk_tme_keyid_bits:4;		/* RW */
3055
+		unsigned long	rsvd_20_63:44;
3056
+	} s;
3057
+
3058
+	/* UVYH common struct */
3059
+	struct uvyh_rh10_gam_addr_map_config_s {
3060
+		unsigned long	undef_0_5:6;			/* Undefined */
3061
+		unsigned long	n_skt:3;			/* RW */
3062
+		unsigned long	undef_9_11:3;			/* Undefined */
3063
+		unsigned long	ls_enable:1;			/* RW */
3064
+		unsigned long	undef_13_15:3;			/* Undefined */
3065
+		unsigned long	mk_tme_keyid_bits:4;		/* RW */
3066
+		unsigned long	rsvd_20_63:44;
3067
+	} sy;
3068
+
3069
+	/* UV5 unique struct */
3070
+	struct uv5h_rh10_gam_addr_map_config_s {
3071
+		unsigned long	undef_0_5:6;			/* Undefined */
3072
+		unsigned long	n_skt:3;			/* RW */
3073
+		unsigned long	undef_9_11:3;			/* Undefined */
3074
+		unsigned long	ls_enable:1;			/* RW */
3075
+		unsigned long	undef_13_15:3;			/* Undefined */
3076
+		unsigned long	mk_tme_keyid_bits:4;		/* RW */
3077
+	} s5;
47793078 };
47803079 
47813080 /* ========================================================================= */
4782
-/*                       UV4H_LB_PROC_INTD_QUEUE_LAST                        */
3081
+/*                     UVH_RH10_GAM_GRU_OVERLAY_CONFIG                       */
47833082 /* ========================================================================= */
4784
-#define UV4H_LB_PROC_INTD_QUEUE_LAST			0xa4108UL
3083
+#define UVH_RH10_GAM_GRU_OVERLAY_CONFIG (				\
3084
+	is_uv(UV5) ? 0x4700b0UL :					\
3085
+	0)
47853086 
4786
-#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5
4787
-#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL
47883087 
4789
-union uv4h_lb_proc_intd_queue_last_u {
3088
+/* UVYH common defines */
3089
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	25
3090
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x000ffffffe000000UL
3091
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT	52
3092
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK	0x0070000000000000UL
3093
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT	63
3094
+#define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3095
+
3096
+#define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK (			\
3097
+	is_uv(UV5) ? 0x000ffffffe000000UL :				\
3098
+	0)
3099
+#define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT (			\
3100
+	is_uv(UV5) ? 25 :						\
3101
+	-1)
3102
+
3103
+union uvh_rh10_gam_gru_overlay_config_u {
47903104 	unsigned long	v;
4791
-	struct uv4h_lb_proc_intd_queue_last_s {
4792
-		unsigned long	undef_0_4:5;			/* Undefined */
4793
-		unsigned long	last_payload_address:41;	/* RW */
4794
-	} s4;
3105
+
3106
+	/* UVH common struct */
3107
+	struct uvh_rh10_gam_gru_overlay_config_s {
3108
+		unsigned long	undef_0_24:25;			/* Undefined */
3109
+		unsigned long	base:27;			/* RW */
3110
+		unsigned long	n_gru:3;			/* RW */
3111
+		unsigned long	undef_55_62:8;			/* Undefined */
3112
+		unsigned long	enable:1;			/* RW */
3113
+	} s;
3114
+
3115
+	/* UVYH common struct */
3116
+	struct uvyh_rh10_gam_gru_overlay_config_s {
3117
+		unsigned long	undef_0_24:25;			/* Undefined */
3118
+		unsigned long	base:27;			/* RW */
3119
+		unsigned long	n_gru:3;			/* RW */
3120
+		unsigned long	undef_55_62:8;			/* Undefined */
3121
+		unsigned long	enable:1;			/* RW */
3122
+	} sy;
3123
+
3124
+	/* UV5 unique struct */
3125
+	struct uv5h_rh10_gam_gru_overlay_config_s {
3126
+		unsigned long	undef_0_24:25;			/* Undefined */
3127
+		unsigned long	base:27;			/* RW */
3128
+		unsigned long	n_gru:3;			/* RW */
3129
+		unsigned long	undef_55_62:8;			/* Undefined */
3130
+		unsigned long	enable:1;			/* RW */
3131
+	} s5;
47953132 };
47963133 
47973134 /* ========================================================================= */
4798
-/*                     UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                      */
3135
+/*                    UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0                     */
47993136 /* ========================================================================= */
4800
-#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR		0xa4118UL
3137
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0 (				\
3138
+	is_uv(UV5) ? 0x473000UL :					\
3139
+	0)
48013140 
4802
-#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0
4803
-#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL
48043141 
4805
-union uv4h_lb_proc_intd_soft_ack_clear_u {
3142
+/* UVYH common defines */
3143
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT	26
3144
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK	0x000ffffffc000000UL
3145
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT	52
3146
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK	0x03f0000000000000UL
3147
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT	63
3148
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK	0x8000000000000000UL
3149
+
3150
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK (			\
3151
+	is_uv(UV5) ? 0x000ffffffc000000UL :				\
3152
+	0)
3153
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT (			\
3154
+	is_uv(UV5) ? 26 :						\
3155
+	-1)
3156
+
3157
+union uvh_rh10_gam_mmioh_overlay_config0_u {
48063158 	unsigned long	v;
4807
-	struct uv4h_lb_proc_intd_soft_ack_clear_s {
4808
-		unsigned long	soft_ack_pending_flags:8;	/* WP */
4809
-	} s4;
3159
+
3160
+	/* UVH common struct */
3161
+	struct uvh_rh10_gam_mmioh_overlay_config0_s {
3162
+		unsigned long	rsvd_0_25:26;
3163
+		unsigned long	base:26;			/* RW */
3164
+		unsigned long	m_io:6;				/* RW */
3165
+		unsigned long	n_io:4;
3166
+		unsigned long	undef_62:1;			/* Undefined */
3167
+		unsigned long	enable:1;			/* RW */
3168
+	} s;
3169
+
3170
+	/* UVYH common struct */
3171
+	struct uvyh_rh10_gam_mmioh_overlay_config0_s {
3172
+		unsigned long	rsvd_0_25:26;
3173
+		unsigned long	base:26;			/* RW */
3174
+		unsigned long	m_io:6;				/* RW */
3175
+		unsigned long	n_io:4;
3176
+		unsigned long	undef_62:1;			/* Undefined */
3177
+		unsigned long	enable:1;			/* RW */
3178
+	} sy;
3179
+
3180
+	/* UV5 unique struct */
3181
+	struct uv5h_rh10_gam_mmioh_overlay_config0_s {
3182
+		unsigned long	rsvd_0_25:26;
3183
+		unsigned long	base:26;			/* RW */
3184
+		unsigned long	m_io:6;				/* RW */
3185
+		unsigned long	n_io:4;
3186
+		unsigned long	undef_62:1;			/* Undefined */
3187
+		unsigned long	enable:1;			/* RW */
3188
+	} s5;
48103189 };
48113190 
48123191 /* ========================================================================= */
4813
-/*                    UV4H_LB_PROC_INTD_SOFT_ACK_PENDING                     */
3192
+/*                    UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1                     */
48143193 /* ========================================================================= */
4815
-#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING		0xa4110UL
3194
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1 (				\
3195
+	is_uv(UV5) ? 0x474000UL :					\
3196
+	0)
48163197 
4817
-#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0
4818
-#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL
48193198 
4820
-union uv4h_lb_proc_intd_soft_ack_pending_u {
3199
+/* UVYH common defines */
3200
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT	26
3201
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK	0x000ffffffc000000UL
3202
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT	52
3203
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK	0x03f0000000000000UL
3204
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT	63
3205
+#define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK	0x8000000000000000UL
3206
+
3207
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK (			\
3208
+	is_uv(UV5) ? 0x000ffffffc000000UL :				\
3209
+	0)
3210
+#define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT (			\
3211
+	is_uv(UV5) ? 26 :						\
3212
+	-1)
3213
+
3214
+union uvh_rh10_gam_mmioh_overlay_config1_u {
48213215 	unsigned long	v;
4822
-	struct uv4h_lb_proc_intd_soft_ack_pending_s {
4823
-		unsigned long	soft_ack_flags:8;		/* RW */
4824
-	} s4;
3216
+
3217
+	/* UVH common struct */
3218
+	struct uvh_rh10_gam_mmioh_overlay_config1_s {
3219
+		unsigned long	rsvd_0_25:26;
3220
+		unsigned long	base:26;			/* RW */
3221
+		unsigned long	m_io:6;				/* RW */
3222
+		unsigned long	n_io:4;
3223
+		unsigned long	undef_62:1;			/* Undefined */
3224
+		unsigned long	enable:1;			/* RW */
3225
+	} s;
3226
+
3227
+	/* UVYH common struct */
3228
+	struct uvyh_rh10_gam_mmioh_overlay_config1_s {
3229
+		unsigned long	rsvd_0_25:26;
3230
+		unsigned long	base:26;			/* RW */
3231
+		unsigned long	m_io:6;				/* RW */
3232
+		unsigned long	n_io:4;
3233
+		unsigned long	undef_62:1;			/* Undefined */
3234
+		unsigned long	enable:1;			/* RW */
3235
+	} sy;
3236
+
3237
+	/* UV5 unique struct */
3238
+	struct uv5h_rh10_gam_mmioh_overlay_config1_s {
3239
+		unsigned long	rsvd_0_25:26;
3240
+		unsigned long	base:26;			/* RW */
3241
+		unsigned long	m_io:6;				/* RW */
3242
+		unsigned long	n_io:4;
3243
+		unsigned long	undef_62:1;			/* Undefined */
3244
+		unsigned long	enable:1;			/* RW */
3245
+	} s5;
48253246 };
48263247 
3248
+/* ========================================================================= */
3249
+/*                   UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0                     */
3250
+/* ========================================================================= */
3251
+#define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0 (				\
3252
+	is_uv(UV5) ? 0x473800UL :					\
3253
+	0)
3254
+
3255
+#define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH (			\
3256
+	is_uv(UV5) ? 128 :						\
3257
+	0)
3258
+
3259
+
3260
+/* UVYH common defines */
3261
+#define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT	0
3262
+#define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK	0x000000000000007fUL
3263
+
3264
+
3265
+union uvh_rh10_gam_mmioh_redirect_config0_u {
3266
+	unsigned long	v;
3267
+
3268
+	/* UVH common struct */
3269
+	struct uvh_rh10_gam_mmioh_redirect_config0_s {
3270
+		unsigned long	nasid:7;			/* RW */
3271
+		unsigned long	rsvd_7_63:57;
3272
+	} s;
3273
+
3274
+	/* UVYH common struct */
3275
+	struct uvyh_rh10_gam_mmioh_redirect_config0_s {
3276
+		unsigned long	nasid:7;			/* RW */
3277
+		unsigned long	rsvd_7_63:57;
3278
+	} sy;
3279
+
3280
+	/* UV5 unique struct */
3281
+	struct uv5h_rh10_gam_mmioh_redirect_config0_s {
3282
+		unsigned long	nasid:7;			/* RW */
3283
+		unsigned long	rsvd_7_63:57;
3284
+	} s5;
3285
+};
3286
+
3287
+/* ========================================================================= */
3288
+/*                   UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1                     */
3289
+/* ========================================================================= */
3290
+#define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1 (				\
3291
+	is_uv(UV5) ? 0x474800UL :					\
3292
+	0)
3293
+
3294
+#define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH (			\
3295
+	is_uv(UV5) ? 128 :						\
3296
+	0)
3297
+
3298
+
3299
+/* UVYH common defines */
3300
+#define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT	0
3301
+#define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK	0x000000000000007fUL
3302
+
3303
+
3304
+union uvh_rh10_gam_mmioh_redirect_config1_u {
3305
+	unsigned long	v;
3306
+
3307
+	/* UVH common struct */
3308
+	struct uvh_rh10_gam_mmioh_redirect_config1_s {
3309
+		unsigned long	nasid:7;			/* RW */
3310
+		unsigned long	rsvd_7_63:57;
3311
+	} s;
3312
+
3313
+	/* UVYH common struct */
3314
+	struct uvyh_rh10_gam_mmioh_redirect_config1_s {
3315
+		unsigned long	nasid:7;			/* RW */
3316
+		unsigned long	rsvd_7_63:57;
3317
+	} sy;
3318
+
3319
+	/* UV5 unique struct */
3320
+	struct uv5h_rh10_gam_mmioh_redirect_config1_s {
3321
+		unsigned long	nasid:7;			/* RW */
3322
+		unsigned long	rsvd_7_63:57;
3323
+	} s5;
3324
+};
3325
+
3326
+/* ========================================================================= */
3327
+/*                     UVH_RH10_GAM_MMR_OVERLAY_CONFIG                       */
3328
+/* ========================================================================= */
3329
+#define UVH_RH10_GAM_MMR_OVERLAY_CONFIG (				\
3330
+	is_uv(UV5) ? 0x470090UL :					\
3331
+	0)
3332
+
3333
+
3334
+/* UVYH common defines */
3335
+#define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT	25
3336
+#define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK	0x000ffffffe000000UL
3337
+#define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT	63
3338
+#define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3339
+
3340
+#define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK (			\
3341
+	is_uv(UV5) ? 0x000ffffffe000000UL :				\
3342
+	0)
3343
+#define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT (			\
3344
+	is_uv(UV5) ? 25 :						\
3345
+	-1)
3346
+
3347
+union uvh_rh10_gam_mmr_overlay_config_u {
3348
+	unsigned long	v;
3349
+
3350
+	/* UVH common struct */
3351
+	struct uvh_rh10_gam_mmr_overlay_config_s {
3352
+		unsigned long	undef_0_24:25;			/* Undefined */
3353
+		unsigned long	base:27;			/* RW */
3354
+		unsigned long	undef_52_62:11;			/* Undefined */
3355
+		unsigned long	enable:1;			/* RW */
3356
+	} s;
3357
+
3358
+	/* UVYH common struct */
3359
+	struct uvyh_rh10_gam_mmr_overlay_config_s {
3360
+		unsigned long	undef_0_24:25;			/* Undefined */
3361
+		unsigned long	base:27;			/* RW */
3362
+		unsigned long	undef_52_62:11;			/* Undefined */
3363
+		unsigned long	enable:1;			/* RW */
3364
+	} sy;
3365
+
3366
+	/* UV5 unique struct */
3367
+	struct uv5h_rh10_gam_mmr_overlay_config_s {
3368
+		unsigned long	undef_0_24:25;			/* Undefined */
3369
+		unsigned long	base:27;			/* RW */
3370
+		unsigned long	undef_52_62:11;			/* Undefined */
3371
+		unsigned long	enable:1;			/* RW */
3372
+	} s5;
3373
+};
3374
+
3375
+/* ========================================================================= */
3376
+/*                        UVH_RH_GAM_ADDR_MAP_CONFIG                         */
3377
+/* ========================================================================= */
3378
+#define UVH_RH_GAM_ADDR_MAP_CONFIG (					\
3379
+	is_uv(UV4) ? 0x480000UL :					\
3380
+	is_uv(UV3) ? 0x1600000UL :					\
3381
+	is_uv(UV2) ? 0x1600000UL :					\
3382
+	0)
3383
+
3384
+
3385
+/* UVXH common defines */
3386
+#define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT		6
3387
+#define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_MASK		0x00000000000003c0UL
3388
+
3389
+/* UV3 unique defines */
3390
+#define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT		0
3391
+#define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK		0x000000000000003fUL
3392
+
3393
+/* UV2 unique defines */
3394
+#define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT		0
3395
+#define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK		0x000000000000003fUL
3396
+
3397
+
3398
+union uvh_rh_gam_addr_map_config_u {
3399
+	unsigned long	v;
3400
+
3401
+	/* UVH common struct */
3402
+	struct uvh_rh_gam_addr_map_config_s {
3403
+		unsigned long	rsvd_0_5:6;
3404
+		unsigned long	n_skt:4;			/* RW */
3405
+		unsigned long	rsvd_10_63:54;
3406
+	} s;
3407
+
3408
+	/* UVXH common struct */
3409
+	struct uvxh_rh_gam_addr_map_config_s {
3410
+		unsigned long	rsvd_0_5:6;
3411
+		unsigned long	n_skt:4;			/* RW */
3412
+		unsigned long	rsvd_10_63:54;
3413
+	} sx;
3414
+
3415
+	/* UV4 unique struct */
3416
+	struct uv4h_rh_gam_addr_map_config_s {
3417
+		unsigned long	rsvd_0_5:6;
3418
+		unsigned long	n_skt:4;			/* RW */
3419
+		unsigned long	rsvd_10_63:54;
3420
+	} s4;
3421
+
3422
+	/* UV3 unique struct */
3423
+	struct uv3h_rh_gam_addr_map_config_s {
3424
+		unsigned long	m_skt:6;			/* RW */
3425
+		unsigned long	n_skt:4;			/* RW */
3426
+		unsigned long	rsvd_10_63:54;
3427
+	} s3;
3428
+
3429
+	/* UV2 unique struct */
3430
+	struct uv2h_rh_gam_addr_map_config_s {
3431
+		unsigned long	m_skt:6;			/* RW */
3432
+		unsigned long	n_skt:4;			/* RW */
3433
+		unsigned long	rsvd_10_63:54;
3434
+	} s2;
3435
+};
3436
+
3437
+/* ========================================================================= */
3438
+/*                    UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG                      */
3439
+/* ========================================================================= */
3440
+#define UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG (				\
3441
+	is_uv(UV4) ? 0x4800c8UL :					\
3442
+	is_uv(UV3) ? 0x16000c8UL :					\
3443
+	is_uv(UV2) ? 0x16000c8UL :					\
3444
+	0)
3445
+
3446
+
3447
+/* UVXH common defines */
3448
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_SHFT	24
3449
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_MASK	0x00000000ff000000UL
3450
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_SHFT	48
3451
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_MASK	0x001f000000000000UL
3452
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_SHFT	63
3453
+#define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3454
+
3455
+
3456
+union uvh_rh_gam_alias_0_overlay_config_u {
3457
+	unsigned long	v;
3458
+
3459
+	/* UVH common struct */
3460
+	struct uvh_rh_gam_alias_0_overlay_config_s {
3461
+		unsigned long	rsvd_0_23:24;
3462
+		unsigned long	base:8;				/* RW */
3463
+		unsigned long	rsvd_32_47:16;
3464
+		unsigned long	m_alias:5;			/* RW */
3465
+		unsigned long	rsvd_53_62:10;
3466
+		unsigned long	enable:1;			/* RW */
3467
+	} s;
3468
+
3469
+	/* UVXH common struct */
3470
+	struct uvxh_rh_gam_alias_0_overlay_config_s {
3471
+		unsigned long	rsvd_0_23:24;
3472
+		unsigned long	base:8;				/* RW */
3473
+		unsigned long	rsvd_32_47:16;
3474
+		unsigned long	m_alias:5;			/* RW */
3475
+		unsigned long	rsvd_53_62:10;
3476
+		unsigned long	enable:1;			/* RW */
3477
+	} sx;
3478
+
3479
+	/* UV4 unique struct */
3480
+	struct uv4h_rh_gam_alias_0_overlay_config_s {
3481
+		unsigned long	rsvd_0_23:24;
3482
+		unsigned long	base:8;				/* RW */
3483
+		unsigned long	rsvd_32_47:16;
3484
+		unsigned long	m_alias:5;			/* RW */
3485
+		unsigned long	rsvd_53_62:10;
3486
+		unsigned long	enable:1;			/* RW */
3487
+	} s4;
3488
+
3489
+	/* UV3 unique struct */
3490
+	struct uv3h_rh_gam_alias_0_overlay_config_s {
3491
+		unsigned long	rsvd_0_23:24;
3492
+		unsigned long	base:8;				/* RW */
3493
+		unsigned long	rsvd_32_47:16;
3494
+		unsigned long	m_alias:5;			/* RW */
3495
+		unsigned long	rsvd_53_62:10;
3496
+		unsigned long	enable:1;			/* RW */
3497
+	} s3;
3498
+
3499
+	/* UV2 unique struct */
3500
+	struct uv2h_rh_gam_alias_0_overlay_config_s {
3501
+		unsigned long	rsvd_0_23:24;
3502
+		unsigned long	base:8;				/* RW */
3503
+		unsigned long	rsvd_32_47:16;
3504
+		unsigned long	m_alias:5;			/* RW */
3505
+		unsigned long	rsvd_53_62:10;
3506
+		unsigned long	enable:1;			/* RW */
3507
+	} s2;
3508
+};
3509
+
3510
+/* ========================================================================= */
3511
+/*                    UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG                     */
3512
+/* ========================================================================= */
3513
+#define UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG (				\
3514
+	is_uv(UV4) ? 0x4800d0UL :					\
3515
+	is_uv(UV3) ? 0x16000d0UL :					\
3516
+	is_uv(UV2) ? 0x16000d0UL :					\
3517
+	0)
3518
+
3519
+
3520
+/* UVXH common defines */
3521
+#define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 24
3522
+#define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3523
+
3524
+
3525
+union uvh_rh_gam_alias_0_redirect_config_u {
3526
+	unsigned long	v;
3527
+
3528
+	/* UVH common struct */
3529
+	struct uvh_rh_gam_alias_0_redirect_config_s {
3530
+		unsigned long	rsvd_0_23:24;
3531
+		unsigned long	dest_base:22;			/* RW */
3532
+		unsigned long	rsvd_46_63:18;
3533
+	} s;
3534
+
3535
+	/* UVXH common struct */
3536
+	struct uvxh_rh_gam_alias_0_redirect_config_s {
3537
+		unsigned long	rsvd_0_23:24;
3538
+		unsigned long	dest_base:22;			/* RW */
3539
+		unsigned long	rsvd_46_63:18;
3540
+	} sx;
3541
+
3542
+	/* UV4 unique struct */
3543
+	struct uv4h_rh_gam_alias_0_redirect_config_s {
3544
+		unsigned long	rsvd_0_23:24;
3545
+		unsigned long	dest_base:22;			/* RW */
3546
+		unsigned long	rsvd_46_63:18;
3547
+	} s4;
3548
+
3549
+	/* UV3 unique struct */
3550
+	struct uv3h_rh_gam_alias_0_redirect_config_s {
3551
+		unsigned long	rsvd_0_23:24;
3552
+		unsigned long	dest_base:22;			/* RW */
3553
+		unsigned long	rsvd_46_63:18;
3554
+	} s3;
3555
+
3556
+	/* UV2 unique struct */
3557
+	struct uv2h_rh_gam_alias_0_redirect_config_s {
3558
+		unsigned long	rsvd_0_23:24;
3559
+		unsigned long	dest_base:22;			/* RW */
3560
+		unsigned long	rsvd_46_63:18;
3561
+	} s2;
3562
+};
3563
+
3564
+/* ========================================================================= */
3565
+/*                    UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG                      */
3566
+/* ========================================================================= */
3567
+#define UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG (				\
3568
+	is_uv(UV4) ? 0x4800d8UL :					\
3569
+	is_uv(UV3) ? 0x16000d8UL :					\
3570
+	is_uv(UV2) ? 0x16000d8UL :					\
3571
+	0)
3572
+
3573
+
3574
+/* UVXH common defines */
3575
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_SHFT	24
3576
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_MASK	0x00000000ff000000UL
3577
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_SHFT	48
3578
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_MASK	0x001f000000000000UL
3579
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_SHFT	63
3580
+#define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3581
+
3582
+
3583
+union uvh_rh_gam_alias_1_overlay_config_u {
3584
+	unsigned long	v;
3585
+
3586
+	/* UVH common struct */
3587
+	struct uvh_rh_gam_alias_1_overlay_config_s {
3588
+		unsigned long	rsvd_0_23:24;
3589
+		unsigned long	base:8;				/* RW */
3590
+		unsigned long	rsvd_32_47:16;
3591
+		unsigned long	m_alias:5;			/* RW */
3592
+		unsigned long	rsvd_53_62:10;
3593
+		unsigned long	enable:1;			/* RW */
3594
+	} s;
3595
+
3596
+	/* UVXH common struct */
3597
+	struct uvxh_rh_gam_alias_1_overlay_config_s {
3598
+		unsigned long	rsvd_0_23:24;
3599
+		unsigned long	base:8;				/* RW */
3600
+		unsigned long	rsvd_32_47:16;
3601
+		unsigned long	m_alias:5;			/* RW */
3602
+		unsigned long	rsvd_53_62:10;
3603
+		unsigned long	enable:1;			/* RW */
3604
+	} sx;
3605
+
3606
+	/* UV4 unique struct */
3607
+	struct uv4h_rh_gam_alias_1_overlay_config_s {
3608
+		unsigned long	rsvd_0_23:24;
3609
+		unsigned long	base:8;				/* RW */
3610
+		unsigned long	rsvd_32_47:16;
3611
+		unsigned long	m_alias:5;			/* RW */
3612
+		unsigned long	rsvd_53_62:10;
3613
+		unsigned long	enable:1;			/* RW */
3614
+	} s4;
3615
+
3616
+	/* UV3 unique struct */
3617
+	struct uv3h_rh_gam_alias_1_overlay_config_s {
3618
+		unsigned long	rsvd_0_23:24;
3619
+		unsigned long	base:8;				/* RW */
3620
+		unsigned long	rsvd_32_47:16;
3621
+		unsigned long	m_alias:5;			/* RW */
3622
+		unsigned long	rsvd_53_62:10;
3623
+		unsigned long	enable:1;			/* RW */
3624
+	} s3;
3625
+
3626
+	/* UV2 unique struct */
3627
+	struct uv2h_rh_gam_alias_1_overlay_config_s {
3628
+		unsigned long	rsvd_0_23:24;
3629
+		unsigned long	base:8;				/* RW */
3630
+		unsigned long	rsvd_32_47:16;
3631
+		unsigned long	m_alias:5;			/* RW */
3632
+		unsigned long	rsvd_53_62:10;
3633
+		unsigned long	enable:1;			/* RW */
3634
+	} s2;
3635
+};
3636
+
3637
+/* ========================================================================= */
3638
+/*                    UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG                     */
3639
+/* ========================================================================= */
3640
+#define UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG (				\
3641
+	is_uv(UV4) ? 0x4800e0UL :					\
3642
+	is_uv(UV3) ? 0x16000e0UL :					\
3643
+	is_uv(UV2) ? 0x16000e0UL :					\
3644
+	0)
3645
+
3646
+
3647
+/* UVXH common defines */
3648
+#define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_SHFT 24
3649
+#define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3650
+
3651
+
3652
+union uvh_rh_gam_alias_1_redirect_config_u {
3653
+	unsigned long	v;
3654
+
3655
+	/* UVH common struct */
3656
+	struct uvh_rh_gam_alias_1_redirect_config_s {
3657
+		unsigned long	rsvd_0_23:24;
3658
+		unsigned long	dest_base:22;			/* RW */
3659
+		unsigned long	rsvd_46_63:18;
3660
+	} s;
3661
+
3662
+	/* UVXH common struct */
3663
+	struct uvxh_rh_gam_alias_1_redirect_config_s {
3664
+		unsigned long	rsvd_0_23:24;
3665
+		unsigned long	dest_base:22;			/* RW */
3666
+		unsigned long	rsvd_46_63:18;
3667
+	} sx;
3668
+
3669
+	/* UV4 unique struct */
3670
+	struct uv4h_rh_gam_alias_1_redirect_config_s {
3671
+		unsigned long	rsvd_0_23:24;
3672
+		unsigned long	dest_base:22;			/* RW */
3673
+		unsigned long	rsvd_46_63:18;
3674
+	} s4;
3675
+
3676
+	/* UV3 unique struct */
3677
+	struct uv3h_rh_gam_alias_1_redirect_config_s {
3678
+		unsigned long	rsvd_0_23:24;
3679
+		unsigned long	dest_base:22;			/* RW */
3680
+		unsigned long	rsvd_46_63:18;
3681
+	} s3;
3682
+
3683
+	/* UV2 unique struct */
3684
+	struct uv2h_rh_gam_alias_1_redirect_config_s {
3685
+		unsigned long	rsvd_0_23:24;
3686
+		unsigned long	dest_base:22;			/* RW */
3687
+		unsigned long	rsvd_46_63:18;
3688
+	} s2;
3689
+};
3690
+
3691
+/* ========================================================================= */
3692
+/*                    UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG                      */
3693
+/* ========================================================================= */
3694
+#define UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG (				\
3695
+	is_uv(UV4) ? 0x4800e8UL :					\
3696
+	is_uv(UV3) ? 0x16000e8UL :					\
3697
+	is_uv(UV2) ? 0x16000e8UL :					\
3698
+	0)
3699
+
3700
+
3701
+/* UVXH common defines */
3702
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_SHFT	24
3703
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_MASK	0x00000000ff000000UL
3704
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_SHFT	48
3705
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_MASK	0x001f000000000000UL
3706
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_SHFT	63
3707
+#define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3708
+
3709
+
3710
+union uvh_rh_gam_alias_2_overlay_config_u {
3711
+	unsigned long	v;
3712
+
3713
+	/* UVH common struct */
3714
+	struct uvh_rh_gam_alias_2_overlay_config_s {
3715
+		unsigned long	rsvd_0_23:24;
3716
+		unsigned long	base:8;				/* RW */
3717
+		unsigned long	rsvd_32_47:16;
3718
+		unsigned long	m_alias:5;			/* RW */
3719
+		unsigned long	rsvd_53_62:10;
3720
+		unsigned long	enable:1;			/* RW */
3721
+	} s;
3722
+
3723
+	/* UVXH common struct */
3724
+	struct uvxh_rh_gam_alias_2_overlay_config_s {
3725
+		unsigned long	rsvd_0_23:24;
3726
+		unsigned long	base:8;				/* RW */
3727
+		unsigned long	rsvd_32_47:16;
3728
+		unsigned long	m_alias:5;			/* RW */
3729
+		unsigned long	rsvd_53_62:10;
3730
+		unsigned long	enable:1;			/* RW */
3731
+	} sx;
3732
+
3733
+	/* UV4 unique struct */
3734
+	struct uv4h_rh_gam_alias_2_overlay_config_s {
3735
+		unsigned long	rsvd_0_23:24;
3736
+		unsigned long	base:8;				/* RW */
3737
+		unsigned long	rsvd_32_47:16;
3738
+		unsigned long	m_alias:5;			/* RW */
3739
+		unsigned long	rsvd_53_62:10;
3740
+		unsigned long	enable:1;			/* RW */
3741
+	} s4;
3742
+
3743
+	/* UV3 unique struct */
3744
+	struct uv3h_rh_gam_alias_2_overlay_config_s {
3745
+		unsigned long	rsvd_0_23:24;
3746
+		unsigned long	base:8;				/* RW */
3747
+		unsigned long	rsvd_32_47:16;
3748
+		unsigned long	m_alias:5;			/* RW */
3749
+		unsigned long	rsvd_53_62:10;
3750
+		unsigned long	enable:1;			/* RW */
3751
+	} s3;
3752
+
3753
+	/* UV2 unique struct */
3754
+	struct uv2h_rh_gam_alias_2_overlay_config_s {
3755
+		unsigned long	rsvd_0_23:24;
3756
+		unsigned long	base:8;				/* RW */
3757
+		unsigned long	rsvd_32_47:16;
3758
+		unsigned long	m_alias:5;			/* RW */
3759
+		unsigned long	rsvd_53_62:10;
3760
+		unsigned long	enable:1;			/* RW */
3761
+	} s2;
3762
+};
3763
+
3764
+/* ========================================================================= */
3765
+/*                    UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG                     */
3766
+/* ========================================================================= */
3767
+#define UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG (				\
3768
+	is_uv(UV4) ? 0x4800f0UL :					\
3769
+	is_uv(UV3) ? 0x16000f0UL :					\
3770
+	is_uv(UV2) ? 0x16000f0UL :					\
3771
+	0)
3772
+
3773
+
3774
+/* UVXH common defines */
3775
+#define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_SHFT 24
3776
+#define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3777
+
3778
+
3779
+union uvh_rh_gam_alias_2_redirect_config_u {
3780
+	unsigned long	v;
3781
+
3782
+	/* UVH common struct */
3783
+	struct uvh_rh_gam_alias_2_redirect_config_s {
3784
+		unsigned long	rsvd_0_23:24;
3785
+		unsigned long	dest_base:22;			/* RW */
3786
+		unsigned long	rsvd_46_63:18;
3787
+	} s;
3788
+
3789
+	/* UVXH common struct */
3790
+	struct uvxh_rh_gam_alias_2_redirect_config_s {
3791
+		unsigned long	rsvd_0_23:24;
3792
+		unsigned long	dest_base:22;			/* RW */
3793
+		unsigned long	rsvd_46_63:18;
3794
+	} sx;
3795
+
3796
+	/* UV4 unique struct */
3797
+	struct uv4h_rh_gam_alias_2_redirect_config_s {
3798
+		unsigned long	rsvd_0_23:24;
3799
+		unsigned long	dest_base:22;			/* RW */
3800
+		unsigned long	rsvd_46_63:18;
3801
+	} s4;
3802
+
3803
+	/* UV3 unique struct */
3804
+	struct uv3h_rh_gam_alias_2_redirect_config_s {
3805
+		unsigned long	rsvd_0_23:24;
3806
+		unsigned long	dest_base:22;			/* RW */
3807
+		unsigned long	rsvd_46_63:18;
3808
+	} s3;
3809
+
3810
+	/* UV2 unique struct */
3811
+	struct uv2h_rh_gam_alias_2_redirect_config_s {
3812
+		unsigned long	rsvd_0_23:24;
3813
+		unsigned long	dest_base:22;			/* RW */
3814
+		unsigned long	rsvd_46_63:18;
3815
+	} s2;
3816
+};
3817
+
3818
+/* ========================================================================= */
3819
+/*                      UVH_RH_GAM_GRU_OVERLAY_CONFIG                        */
3820
+/* ========================================================================= */
3821
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG (					\
3822
+	is_uv(UV4) ? 0x480010UL :					\
3823
+	is_uv(UV3) ? 0x1600010UL :					\
3824
+	is_uv(UV2) ? 0x1600010UL :					\
3825
+	0)
3826
+
3827
+
3828
+/* UVXH common defines */
3829
+#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT	52
3830
+#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK	0x00f0000000000000UL
3831
+#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT	63
3832
+#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3833
+
3834
+/* UV4A unique defines */
3835
+#define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	26
3836
+#define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x000ffffffc000000UL
3837
+
3838
+/* UV4 unique defines */
3839
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	26
3840
+#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x00003ffffc000000UL
3841
+
3842
+/* UV3 unique defines */
3843
+#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	28
3844
+#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x00003ffff0000000UL
3845
+#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_SHFT	62
3846
+#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_MASK	0x4000000000000000UL
3847
+
3848
+/* UV2 unique defines */
3849
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	28
3850
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x00003ffff0000000UL
3851
+
3852
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK (			\
3853
+	is_uv(UV4A) ? 0x000ffffffc000000UL :				\
3854
+	is_uv(UV4) ? 0x00003ffffc000000UL :				\
3855
+	is_uv(UV3) ? 0x00003ffff0000000UL :				\
3856
+	is_uv(UV2) ? 0x00003ffff0000000UL :				\
3857
+	0)
3858
+#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT (			\
3859
+	is_uv(UV4) ? 26 :						\
3860
+	is_uv(UV3) ? 28 :						\
3861
+	is_uv(UV2) ? 28 :						\
3862
+	-1)
3863
+
3864
+union uvh_rh_gam_gru_overlay_config_u {
3865
+	unsigned long	v;
3866
+
3867
+	/* UVH common struct */
3868
+	struct uvh_rh_gam_gru_overlay_config_s {
3869
+		unsigned long	rsvd_0_45:46;
3870
+		unsigned long	rsvd_46_51:6;
3871
+		unsigned long	n_gru:4;			/* RW */
3872
+		unsigned long	rsvd_56_62:7;
3873
+		unsigned long	enable:1;			/* RW */
3874
+	} s;
3875
+
3876
+	/* UVXH common struct */
3877
+	struct uvxh_rh_gam_gru_overlay_config_s {
3878
+		unsigned long	rsvd_0_45:46;
3879
+		unsigned long	rsvd_46_51:6;
3880
+		unsigned long	n_gru:4;			/* RW */
3881
+		unsigned long	rsvd_56_62:7;
3882
+		unsigned long	enable:1;			/* RW */
3883
+	} sx;
3884
+
3885
+	/* UV4A unique struct */
3886
+	struct uv4ah_rh_gam_gru_overlay_config_s {
3887
+		unsigned long	rsvd_0_24:25;
3888
+		unsigned long	undef_25:1;			/* Undefined */
3889
+		unsigned long	base:26;			/* RW */
3890
+		unsigned long	n_gru:4;			/* RW */
3891
+		unsigned long	rsvd_56_62:7;
3892
+		unsigned long	enable:1;			/* RW */
3893
+	} s4a;
3894
+
3895
+	/* UV4 unique struct */
3896
+	struct uv4h_rh_gam_gru_overlay_config_s {
3897
+		unsigned long	rsvd_0_24:25;
3898
+		unsigned long	undef_25:1;			/* Undefined */
3899
+		unsigned long	base:20;			/* RW */
3900
+		unsigned long	rsvd_46_51:6;
3901
+		unsigned long	n_gru:4;			/* RW */
3902
+		unsigned long	rsvd_56_62:7;
3903
+		unsigned long	enable:1;			/* RW */
3904
+	} s4;
3905
+
3906
+	/* UV3 unique struct */
3907
+	struct uv3h_rh_gam_gru_overlay_config_s {
3908
+		unsigned long	rsvd_0_27:28;
3909
+		unsigned long	base:18;			/* RW */
3910
+		unsigned long	rsvd_46_51:6;
3911
+		unsigned long	n_gru:4;			/* RW */
3912
+		unsigned long	rsvd_56_61:6;
3913
+		unsigned long	mode:1;				/* RW */
3914
+		unsigned long	enable:1;			/* RW */
3915
+	} s3;
3916
+
3917
+	/* UV2 unique struct */
3918
+	struct uv2h_rh_gam_gru_overlay_config_s {
3919
+		unsigned long	rsvd_0_27:28;
3920
+		unsigned long	base:18;			/* RW */
3921
+		unsigned long	rsvd_46_51:6;
3922
+		unsigned long	n_gru:4;			/* RW */
3923
+		unsigned long	rsvd_56_62:7;
3924
+		unsigned long	enable:1;			/* RW */
3925
+	} s2;
3926
+};
3927
+
3928
+/* ========================================================================= */
3929
+/*                     UVH_RH_GAM_MMIOH_OVERLAY_CONFIG                       */
3930
+/* ========================================================================= */
3931
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG (				\
3932
+	is_uv(UV2) ? 0x1600030UL :					\
3933
+	0)
3934
+
3935
+
3936
+
3937
+/* UV2 unique defines */
3938
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT	27
3939
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_MASK	0x00003ffff8000000UL
3940
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_SHFT	46
3941
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_MASK	0x000fc00000000000UL
3942
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_SHFT	52
3943
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_MASK	0x00f0000000000000UL
3944
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_SHFT	63
3945
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
3946
+
3947
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT (			\
3948
+	is_uv(UV2) ? 27 :						\
3949
+	uv_undefined("UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT"))
3950
+
3951
+union uvh_rh_gam_mmioh_overlay_config_u {
3952
+	unsigned long	v;
3953
+
3954
+	/* UVH common struct */
3955
+	struct uvh_rh_gam_mmioh_overlay_config_s {
3956
+		unsigned long	rsvd_0_26:27;
3957
+		unsigned long	base:19;			/* RW */
3958
+		unsigned long	m_io:6;				/* RW */
3959
+		unsigned long	n_io:4;				/* RW */
3960
+		unsigned long	rsvd_56_62:7;
3961
+		unsigned long	enable:1;			/* RW */
3962
+	} s;
3963
+
3964
+	/* UVXH common struct */
3965
+	struct uvxh_rh_gam_mmioh_overlay_config_s {
3966
+		unsigned long	rsvd_0_26:27;
3967
+		unsigned long	base:19;			/* RW */
3968
+		unsigned long	m_io:6;				/* RW */
3969
+		unsigned long	n_io:4;				/* RW */
3970
+		unsigned long	rsvd_56_62:7;
3971
+		unsigned long	enable:1;			/* RW */
3972
+	} sx;
3973
+
3974
+	/* UV2 unique struct */
3975
+	struct uv2h_rh_gam_mmioh_overlay_config_s {
3976
+		unsigned long	rsvd_0_26:27;
3977
+		unsigned long	base:19;			/* RW */
3978
+		unsigned long	m_io:6;				/* RW */
3979
+		unsigned long	n_io:4;				/* RW */
3980
+		unsigned long	rsvd_56_62:7;
3981
+		unsigned long	enable:1;			/* RW */
3982
+	} s2;
3983
+};
3984
+
3985
+/* ========================================================================= */
3986
+/*                     UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0                      */
3987
+/* ========================================================================= */
3988
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0 (				\
3989
+	is_uv(UV4) ? 0x483000UL :					\
3990
+	is_uv(UV3) ? 0x1603000UL :					\
3991
+	0)
3992
+
3993
+/* UV4A unique defines */
3994
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT	26
3995
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK	0x000ffffffc000000UL
3996
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT	52
3997
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK	0x03f0000000000000UL
3998
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT	63
3999
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK	0x8000000000000000UL
4000
+
4001
+/* UV4 unique defines */
4002
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT	26
4003
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK	0x00003ffffc000000UL
4004
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT	46
4005
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK	0x000fc00000000000UL
4006
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT	63
4007
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK	0x8000000000000000UL
4008
+
4009
+/* UV3 unique defines */
4010
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT	26
4011
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK	0x00003ffffc000000UL
4012
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT	46
4013
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK	0x000fc00000000000UL
4014
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT	63
4015
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK	0x8000000000000000UL
4016
+
4017
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK (			\
4018
+	is_uv(UV4A) ? 0x000ffffffc000000UL :				\
4019
+	is_uv(UV4) ? 0x00003ffffc000000UL :				\
4020
+	is_uv(UV3) ? 0x00003ffffc000000UL :				\
4021
+	0)
4022
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT (			\
4023
+	is_uv(UV4) ? 26 :						\
4024
+	is_uv(UV3) ? 26 :						\
4025
+	-1)
4026
+
4027
+union uvh_rh_gam_mmioh_overlay_config0_u {
4028
+	unsigned long	v;
4029
+
4030
+	/* UVH common struct */
4031
+	struct uvh_rh_gam_mmioh_overlay_config0_s {
4032
+		unsigned long	rsvd_0_25:26;
4033
+		unsigned long	base:20;			/* RW */
4034
+		unsigned long	m_io:6;				/* RW */
4035
+		unsigned long	n_io:4;
4036
+		unsigned long	rsvd_56_62:7;
4037
+		unsigned long	enable:1;			/* RW */
4038
+	} s;
4039
+
4040
+	/* UVXH common struct */
4041
+	struct uvxh_rh_gam_mmioh_overlay_config0_s {
4042
+		unsigned long	rsvd_0_25:26;
4043
+		unsigned long	base:20;			/* RW */
4044
+		unsigned long	m_io:6;				/* RW */
4045
+		unsigned long	n_io:4;
4046
+		unsigned long	rsvd_56_62:7;
4047
+		unsigned long	enable:1;			/* RW */
4048
+	} sx;
4049
+
4050
+	/* UV4A unique struct */
4051
+	struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s {
4052
+		unsigned long	rsvd_0_25:26;
4053
+		unsigned long	base:26;			/* RW */
4054
+		unsigned long	m_io:6;				/* RW */
4055
+		unsigned long	n_io:4;
4056
+		unsigned long	undef_62:1;			/* Undefined */
4057
+		unsigned long	enable:1;			/* RW */
4058
+	} s4a;
4059
+
4060
+	/* UV4 unique struct */
4061
+	struct uv4h_rh_gam_mmioh_overlay_config0_s {
4062
+		unsigned long	rsvd_0_25:26;
4063
+		unsigned long	base:20;			/* RW */
4064
+		unsigned long	m_io:6;				/* RW */
4065
+		unsigned long	n_io:4;
4066
+		unsigned long	rsvd_56_62:7;
4067
+		unsigned long	enable:1;			/* RW */
4068
+	} s4;
4069
+
4070
+	/* UV3 unique struct */
4071
+	struct uv3h_rh_gam_mmioh_overlay_config0_s {
4072
+		unsigned long	rsvd_0_25:26;
4073
+		unsigned long	base:20;			/* RW */
4074
+		unsigned long	m_io:6;				/* RW */
4075
+		unsigned long	n_io:4;
4076
+		unsigned long	rsvd_56_62:7;
4077
+		unsigned long	enable:1;			/* RW */
4078
+	} s3;
4079
+};
4080
+
4081
+/* ========================================================================= */
4082
+/*                     UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1                      */
4083
+/* ========================================================================= */
4084
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1 (				\
4085
+	is_uv(UV4) ? 0x484000UL :					\
4086
+	is_uv(UV3) ? 0x1604000UL :					\
4087
+	0)
4088
+
4089
+/* UV4A unique defines */
4090
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT	26
4091
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK	0x000ffffffc000000UL
4092
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT	52
4093
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK	0x03f0000000000000UL
4094
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT	63
4095
+#define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK	0x8000000000000000UL
4096
+
4097
+/* UV4 unique defines */
4098
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT	26
4099
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK	0x00003ffffc000000UL
4100
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT	46
4101
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK	0x000fc00000000000UL
4102
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT	63
4103
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK	0x8000000000000000UL
4104
+
4105
+/* UV3 unique defines */
4106
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT	26
4107
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK	0x00003ffffc000000UL
4108
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT	46
4109
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK	0x000fc00000000000UL
4110
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT	63
4111
+#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK	0x8000000000000000UL
4112
+
4113
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK (			\
4114
+	is_uv(UV4A) ? 0x000ffffffc000000UL : \
4115
+	is_uv(UV4) ? 0x00003ffffc000000UL :				\
4116
+	is_uv(UV3) ? 0x00003ffffc000000UL :				\
4117
+	0)
4118
+#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT (			\
4119
+	is_uv(UV4) ? 26 :						\
4120
+	is_uv(UV3) ? 26 :						\
4121
+	-1)
4122
+
4123
+union uvh_rh_gam_mmioh_overlay_config1_u {
4124
+	unsigned long	v;
4125
+
4126
+	/* UVH common struct */
4127
+	struct uvh_rh_gam_mmioh_overlay_config1_s {
4128
+		unsigned long	rsvd_0_25:26;
4129
+		unsigned long	base:20;			/* RW */
4130
+		unsigned long	m_io:6;				/* RW */
4131
+		unsigned long	n_io:4;
4132
+		unsigned long	rsvd_56_62:7;
4133
+		unsigned long	enable:1;			/* RW */
4134
+	} s;
4135
+
4136
+	/* UVXH common struct */
4137
+	struct uvxh_rh_gam_mmioh_overlay_config1_s {
4138
+		unsigned long	rsvd_0_25:26;
4139
+		unsigned long	base:20;			/* RW */
4140
+		unsigned long	m_io:6;				/* RW */
4141
+		unsigned long	n_io:4;
4142
+		unsigned long	rsvd_56_62:7;
4143
+		unsigned long	enable:1;			/* RW */
4144
+	} sx;
4145
+
4146
+	/* UV4A unique struct */
4147
+	struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s {
4148
+		unsigned long	rsvd_0_25:26;
4149
+		unsigned long	base:26;			/* RW */
4150
+		unsigned long	m_io:6;				/* RW */
4151
+		unsigned long	n_io:4;
4152
+		unsigned long	undef_62:1;			/* Undefined */
4153
+		unsigned long	enable:1;			/* RW */
4154
+	} s4a;
4155
+
4156
+	/* UV4 unique struct */
4157
+	struct uv4h_rh_gam_mmioh_overlay_config1_s {
4158
+		unsigned long	rsvd_0_25:26;
4159
+		unsigned long	base:20;			/* RW */
4160
+		unsigned long	m_io:6;				/* RW */
4161
+		unsigned long	n_io:4;
4162
+		unsigned long	rsvd_56_62:7;
4163
+		unsigned long	enable:1;			/* RW */
4164
+	} s4;
4165
+
4166
+	/* UV3 unique struct */
4167
+	struct uv3h_rh_gam_mmioh_overlay_config1_s {
4168
+		unsigned long	rsvd_0_25:26;
4169
+		unsigned long	base:20;			/* RW */
4170
+		unsigned long	m_io:6;				/* RW */
4171
+		unsigned long	n_io:4;
4172
+		unsigned long	rsvd_56_62:7;
4173
+		unsigned long	enable:1;			/* RW */
4174
+	} s3;
4175
+};
4176
+
4177
+/* ========================================================================= */
4178
+/*                    UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0                      */
4179
+/* ========================================================================= */
4180
+#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0 (				\
4181
+	is_uv(UV4) ? 0x483800UL :					\
4182
+	is_uv(UV3) ? 0x1603800UL :					\
4183
+	0)
4184
+
4185
+#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH (			\
4186
+	is_uv(UV4) ? 128 :						\
4187
+	is_uv(UV3) ? 128 :						\
4188
+	0)
4189
+
4190
+/* UV4A unique defines */
4191
+#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT	0
4192
+#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK	0x0000000000000fffUL
4193
+
4194
+/* UV4 unique defines */
4195
+#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT	0
4196
+#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK	0x0000000000007fffUL
4197
+
4198
+/* UV3 unique defines */
4199
+#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT	0
4200
+#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK	0x0000000000007fffUL
4201
+
4202
+
4203
+union uvh_rh_gam_mmioh_redirect_config0_u {
4204
+	unsigned long	v;
4205
+
4206
+	/* UVH common struct */
4207
+	struct uvh_rh_gam_mmioh_redirect_config0_s {
4208
+		unsigned long	nasid:15;			/* RW */
4209
+		unsigned long	rsvd_15_63:49;
4210
+	} s;
4211
+
4212
+	/* UVXH common struct */
4213
+	struct uvxh_rh_gam_mmioh_redirect_config0_s {
4214
+		unsigned long	nasid:15;			/* RW */
4215
+		unsigned long	rsvd_15_63:49;
4216
+	} sx;
4217
+
4218
+	struct uv4ah_rh_gam_mmioh_redirect_config0_s {
4219
+		unsigned long	nasid:12;			/* RW */
4220
+		unsigned long	rsvd_12_63:52;
4221
+	} s4a;
4222
+
4223
+	/* UV4 unique struct */
4224
+	struct uv4h_rh_gam_mmioh_redirect_config0_s {
4225
+		unsigned long	nasid:15;			/* RW */
4226
+		unsigned long	rsvd_15_63:49;
4227
+	} s4;
4228
+
4229
+	/* UV3 unique struct */
4230
+	struct uv3h_rh_gam_mmioh_redirect_config0_s {
4231
+		unsigned long	nasid:15;			/* RW */
4232
+		unsigned long	rsvd_15_63:49;
4233
+	} s3;
4234
+};
4235
+
4236
+/* ========================================================================= */
4237
+/*                    UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1                      */
4238
+/* ========================================================================= */
4239
+#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1 (				\
4240
+	is_uv(UV4) ? 0x484800UL :					\
4241
+	is_uv(UV3) ? 0x1604800UL :					\
4242
+	0)
4243
+
4244
+#define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH (			\
4245
+	is_uv(UV4) ? 128 :						\
4246
+	is_uv(UV3) ? 128 :						\
4247
+	0)
4248
+
4249
+/* UV4A unique defines */
4250
+#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT	0
4251
+#define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK	0x0000000000000fffUL
4252
+
4253
+/* UV4 unique defines */
4254
+#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT	0
4255
+#define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK	0x0000000000007fffUL
4256
+
4257
+/* UV3 unique defines */
4258
+#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT	0
4259
+#define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK	0x0000000000007fffUL
4260
+
4261
+
4262
+union uvh_rh_gam_mmioh_redirect_config1_u {
4263
+	unsigned long	v;
4264
+
4265
+	/* UVH common struct */
4266
+	struct uvh_rh_gam_mmioh_redirect_config1_s {
4267
+		unsigned long	nasid:15;			/* RW */
4268
+		unsigned long	rsvd_15_63:49;
4269
+	} s;
4270
+
4271
+	/* UVXH common struct */
4272
+	struct uvxh_rh_gam_mmioh_redirect_config1_s {
4273
+		unsigned long	nasid:15;			/* RW */
4274
+		unsigned long	rsvd_15_63:49;
4275
+	} sx;
4276
+
4277
+	struct uv4ah_rh_gam_mmioh_redirect_config1_s {
4278
+		unsigned long	nasid:12;			/* RW */
4279
+		unsigned long	rsvd_12_63:52;
4280
+	} s4a;
4281
+
4282
+	/* UV4 unique struct */
4283
+	struct uv4h_rh_gam_mmioh_redirect_config1_s {
4284
+		unsigned long	nasid:15;			/* RW */
4285
+		unsigned long	rsvd_15_63:49;
4286
+	} s4;
4287
+
4288
+	/* UV3 unique struct */
4289
+	struct uv3h_rh_gam_mmioh_redirect_config1_s {
4290
+		unsigned long	nasid:15;			/* RW */
4291
+		unsigned long	rsvd_15_63:49;
4292
+	} s3;
4293
+};
4294
+
4295
+/* ========================================================================= */
4296
+/*                      UVH_RH_GAM_MMR_OVERLAY_CONFIG                        */
4297
+/* ========================================================================= */
4298
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG (					\
4299
+	is_uv(UV4) ? 0x480028UL :					\
4300
+	is_uv(UV3) ? 0x1600028UL :					\
4301
+	is_uv(UV2) ? 0x1600028UL :					\
4302
+	0)
4303
+
4304
+
4305
+/* UVXH common defines */
4306
+#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT	26
4307
+#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK (			\
4308
+	is_uv(UV4A) ? 0x000ffffffc000000UL :				\
4309
+	is_uv(UV4) ? 0x00003ffffc000000UL :				\
4310
+	is_uv(UV3) ? 0x00003ffffc000000UL :				\
4311
+	is_uv(UV2) ? 0x00003ffffc000000UL :				\
4312
+	0)
4313
+#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT	63
4314
+#define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK	0x8000000000000000UL
4315
+
4316
+/* UV4A unique defines */
4317
+#define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT	26
4318
+#define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK	0x000ffffffc000000UL
4319
+
4320
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK (			\
4321
+	is_uv(UV4A) ? 0x000ffffffc000000UL :				\
4322
+	is_uv(UV4) ? 0x00003ffffc000000UL :				\
4323
+	is_uv(UV3) ? 0x00003ffffc000000UL :				\
4324
+	is_uv(UV2) ? 0x00003ffffc000000UL :				\
4325
+	0)
4326
+
4327
+#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT (			\
4328
+	is_uv(UV4) ? 26 :						\
4329
+	is_uv(UV3) ? 26 :						\
4330
+	is_uv(UV2) ? 26 :						\
4331
+	-1)
4332
+
4333
+union uvh_rh_gam_mmr_overlay_config_u {
4334
+	unsigned long	v;
4335
+
4336
+	/* UVH common struct */
4337
+	struct uvh_rh_gam_mmr_overlay_config_s {
4338
+		unsigned long	rsvd_0_25:26;
4339
+		unsigned long	base:20;			/* RW */
4340
+		unsigned long	rsvd_46_62:17;
4341
+		unsigned long	enable:1;			/* RW */
4342
+	} s;
4343
+
4344
+	/* UVXH common struct */
4345
+	struct uvxh_rh_gam_mmr_overlay_config_s {
4346
+		unsigned long	rsvd_0_25:26;
4347
+		unsigned long	base:20;			/* RW */
4348
+		unsigned long	rsvd_46_62:17;
4349
+		unsigned long	enable:1;			/* RW */
4350
+	} sx;
4351
+
4352
+	/* UV4 unique struct */
4353
+	struct uv4h_rh_gam_mmr_overlay_config_s {
4354
+		unsigned long	rsvd_0_25:26;
4355
+		unsigned long	base:20;			/* RW */
4356
+		unsigned long	rsvd_46_62:17;
4357
+		unsigned long	enable:1;			/* RW */
4358
+	} s4;
4359
+
4360
+	/* UV3 unique struct */
4361
+	struct uv3h_rh_gam_mmr_overlay_config_s {
4362
+		unsigned long	rsvd_0_25:26;
4363
+		unsigned long	base:20;			/* RW */
4364
+		unsigned long	rsvd_46_62:17;
4365
+		unsigned long	enable:1;			/* RW */
4366
+	} s3;
4367
+
4368
+	/* UV2 unique struct */
4369
+	struct uv2h_rh_gam_mmr_overlay_config_s {
4370
+		unsigned long	rsvd_0_25:26;
4371
+		unsigned long	base:20;			/* RW */
4372
+		unsigned long	rsvd_46_62:17;
4373
+		unsigned long	enable:1;			/* RW */
4374
+	} s2;
4375
+};
4376
+
4377
+/* ========================================================================= */
4378
+/*                                 UVH_RTC                                   */
4379
+/* ========================================================================= */
4380
+#define UVH_RTC (							\
4381
+	is_uv(UV5) ? 0xe0000UL :					\
4382
+	is_uv(UV4) ? 0xe0000UL :					\
4383
+	is_uv(UV3) ? 0x340000UL :					\
4384
+	is_uv(UV2) ? 0x340000UL :					\
4385
+	0)
4386
+
4387
+/* UVH common defines*/
4388
+#define UVH_RTC_REAL_TIME_CLOCK_SHFT			0
4389
+#define UVH_RTC_REAL_TIME_CLOCK_MASK			0x00ffffffffffffffUL
4390
+
4391
+
4392
+union uvh_rtc_u {
4393
+	unsigned long	v;
4394
+
4395
+	/* UVH common struct */
4396
+	struct uvh_rtc_s {
4397
+		unsigned long	real_time_clock:56;		/* RW */
4398
+		unsigned long	rsvd_56_63:8;
4399
+	} s;
4400
+
4401
+	/* UV5 unique struct */
4402
+	struct uv5h_rtc_s {
4403
+		unsigned long	real_time_clock:56;		/* RW */
4404
+		unsigned long	rsvd_56_63:8;
4405
+	} s5;
4406
+
4407
+	/* UV4 unique struct */
4408
+	struct uv4h_rtc_s {
4409
+		unsigned long	real_time_clock:56;		/* RW */
4410
+		unsigned long	rsvd_56_63:8;
4411
+	} s4;
4412
+
4413
+	/* UV3 unique struct */
4414
+	struct uv3h_rtc_s {
4415
+		unsigned long	real_time_clock:56;		/* RW */
4416
+		unsigned long	rsvd_56_63:8;
4417
+	} s3;
4418
+
4419
+	/* UV2 unique struct */
4420
+	struct uv2h_rtc_s {
4421
+		unsigned long	real_time_clock:56;		/* RW */
4422
+		unsigned long	rsvd_56_63:8;
4423
+	} s2;
4424
+};
4425
+
4426
+/* ========================================================================= */
4427
+/*                           UVH_RTC1_INT_CONFIG                             */
4428
+/* ========================================================================= */
4429
+#define UVH_RTC1_INT_CONFIG 0x615c0UL
4430
+
4431
+/* UVH common defines*/
4432
+#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT			0
4433
+#define UVH_RTC1_INT_CONFIG_VECTOR_MASK			0x00000000000000ffUL
4434
+#define UVH_RTC1_INT_CONFIG_DM_SHFT			8
4435
+#define UVH_RTC1_INT_CONFIG_DM_MASK			0x0000000000000700UL
4436
+#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT		11
4437
+#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK		0x0000000000000800UL
4438
+#define UVH_RTC1_INT_CONFIG_STATUS_SHFT			12
4439
+#define UVH_RTC1_INT_CONFIG_STATUS_MASK			0x0000000000001000UL
4440
+#define UVH_RTC1_INT_CONFIG_P_SHFT			13
4441
+#define UVH_RTC1_INT_CONFIG_P_MASK			0x0000000000002000UL
4442
+#define UVH_RTC1_INT_CONFIG_T_SHFT			15
4443
+#define UVH_RTC1_INT_CONFIG_T_MASK			0x0000000000008000UL
4444
+#define UVH_RTC1_INT_CONFIG_M_SHFT			16
4445
+#define UVH_RTC1_INT_CONFIG_M_MASK			0x0000000000010000UL
4446
+#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT		32
4447
+#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
4448
+
4449
+
4450
+union uvh_rtc1_int_config_u {
4451
+	unsigned long	v;
4452
+
4453
+	/* UVH common struct */
4454
+	struct uvh_rtc1_int_config_s {
4455
+		unsigned long	vector_:8;			/* RW */
4456
+		unsigned long	dm:3;				/* RW */
4457
+		unsigned long	destmode:1;			/* RW */
4458
+		unsigned long	status:1;			/* RO */
4459
+		unsigned long	p:1;				/* RO */
4460
+		unsigned long	rsvd_14:1;
4461
+		unsigned long	t:1;				/* RO */
4462
+		unsigned long	m:1;				/* RW */
4463
+		unsigned long	rsvd_17_31:15;
4464
+		unsigned long	apic_id:32;			/* RW */
4465
+	} s;
4466
+
4467
+	/* UV5 unique struct */
4468
+	struct uv5h_rtc1_int_config_s {
4469
+		unsigned long	vector_:8;			/* RW */
4470
+		unsigned long	dm:3;				/* RW */
4471
+		unsigned long	destmode:1;			/* RW */
4472
+		unsigned long	status:1;			/* RO */
4473
+		unsigned long	p:1;				/* RO */
4474
+		unsigned long	rsvd_14:1;
4475
+		unsigned long	t:1;				/* RO */
4476
+		unsigned long	m:1;				/* RW */
4477
+		unsigned long	rsvd_17_31:15;
4478
+		unsigned long	apic_id:32;			/* RW */
4479
+	} s5;
4480
+
4481
+	/* UV4 unique struct */
4482
+	struct uv4h_rtc1_int_config_s {
4483
+		unsigned long	vector_:8;			/* RW */
4484
+		unsigned long	dm:3;				/* RW */
4485
+		unsigned long	destmode:1;			/* RW */
4486
+		unsigned long	status:1;			/* RO */
4487
+		unsigned long	p:1;				/* RO */
4488
+		unsigned long	rsvd_14:1;
4489
+		unsigned long	t:1;				/* RO */
4490
+		unsigned long	m:1;				/* RW */
4491
+		unsigned long	rsvd_17_31:15;
4492
+		unsigned long	apic_id:32;			/* RW */
4493
+	} s4;
4494
+
4495
+	/* UV3 unique struct */
4496
+	struct uv3h_rtc1_int_config_s {
4497
+		unsigned long	vector_:8;			/* RW */
4498
+		unsigned long	dm:3;				/* RW */
4499
+		unsigned long	destmode:1;			/* RW */
4500
+		unsigned long	status:1;			/* RO */
4501
+		unsigned long	p:1;				/* RO */
4502
+		unsigned long	rsvd_14:1;
4503
+		unsigned long	t:1;				/* RO */
4504
+		unsigned long	m:1;				/* RW */
4505
+		unsigned long	rsvd_17_31:15;
4506
+		unsigned long	apic_id:32;			/* RW */
4507
+	} s3;
4508
+
4509
+	/* UV2 unique struct */
4510
+	struct uv2h_rtc1_int_config_s {
4511
+		unsigned long	vector_:8;			/* RW */
4512
+		unsigned long	dm:3;				/* RW */
4513
+		unsigned long	destmode:1;			/* RW */
4514
+		unsigned long	status:1;			/* RO */
4515
+		unsigned long	p:1;				/* RO */
4516
+		unsigned long	rsvd_14:1;
4517
+		unsigned long	t:1;				/* RO */
4518
+		unsigned long	m:1;				/* RW */
4519
+		unsigned long	rsvd_17_31:15;
4520
+		unsigned long	apic_id:32;			/* RW */
4521
+	} s2;
4522
+};
4523
+
4524
+/* ========================================================================= */
4525
+/*                               UVH_SCRATCH5                                */
4526
+/* ========================================================================= */
4527
+#define UVH_SCRATCH5 (							\
4528
+	is_uv(UV5) ? 0xb0200UL :					\
4529
+	is_uv(UV4) ? 0xb0200UL :					\
4530
+	is_uv(UV3) ? 0x2d0200UL :					\
4531
+	is_uv(UV2) ? 0x2d0200UL :					\
4532
+	0)
4533
+#define UV5H_SCRATCH5 0xb0200UL
4534
+#define UV4H_SCRATCH5 0xb0200UL
4535
+#define UV3H_SCRATCH5 0x2d0200UL
4536
+#define UV2H_SCRATCH5 0x2d0200UL
4537
+
4538
+/* UVH common defines*/
4539
+#define UVH_SCRATCH5_SCRATCH5_SHFT			0
4540
+#define UVH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4541
+
4542
+/* UVXH common defines */
4543
+#define UVXH_SCRATCH5_SCRATCH5_SHFT			0
4544
+#define UVXH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4545
+
4546
+/* UVYH common defines */
4547
+#define UVYH_SCRATCH5_SCRATCH5_SHFT			0
4548
+#define UVYH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4549
+
4550
+/* UV5 unique defines */
4551
+#define UV5H_SCRATCH5_SCRATCH5_SHFT			0
4552
+#define UV5H_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4553
+
4554
+/* UV4 unique defines */
4555
+#define UV4H_SCRATCH5_SCRATCH5_SHFT			0
4556
+#define UV4H_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4557
+
4558
+/* UV3 unique defines */
4559
+#define UV3H_SCRATCH5_SCRATCH5_SHFT			0
4560
+#define UV3H_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4561
+
4562
+/* UV2 unique defines */
4563
+#define UV2H_SCRATCH5_SCRATCH5_SHFT			0
4564
+#define UV2H_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4565
+
4566
+
4567
+union uvh_scratch5_u {
4568
+	unsigned long	v;
4569
+
4570
+	/* UVH common struct */
4571
+	struct uvh_scratch5_s {
4572
+		unsigned long	scratch5:64;			/* RW */
4573
+	} s;
4574
+
4575
+	/* UVXH common struct */
4576
+	struct uvxh_scratch5_s {
4577
+		unsigned long	scratch5:64;			/* RW */
4578
+	} sx;
4579
+
4580
+	/* UVYH common struct */
4581
+	struct uvyh_scratch5_s {
4582
+		unsigned long	scratch5:64;			/* RW */
4583
+	} sy;
4584
+
4585
+	/* UV5 unique struct */
4586
+	struct uv5h_scratch5_s {
4587
+		unsigned long	scratch5:64;			/* RW */
4588
+	} s5;
4589
+
4590
+	/* UV4 unique struct */
4591
+	struct uv4h_scratch5_s {
4592
+		unsigned long	scratch5:64;			/* RW */
4593
+	} s4;
4594
+
4595
+	/* UV3 unique struct */
4596
+	struct uv3h_scratch5_s {
4597
+		unsigned long	scratch5:64;			/* RW */
4598
+	} s3;
4599
+
4600
+	/* UV2 unique struct */
4601
+	struct uv2h_scratch5_s {
4602
+		unsigned long	scratch5:64;			/* RW */
4603
+	} s2;
4604
+};
4605
+
4606
+/* ========================================================================= */
4607
+/*                            UVH_SCRATCH5_ALIAS                             */
4608
+/* ========================================================================= */
4609
+#define UVH_SCRATCH5_ALIAS (						\
4610
+	is_uv(UV5) ? 0xb0208UL :					\
4611
+	is_uv(UV4) ? 0xb0208UL :					\
4612
+	is_uv(UV3) ? 0x2d0208UL :					\
4613
+	is_uv(UV2) ? 0x2d0208UL :					\
4614
+	0)
4615
+#define UV5H_SCRATCH5_ALIAS 0xb0208UL
4616
+#define UV4H_SCRATCH5_ALIAS 0xb0208UL
4617
+#define UV3H_SCRATCH5_ALIAS 0x2d0208UL
4618
+#define UV2H_SCRATCH5_ALIAS 0x2d0208UL
4619
+
4620
+
4621
+/* ========================================================================= */
4622
+/*                           UVH_SCRATCH5_ALIAS_2                            */
4623
+/* ========================================================================= */
4624
+#define UVH_SCRATCH5_ALIAS_2 (						\
4625
+	is_uv(UV5) ? 0xb0210UL :					\
4626
+	is_uv(UV4) ? 0xb0210UL :					\
4627
+	is_uv(UV3) ? 0x2d0210UL :					\
4628
+	is_uv(UV2) ? 0x2d0210UL :					\
4629
+	0)
4630
+#define UV5H_SCRATCH5_ALIAS_2 0xb0210UL
4631
+#define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
4632
+#define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
4633
+#define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
4634
+
4635
+
48274636 
48284637 #endif /* _ASM_X86_UV_UV_MMRS_H */