修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/arch/x86/include/asm/invpcid.h
..
..
@@ -12,12 +12,9 @@
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 	 * stale TLB entries and, especially if we're flushing global
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 	 * mappings, we don't want the compiler to reorder any subsequent
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 	 * memory accesses before the TLB flush.
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-	 *
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-	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
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-	 * invpcid (%rcx), %rax in long mode.
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 	 */
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-	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
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-		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");
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+	asm volatile("invpcid %[desc], %[type]"
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+		     :: [desc] "m" (desc), [type] "r" (type) : "memory");
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 }
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 #define INVPCID_TYPE_INDIV_ADDR		0