修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/arch/x86/include/asm/cpufeatures.h
..
..
@@ -13,8 +13,8 @@
13
13
 /*
14
14
  * Defines x86 CPU feature bits
15
15
  */
16
-#define NCAPINTS			19	   /* N 32-bit words worth of info */
17
-#define NBUGINTS			1	   /* N 32-bit bug flags */
16
+#define NCAPINTS			21	   /* N 32-bit words worth of info */
17
+#define NBUGINTS			2	   /* N 32-bit bug flags */
18
18
 
19
19
 /*
20
20
  * Note: If the comment begins with a quoted string, that string is used
..
..
@@ -96,7 +96,7 @@
96
96
 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
97
97
 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
98
98
 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
99
-#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */
99
+/* FREE!                                ( 3*32+17) */
100
100
 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
101
101
 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
102
102
 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
..
..
@@ -201,7 +201,7 @@
201
201
 #define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
202
202
 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
203
203
 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
204
-#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
204
+/* FREE!                                ( 7*32+10) */
205
205
 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
206
206
 #define X86_FEATURE_KERNEL_IBRS		( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
207
207
 #define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
..
..
@@ -211,7 +211,7 @@
211
211
 #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
212
212
 #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
213
213
 #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
214
-#define X86_FEATURE_SEV			( 7*32+20) /* AMD Secure Encrypted Virtualization */
214
+/* FREE!                                ( 7*32+20) */
215
215
 #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
216
216
 #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
217
217
 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
..
..
@@ -236,7 +236,6 @@
236
236
 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
237
237
 #define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
238
238
 #define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
239
-#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
240
239
 
241
240
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
242
241
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
..
..
@@ -301,6 +300,10 @@
301
300
 #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
302
301
 #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
303
302
 #define X86_FEATURE_MSR_TSX_CTRL	(11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
303
+
304
+#define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */
305
+#define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */
306
+#define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */
304
307
 
305
308
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
306
309
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
..
..
@@ -393,6 +396,17 @@
393
396
 #define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
394
397
 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
395
398
 
399
+/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
400
+#define X86_FEATURE_SME			(19*32+ 0) /* AMD Secure Memory Encryption */
401
+#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
402
+#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
403
+#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
404
+#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
405
+
406
+#define X86_FEATURE_SBPB		(20*32+27) /* "" Selective Branch Prediction Barrier */
407
+#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
408
+#define X86_FEATURE_SRSO_NO		(20*32+29) /* "" CPU is not affected by SRSO */
409
+
396
410
 /*
397
411
  * BUG word(s)
398
412
  */
..
..
@@ -433,5 +447,9 @@
433
447
 #define X86_BUG_MMIO_UNKNOWN		X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
434
448
 #define X86_BUG_RETBLEED		X86_BUG(27) /* CPU is affected by RETBleed */
435
449
 #define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
450
+#define X86_BUG_GDS			X86_BUG(29) /* CPU is affected by Gather Data Sampling */
436
451
 
452
+/* BUG word 2 */
453
+#define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* AMD SRSO bug */
454
+#define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* AMD DIV0 speculation bug */
437
455
 #endif /* _ASM_X86_CPUFEATURES_H */