修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/arch/powerpc/include/asm/cache.h
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@@ -6,7 +6,7 @@
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 /* bytes per L1 cache line */
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-#if defined(CONFIG_PPC_8xx) || defined(CONFIG_403GCX)
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+#if defined(CONFIG_PPC_8xx)
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 #define L1_CACHE_SHIFT		4
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 #define MAX_COPY_PREFETCH	1
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 #define IFETCH_ALIGN_SHIFT	2
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@@ -33,7 +33,8 @@
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 #define IFETCH_ALIGN_BYTES	(1 << IFETCH_ALIGN_SHIFT)
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-#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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+#if !defined(__ASSEMBLY__)
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+#ifdef CONFIG_PPC64
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 struct ppc_cache_info {
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 	u32 size;
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@@ -53,25 +54,52 @@
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 };
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 extern struct ppc64_caches ppc64_caches;
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-#endif /* __powerpc64__ && ! __ASSEMBLY__ */
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-#if defined(__ASSEMBLY__)
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-/*
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- * For a snooping icache, we still need a dummy icbi to purge all the
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- * prefetched instructions from the ifetch buffers. We also need a sync
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- * before the icbi to order the the actual stores to memory that might
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- * have modified instructions with the icbi.
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- */
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-#define PURGE_PREFETCHED_INS	\
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-	sync;			\
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-	icbi	0,r3;		\
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-	sync;			\
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-	isync
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+static inline u32 l1_dcache_shift(void)
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+{
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+	return ppc64_caches.l1d.log_block_size;
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+}
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+static inline u32 l1_dcache_bytes(void)
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+{
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+	return ppc64_caches.l1d.block_size;
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+}
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+
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+static inline u32 l1_icache_shift(void)
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+{
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+	return ppc64_caches.l1i.log_block_size;
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+}
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+
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+static inline u32 l1_icache_bytes(void)
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+{
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+	return ppc64_caches.l1i.block_size;
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+}
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 #else
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-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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+static inline u32 l1_dcache_shift(void)
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+{
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+	return L1_CACHE_SHIFT;
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+}
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-#ifdef CONFIG_6xx
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+static inline u32 l1_dcache_bytes(void)
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+{
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+	return L1_CACHE_BYTES;
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+}
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+
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+static inline u32 l1_icache_shift(void)
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+{
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+	return L1_CACHE_SHIFT;
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+}
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+
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+static inline u32 l1_icache_bytes(void)
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+{
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+	return L1_CACHE_BYTES;
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+}
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+
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+#endif
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+
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+#define __read_mostly __section(".data..read_mostly")
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+
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+#ifdef CONFIG_PPC_BOOK3S_32
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 extern long _get_L2CR(void);
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 extern long _get_L3CR(void);
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 extern void _set_L2CR(unsigned long);
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@@ -102,6 +130,17 @@
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 {
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 	__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
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 }
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+
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+static inline void icbi(void *addr)
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+{
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+	asm volatile ("icbi 0, %0" : : "r"(addr) : "memory");
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+}
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+
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+static inline void iccci(void *addr)
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+{
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+	asm volatile ("iccci 0, %0" : : "r"(addr) : "memory");
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+}
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+
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 #endif /* !__ASSEMBLY__ */
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 #endif /* __KERNEL__ */
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 #endif /* _ASM_POWERPC_CACHE_H */