修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
..
..
@@ -9,8 +9,6 @@
9
9
 #include <dt-bindings/gpio/uniphier-gpio.h>
10
10
 #include <dt-bindings/thermal/thermal.h>
11
11
 
12
-/memreserve/ 0x80000000 0x02000000;
13
-
14
12
 / {
15
13
 	compatible = "socionext,uniphier-ld20";
16
14
 	#address-cells = <2>;
..
..
@@ -43,7 +41,7 @@
43
41
 
44
42
 		cpu0: cpu@0 {
45
43
 			device_type = "cpu";
46
-			compatible = "arm,cortex-a72", "arm,armv8";
44
+			compatible = "arm,cortex-a72";
47
45
 			reg = <0 0x000>;
48
46
 			clocks = <&sys_clk 32>;
49
47
 			enable-method = "psci";
..
..
@@ -53,7 +51,7 @@
53
51
 
54
52
 		cpu1: cpu@1 {
55
53
 			device_type = "cpu";
56
-			compatible = "arm,cortex-a72", "arm,armv8";
54
+			compatible = "arm,cortex-a72";
57
55
 			reg = <0 0x001>;
58
56
 			clocks = <&sys_clk 32>;
59
57
 			enable-method = "psci";
..
..
@@ -63,7 +61,7 @@
63
61
 
64
62
 		cpu2: cpu@100 {
65
63
 			device_type = "cpu";
66
-			compatible = "arm,cortex-a53", "arm,armv8";
64
+			compatible = "arm,cortex-a53";
67
65
 			reg = <0 0x100>;
68
66
 			clocks = <&sys_clk 33>;
69
67
 			enable-method = "psci";
..
..
@@ -73,7 +71,7 @@
73
71
 
74
72
 		cpu3: cpu@101 {
75
73
 			device_type = "cpu";
76
-			compatible = "arm,cortex-a53", "arm,armv8";
74
+			compatible = "arm,cortex-a53";
77
75
 			reg = <0 0x101>;
78
76
 			clocks = <&sys_clk 33>;
79
77
 			enable-method = "psci";
..
..
@@ -206,15 +204,23 @@
206
204
 			cooling-maps {
207
205
 				map0 {
208
206
 					trip = <&cpu_alert>;
209
-					cooling-device = <&cpu0
210
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211
-				};
212
-				map1 {
213
-					trip = <&cpu_alert>;
214
-					cooling-device = <&cpu2
215
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216
211
 				};
217
212
 			};
213
+		};
214
+	};
215
+
216
+	reserved-memory {
217
+		#address-cells = <2>;
218
+		#size-cells = <2>;
219
+		ranges;
220
+
221
+		secure-memory@81000000 {
222
+			reg = <0x0 0x81000000 0x0 0x01000000>;
223
+			no-map;
218
224
 		};
219
225
 	};
220
226
 
..
..
@@ -223,6 +229,58 @@
223
229
 		#address-cells = <1>;
224
230
 		#size-cells = <1>;
225
231
 		ranges = <0 0 0 0xffffffff>;
232
+
233
+		spi0: spi@54006000 {
234
+			compatible = "socionext,uniphier-scssi";
235
+			status = "disabled";
236
+			reg = <0x54006000 0x100>;
237
+			#address-cells = <1>;
238
+			#size-cells = <0>;
239
+			interrupts = <0 39 4>;
240
+			pinctrl-names = "default";
241
+			pinctrl-0 = <&pinctrl_spi0>;
242
+			clocks = <&peri_clk 11>;
243
+			resets = <&peri_rst 11>;
244
+		};
245
+
246
+		spi1: spi@54006100 {
247
+			compatible = "socionext,uniphier-scssi";
248
+			status = "disabled";
249
+			reg = <0x54006100 0x100>;
250
+			#address-cells = <1>;
251
+			#size-cells = <0>;
252
+			interrupts = <0 216 4>;
253
+			pinctrl-names = "default";
254
+			pinctrl-0 = <&pinctrl_spi1>;
255
+			clocks = <&peri_clk 12>;
256
+			resets = <&peri_rst 12>;
257
+		};
258
+
259
+		spi2: spi@54006200 {
260
+			compatible = "socionext,uniphier-scssi";
261
+			status = "disabled";
262
+			reg = <0x54006200 0x100>;
263
+			#address-cells = <1>;
264
+			#size-cells = <0>;
265
+			interrupts = <0 229 4>;
266
+			pinctrl-names = "default";
267
+			pinctrl-0 = <&pinctrl_spi2>;
268
+			clocks = <&peri_clk 13>;
269
+			resets = <&peri_rst 13>;
270
+		};
271
+
272
+		spi3: spi@54006300 {
273
+			compatible = "socionext,uniphier-scssi";
274
+			status = "disabled";
275
+			reg = <0x54006300 0x100>;
276
+			#address-cells = <1>;
277
+			#size-cells = <0>;
278
+			interrupts = <0 230 4>;
279
+			pinctrl-names = "default";
280
+			pinctrl-0 = <&pinctrl_spi3>;
281
+			clocks = <&peri_clk 14>;
282
+			resets = <&peri_rst 14>;
283
+		};
226
284
 
227
285
 		serial0: serial@54006800 {
228
286
 			compatible = "socionext,uniphier-uart";
..
..
@@ -509,7 +567,7 @@
509
567
 			};
510
568
 		};
511
569
 
512
-		emmc: sdhc@5a000000 {
570
+		emmc: mmc@5a000000 {
513
571
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
514
572
 			reg = <0x5a000000 0x400>;
515
573
 			interrupts = <0 78 4>;
..
..
@@ -526,6 +584,20 @@
526
584
 			cdns,phy-input-delay-mmc-ddr = <3>;
527
585
 			cdns,phy-dll-delay-sdclk = <21>;
528
586
 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
587
+		};
588
+
589
+		sd: mmc@5a400000 {
590
+			compatible = "socionext,uniphier-sd-v3.1.1";
591
+			status = "disabled";
592
+			reg = <0x5a400000 0x800>;
593
+			interrupts = <0 76 4>;
594
+			pinctrl-names = "default";
595
+			pinctrl-0 = <&pinctrl_sd>;
596
+			clocks = <&sd_clk 0>;
597
+			reset-names = "host";
598
+			resets = <&sd_rst 0>;
599
+			bus-width = <4>;
600
+			cap-sd-highspeed;
529
601
 		};
530
602
 
531
603
 		soc_glue: soc-glue@5f800000 {
..
..
@@ -553,10 +625,62 @@
553
625
 			efuse@200 {
554
626
 				compatible = "socionext,uniphier-efuse";
555
627
 				reg = <0x200 0x68>;
628
+				#address-cells = <1>;
629
+				#size-cells = <1>;
630
+
631
+				/* USB cells */
632
+				usb_rterm0: trim@54,4 {
633
+					reg = <0x54 1>;
634
+					bits = <4 2>;
635
+				};
636
+				usb_rterm1: trim@55,4 {
637
+					reg = <0x55 1>;
638
+					bits = <4 2>;
639
+				};
640
+				usb_rterm2: trim@58,4 {
641
+					reg = <0x58 1>;
642
+					bits = <4 2>;
643
+				};
644
+				usb_rterm3: trim@59,4 {
645
+					reg = <0x59 1>;
646
+					bits = <4 2>;
647
+				};
648
+				usb_sel_t0: trim@54,0 {
649
+					reg = <0x54 1>;
650
+					bits = <0 4>;
651
+				};
652
+				usb_sel_t1: trim@55,0 {
653
+					reg = <0x55 1>;
654
+					bits = <0 4>;
655
+				};
656
+				usb_sel_t2: trim@58,0 {
657
+					reg = <0x58 1>;
658
+					bits = <0 4>;
659
+				};
660
+				usb_sel_t3: trim@59,0 {
661
+					reg = <0x59 1>;
662
+					bits = <0 4>;
663
+				};
664
+				usb_hs_i0: trim@56,0 {
665
+					reg = <0x56 1>;
666
+					bits = <0 4>;
667
+				};
668
+				usb_hs_i2: trim@5a,0 {
669
+					reg = <0x5a 1>;
670
+					bits = <0 4>;
671
+				};
556
672
 			};
557
673
 		};
558
674
 
559
-		aidet: aidet@5fc20000 {
675
+		xdmac: dma-controller@5fc10000 {
676
+			compatible = "socionext,uniphier-xdmac";
677
+			reg = <0x5fc10000 0x5300>;
678
+			interrupts = <0 188 4>;
679
+			dma-channels = <16>;
680
+			#dma-cells = <2>;
681
+		};
682
+
683
+		aidet: interrupt-controller@5fc20000 {
560
684
 			compatible = "socionext,uniphier-ld20-aidet";
561
685
 			reg = <0x5fc20000 0x200>;
562
686
 			interrupt-controller;
..
..
@@ -620,16 +744,219 @@
620
744
 			};
621
745
 		};
622
746
 
623
-		nand: nand@68000000 {
747
+		usb: usb@65a00000 {
748
+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
749
+			status = "disabled";
750
+			reg = <0x65a00000 0xcd00>;
751
+			interrupt-names = "host";
752
+			interrupts = <0 134 4>;
753
+			pinctrl-names = "default";
754
+			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
755
+				    <&pinctrl_usb2>, <&pinctrl_usb3>;
756
+			clock-names = "ref", "bus_early", "suspend";
757
+			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
758
+			resets = <&usb_rst 15>;
759
+			phys = <&usb_hsphy0>, <&usb_hsphy1>,
760
+			       <&usb_hsphy2>, <&usb_hsphy3>,
761
+			       <&usb_ssphy0>, <&usb_ssphy1>;
762
+			dr_mode = "host";
763
+		};
764
+
765
+		usb-glue@65b00000 {
766
+			compatible = "socionext,uniphier-ld20-dwc3-glue",
767
+				     "simple-mfd";
768
+			#address-cells = <1>;
769
+			#size-cells = <1>;
770
+			ranges = <0 0x65b00000 0x400>;
771
+
772
+			usb_rst: reset@0 {
773
+				compatible = "socionext,uniphier-ld20-usb3-reset";
774
+				reg = <0x0 0x4>;
775
+				#reset-cells = <1>;
776
+				clock-names = "link";
777
+				clocks = <&sys_clk 14>;
778
+				reset-names = "link";
779
+				resets = <&sys_rst 14>;
780
+			};
781
+
782
+			usb_vbus0: regulator@100 {
783
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
784
+				reg = <0x100 0x10>;
785
+				clock-names = "link";
786
+				clocks = <&sys_clk 14>;
787
+				reset-names = "link";
788
+				resets = <&sys_rst 14>;
789
+			};
790
+
791
+			usb_vbus1: regulator@110 {
792
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
793
+				reg = <0x110 0x10>;
794
+				clock-names = "link";
795
+				clocks = <&sys_clk 14>;
796
+				reset-names = "link";
797
+				resets = <&sys_rst 14>;
798
+			};
799
+
800
+			usb_vbus2: regulator@120 {
801
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
802
+				reg = <0x120 0x10>;
803
+				clock-names = "link";
804
+				clocks = <&sys_clk 14>;
805
+				reset-names = "link";
806
+				resets = <&sys_rst 14>;
807
+			};
808
+
809
+			usb_vbus3: regulator@130 {
810
+				compatible = "socionext,uniphier-ld20-usb3-regulator";
811
+				reg = <0x130 0x10>;
812
+				clock-names = "link";
813
+				clocks = <&sys_clk 14>;
814
+				reset-names = "link";
815
+				resets = <&sys_rst 14>;
816
+			};
817
+
818
+			usb_hsphy0: hs-phy@200 {
819
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
820
+				reg = <0x200 0x10>;
821
+				#phy-cells = <0>;
822
+				clock-names = "link", "phy";
823
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
824
+				reset-names = "link", "phy";
825
+				resets = <&sys_rst 14>, <&sys_rst 16>;
826
+				vbus-supply = <&usb_vbus0>;
827
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
828
+				nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
829
+					      <&usb_hs_i0>;
830
+			};
831
+
832
+			usb_hsphy1: hs-phy@210 {
833
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
834
+				reg = <0x210 0x10>;
835
+				#phy-cells = <0>;
836
+				clock-names = "link", "phy";
837
+				clocks = <&sys_clk 14>, <&sys_clk 16>;
838
+				reset-names = "link", "phy";
839
+				resets = <&sys_rst 14>, <&sys_rst 16>;
840
+				vbus-supply = <&usb_vbus1>;
841
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
842
+				nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
843
+					      <&usb_hs_i0>;
844
+			};
845
+
846
+			usb_hsphy2: hs-phy@220 {
847
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
848
+				reg = <0x220 0x10>;
849
+				#phy-cells = <0>;
850
+				clock-names = "link", "phy";
851
+				clocks = <&sys_clk 14>, <&sys_clk 17>;
852
+				reset-names = "link", "phy";
853
+				resets = <&sys_rst 14>, <&sys_rst 17>;
854
+				vbus-supply = <&usb_vbus2>;
855
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
856
+				nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
857
+					      <&usb_hs_i2>;
858
+			};
859
+
860
+			usb_hsphy3: hs-phy@230 {
861
+				compatible = "socionext,uniphier-ld20-usb3-hsphy";
862
+				reg = <0x230 0x10>;
863
+				#phy-cells = <0>;
864
+				clock-names = "link", "phy";
865
+				clocks = <&sys_clk 14>, <&sys_clk 17>;
866
+				reset-names = "link", "phy";
867
+				resets = <&sys_rst 14>, <&sys_rst 17>;
868
+				vbus-supply = <&usb_vbus3>;
869
+				nvmem-cell-names = "rterm", "sel_t", "hs_i";
870
+				nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
871
+					      <&usb_hs_i2>;
872
+			};
873
+
874
+			usb_ssphy0: ss-phy@300 {
875
+				compatible = "socionext,uniphier-ld20-usb3-ssphy";
876
+				reg = <0x300 0x10>;
877
+				#phy-cells = <0>;
878
+				clock-names = "link", "phy";
879
+				clocks = <&sys_clk 14>, <&sys_clk 18>;
880
+				reset-names = "link", "phy";
881
+				resets = <&sys_rst 14>, <&sys_rst 18>;
882
+				vbus-supply = <&usb_vbus0>;
883
+			};
884
+
885
+			usb_ssphy1: ss-phy@310 {
886
+				compatible = "socionext,uniphier-ld20-usb3-ssphy";
887
+				reg = <0x310 0x10>;
888
+				#phy-cells = <0>;
889
+				clock-names = "link", "phy";
890
+				clocks = <&sys_clk 14>, <&sys_clk 19>;
891
+				reset-names = "link", "phy";
892
+				resets = <&sys_rst 14>, <&sys_rst 19>;
893
+				vbus-supply = <&usb_vbus1>;
894
+			};
895
+		};
896
+
897
+		pcie: pcie@66000000 {
898
+			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
899
+			status = "disabled";
900
+			reg-names = "dbi", "link", "config";
901
+			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
902
+			      <0x2fff0000 0x10000>;
903
+			#address-cells = <3>;
904
+			#size-cells = <2>;
905
+			clocks = <&sys_clk 24>;
906
+			resets = <&sys_rst 24>;
907
+			num-lanes = <1>;
908
+			num-viewport = <1>;
909
+			bus-range = <0x0 0xff>;
910
+			device_type = "pci";
911
+			ranges =
912
+			/* downstream I/O */
913
+				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
914
+			/* non-prefetchable memory */
915
+				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
916
+			#interrupt-cells = <1>;
917
+			interrupt-names = "dma", "msi";
918
+			interrupts = <0 224 4>, <0 225 4>;
919
+			interrupt-map-mask = <0 0 0 7>;
920
+			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */
921
+					<0 0 0 2 &pcie_intc 1>,	/* INTB */
922
+					<0 0 0 3 &pcie_intc 2>,	/* INTC */
923
+					<0 0 0 4 &pcie_intc 3>;	/* INTD */
924
+			phy-names = "pcie-phy";
925
+			phys = <&pcie_phy>;
926
+
927
+			pcie_intc: legacy-interrupt-controller {
928
+				interrupt-controller;
929
+				#interrupt-cells = <1>;
930
+				interrupt-parent = <&gic>;
931
+				interrupts = <0 226 4>;
932
+			};
933
+		};
934
+
935
+		pcie_phy: phy@66038000 {
936
+			compatible = "socionext,uniphier-ld20-pcie-phy";
937
+			reg = <0x66038000 0x4000>;
938
+			#phy-cells = <0>;
939
+			clock-names = "link";
940
+			clocks = <&sys_clk 24>;
941
+			reset-names = "link";
942
+			resets = <&sys_rst 24>;
943
+			socionext,syscon = <&soc_glue>;
944
+		};
945
+
946
+		nand: nand-controller@68000000 {
624
947
 			compatible = "socionext,uniphier-denali-nand-v5b";
625
948
 			status = "disabled";
626
949
 			reg-names = "nand_data", "denali_reg";
627
950
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
951
+			#address-cells = <1>;
952
+			#size-cells = <0>;
628
953
 			interrupts = <0 65 4>;
629
954
 			pinctrl-names = "default";
630
955
 			pinctrl-0 = <&pinctrl_nand>;
631
-			clocks = <&sys_clk 2>;
632
-			resets = <&sys_rst 2>;
956
+			clock-names = "nand", "nand_x", "ecc";
957
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
958
+			reset-names = "nand", "reg";
959
+			resets = <&sys_rst 2>, <&sys_rst 2>;
633
960
 		};
634
961
 	};
635
962
 };