修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/Documentation/devicetree/bindings/net/xilinx_axienet.txt
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@@ -17,8 +17,15 @@
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 Required properties:
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 - compatible	: Must be one of "xlnx,axi-ethernet-1.00.a",
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 		  "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
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-- reg		: Address and length of the IO space.
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-- interrupts	: Should be a list of two interrupt, TX and RX.
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+- reg		: Address and length of the IO space, as well as the address
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+                  and length of the AXI DMA controller IO space, unless
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+                  axistream-connected is specified, in which case the reg
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+                  attribute of the node referenced by it is used.
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+- interrupts	: Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
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+		  and optionally Ethernet core. If axistream-connected is
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+		  specified, the TX/RX DMA interrupts should be on that node
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+		  instead, and only the Ethernet core interrupt is optionally
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+		  specified here.
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 - phy-handle	: Should point to the external phy device.
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 		  See ethernet.txt file in the same directory.
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 - xlnx,rxmem	: Set to allocated memory buffer for Rx/Tx in the hardware
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@@ -31,15 +38,29 @@
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 		  1 to enable partial TX checksum offload,
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 		  2 to enable full TX checksum offload
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 - xlnx,rxcsum	: Same values as xlnx,txcsum but for RX checksum offload
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+- clocks	: AXI bus clock for the device. Refer to common clock bindings.
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+		  Used to calculate MDIO clock divisor. If not specified, it is
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+		  auto-detected from the CPU clock (but only on platforms where
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+		  this is possible). New device trees should specify this - the
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+		  auto detection is only for backward compatibility.
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+- axistream-connected: Reference to another node which contains the resources
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+		       for the AXI DMA controller used by this device.
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+		       If this is specified, the DMA-related resources from that
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+		       device (DMA registers and DMA TX/RX interrupts) rather
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+		       than this one will be used.
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+ - mdio		: Child node for MDIO bus. Must be defined if PHY access is
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+		  required through the core's MDIO interface (i.e. always,
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+		  unless the PHY is accessed through a different bus).
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 Example:
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 	axi_ethernet_eth: ethernet@40c00000 {
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 		compatible = "xlnx,axi-ethernet-1.00.a";
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 		device_type = "network";
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 		interrupt-parent = <&microblaze_0_axi_intc>;
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-		interrupts = <2 0>;
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+		interrupts = <2 0 1>;
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+		clocks = <&axi_clk>;
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 		phy-mode = "mii";
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-		reg = <0x40c00000 0x40000>;
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+		reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
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 		xlnx,rxcsum = <0x2>;
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 		xlnx,rxmem = <0x800>;
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 		xlnx,txcsum = <0x2>;