.. | .. |
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11 | 11 | "mediatek,mt2701-eth": for MT2701 SoC |
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12 | 12 | "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC |
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13 | 13 | "mediatek,mt7622-eth": for MT7622 SoC |
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| 14 | + "mediatek,mt7629-eth": for MT7629 SoC |
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| 15 | + "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC |
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14 | 16 | - reg: Address and length of the register set for the device |
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15 | 17 | - interrupts: Should contain the three frame engines interrupts in numeric |
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16 | 18 | order. These are fe_int0, fe_int1 and fe_int2. |
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.. | .. |
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19 | 21 | "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC |
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20 | 22 | "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m", |
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21 | 23 | "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC |
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| 24 | + "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "sgmii_tx250m", |
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| 25 | + "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m", |
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| 26 | + "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck", |
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| 27 | + "eth2pll" : For MT7629 SoC. |
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22 | 28 | - power-domains: phandle to the power domain that the ethernet is part of |
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23 | 29 | - resets: Should contain phandles to the ethsys reset signals |
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24 | 30 | - reset-names: Should contain the names of reset signal listed in the resets |
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25 | 31 | property |
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26 | 32 | These are "fe", "gmac" and "ppe" |
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27 | 33 | - mediatek,ethsys: phandle to the syscon node that handles the port setup |
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28 | | -- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup |
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29 | | - which is required for those SoCs equipped with SGMII such as MT7622 SoC. |
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| 34 | +- mediatek,infracfg: phandle to the syscon node that handles the path from |
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| 35 | + GMAC to PHY variants, which is required for MT7629 SoC. |
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| 36 | +- mediatek,sgmiisys: a list of phandles to the syscon node that handles the |
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| 37 | + SGMII setup which is required for those SoCs equipped with SGMII such |
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| 38 | + as MT7622 and MT7629 SoC. And MT7622 have only one set of SGMII shared |
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| 39 | + by GMAC1 and GMAC2; MT7629 have two independent sets of SGMII directed |
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| 40 | + to GMAC1 and GMAC2, respectively. |
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30 | 41 | - mediatek,pctl: phandle to the syscon node that handles the ports slew rate |
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31 | 42 | and driver current: only for MT2701 and MT7623 SoC |
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32 | 43 | |
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