修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/Documentation/devicetree/bindings/fpga/fpga-region.txt
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@@ -263,7 +263,7 @@
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 			gpio@10040 {
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 				compatible = "altr,pio-1.0";
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 				reg = <0x10040 0x20>;
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-				altr,gpio-bank-width = <4>;
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+				altr,ngpio = <4>;
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 				#gpio-cells = <2>;
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 				clocks = <2>;
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 				gpio-controller;
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@@ -415,7 +415,7 @@
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 			firmware-name = "base.rbf";
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 			fpga-bridge@4400 {
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-				compatible = "altr,freeze-bridge";
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+				compatible = "altr,freeze-bridge-controller";
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 				reg = <0x4400 0x10>;
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 				fpga_region1: fpga-region1 {
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@@ -427,7 +427,7 @@
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 			};
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 			fpga-bridge@4420 {
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-				compatible = "altr,freeze-bridge";
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+				compatible = "altr,freeze-bridge-controller";
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 				reg = <0x4420 0x10>;
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 				fpga_region2: fpga-region2 {
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@@ -468,8 +468,7 @@
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 				compatible = "altr,pio-1.0";
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 				reg = <0x10040 0x20>;
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 				clocks = <0x2>;
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-				altr,gpio-bank-width = <0x4>;
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-				resetvalue = <0x0>;
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+				altr,ngpio = <0x4>;
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 				#gpio-cells = <0x2>;
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 				gpio-controller;
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 			};
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@@ -494,4 +493,4 @@
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 --
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 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
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 [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
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-[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
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+[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf