hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
kernel/Documentation/devicetree/bindings/clock/ti,cdce925.txt
....@@ -4,10 +4,10 @@
44 This binding uses the common clock binding[1].
55
66 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7
-[2] http://www.ti.com/product/cdce913
8
-[3] http://www.ti.com/product/cdce925
9
-[4] http://www.ti.com/product/cdce937
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-[5] http://www.ti.com/product/cdce949
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+[2] https://www.ti.com/product/cdce913
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+[3] https://www.ti.com/product/cdce925
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+[4] https://www.ti.com/product/cdce937
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+[5] https://www.ti.com/product/cdce949
1111
1212 The driver provides clock sources for each output Y1 through Y5.
1313
....@@ -24,6 +24,8 @@
2424 Optional properties:
2525 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
2626 board, or to compensate for external influences.
27
+- vdd-supply: A regulator node for Vdd
28
+- vddout-supply: A regulator node for Vddout
2729
2830 For all PLL1, PLL2, ... an optional child node can be used to specify spread
2931 spectrum clocking parameters for a board.
....@@ -41,6 +43,8 @@
4143 clocks = <&xtal_27Mhz>;
4244 #clock-cells = <1>;
4345 xtal-load-pf = <5>;
46
+ vdd-supply = <&1v8-reg>;
47
+ vddout-supply = <&3v3-reg>;
4448 /* PLL options to get SSC 1% centered */
4549 PLL2 {
4650 spread-spectrum = <4>;