.. | .. |
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4 | 4 | This binding uses the common clock binding[1]. |
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5 | 5 | |
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6 | 6 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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7 | | -[2] http://www.ti.com/product/cdce913 |
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8 | | -[3] http://www.ti.com/product/cdce925 |
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9 | | -[4] http://www.ti.com/product/cdce937 |
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10 | | -[5] http://www.ti.com/product/cdce949 |
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| 7 | +[2] https://www.ti.com/product/cdce913 |
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| 8 | +[3] https://www.ti.com/product/cdce925 |
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| 9 | +[4] https://www.ti.com/product/cdce937 |
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| 10 | +[5] https://www.ti.com/product/cdce949 |
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11 | 11 | |
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12 | 12 | The driver provides clock sources for each output Y1 through Y5. |
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13 | 13 | |
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.. | .. |
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24 | 24 | Optional properties: |
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25 | 25 | - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a |
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26 | 26 | board, or to compensate for external influences. |
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| 27 | +- vdd-supply: A regulator node for Vdd |
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| 28 | +- vddout-supply: A regulator node for Vddout |
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27 | 29 | |
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28 | 30 | For all PLL1, PLL2, ... an optional child node can be used to specify spread |
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29 | 31 | spectrum clocking parameters for a board. |
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.. | .. |
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41 | 43 | clocks = <&xtal_27Mhz>; |
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42 | 44 | #clock-cells = <1>; |
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43 | 45 | xtal-load-pf = <5>; |
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| 46 | + vdd-supply = <&1v8-reg>; |
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| 47 | + vddout-supply = <&3v3-reg>; |
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44 | 48 | /* PLL options to get SSC 1% centered */ |
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45 | 49 | PLL2 { |
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46 | 50 | spread-spectrum = <4>; |
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