.. | .. |
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11 | 11 | Date: March 2016 |
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12 | 12 | KernelVersion: 4.7 |
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13 | 13 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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14 | | -Description: (R) Defines the size, in 32-bit words, of the local RAM buffer. |
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| 14 | +Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer. |
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15 | 15 | The value is read directly from HW register RSZ, 0x004. |
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16 | 16 | |
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17 | 17 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts |
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18 | 18 | Date: March 2016 |
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19 | 19 | KernelVersion: 4.7 |
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20 | 20 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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21 | | -Description: (R) Shows the value held by the TMC status register. The value |
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| 21 | +Description: (Read) Shows the value held by the TMC status register. The value |
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22 | 22 | is read directly from HW register STS, 0x00C. |
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23 | 23 | |
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24 | 24 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp |
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25 | 25 | Date: March 2016 |
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26 | 26 | KernelVersion: 4.7 |
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27 | 27 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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28 | | -Description: (R) Shows the value held by the TMC RAM Read Pointer register |
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| 28 | +Description: (Read) Shows the value held by the TMC RAM Read Pointer register |
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29 | 29 | that is used to read entries from the Trace RAM over the APB |
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30 | 30 | interface. The value is read directly from HW register RRP, |
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31 | 31 | 0x014. |
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.. | .. |
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34 | 34 | Date: March 2016 |
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35 | 35 | KernelVersion: 4.7 |
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36 | 36 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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37 | | -Description: (R) Shows the value held by the TMC RAM Write Pointer register |
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| 37 | +Description: (Read) Shows the value held by the TMC RAM Write Pointer register |
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38 | 38 | that is used to sets the write pointer to write entries from |
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39 | 39 | the CoreSight bus into the Trace RAM. The value is read directly |
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40 | 40 | from HW register RWP, 0x018. |
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.. | .. |
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43 | 43 | Date: March 2016 |
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44 | 44 | KernelVersion: 4.7 |
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45 | 45 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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46 | | -Description: (R) Similar to "trigger_cntr" above except that this value is |
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| 46 | +Description: (Read) Similar to "trigger_cntr" above except that this value is |
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47 | 47 | read directly from HW register TRG, 0x01C. |
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48 | 48 | |
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49 | 49 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl |
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50 | 50 | Date: March 2016 |
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51 | 51 | KernelVersion: 4.7 |
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52 | 52 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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53 | | -Description: (R) Shows the value held by the TMC Control register. The value |
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| 53 | +Description: (Read) Shows the value held by the TMC Control register. The value |
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54 | 54 | is read directly from HW register CTL, 0x020. |
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55 | 55 | |
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56 | 56 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr |
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57 | 57 | Date: March 2016 |
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58 | 58 | KernelVersion: 4.7 |
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59 | 59 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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60 | | -Description: (R) Shows the value held by the TMC Formatter and Flush Status |
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| 60 | +Description: (Read) Shows the value held by the TMC Formatter and Flush Status |
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61 | 61 | register. The value is read directly from HW register FFSR, |
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62 | 62 | 0x300. |
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63 | 63 | |
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.. | .. |
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65 | 65 | Date: March 2016 |
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66 | 66 | KernelVersion: 4.7 |
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67 | 67 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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68 | | -Description: (R) Shows the value held by the TMC Formatter and Flush Control |
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| 68 | +Description: (Read) Shows the value held by the TMC Formatter and Flush Control |
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69 | 69 | register. The value is read directly from HW register FFCR, |
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70 | 70 | 0x304. |
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71 | 71 | |
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.. | .. |
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73 | 73 | Date: March 2016 |
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74 | 74 | KernelVersion: 4.7 |
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75 | 75 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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76 | | -Description: (R) Shows the value held by the TMC Mode register, which |
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| 76 | +Description: (Read) Shows the value held by the TMC Mode register, which |
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77 | 77 | indicate the mode the device has been configured to enact. The |
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78 | 78 | The value is read directly from the MODE register, 0x028. |
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79 | 79 | |
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.. | .. |
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81 | 81 | Date: March 2016 |
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82 | 82 | KernelVersion: 4.7 |
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83 | 83 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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84 | | -Description: (R) Indicates the capabilities of the Coresight TMC. |
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| 84 | +Description: (Read) Indicates the capabilities of the Coresight TMC. |
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85 | 85 | The value is read directly from the DEVID register, 0xFC8, |
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86 | 86 | |
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87 | 87 | What: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size |
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