.. | .. |
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4 | 4 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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5 | 5 | Description: (RW) Add/remove a sink from a trace path. There can be multiple |
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6 | 6 | source for a single sink. |
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7 | | - ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink |
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| 7 | + |
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| 8 | + ex:: |
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| 9 | + |
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| 10 | + echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink |
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8 | 11 | |
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9 | 12 | What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr |
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10 | 13 | Date: November 2014 |
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.. | .. |
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20 | 23 | Date: March 2016 |
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21 | 24 | KernelVersion: 4.7 |
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22 | 25 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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23 | | -Description: (R) Defines the depth, in words, of the trace RAM in powers of |
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| 26 | +Description: (Read) Defines the depth, in words, of the trace RAM in powers of |
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24 | 27 | 2. The value is read directly from HW register RDP, 0x004. |
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25 | 28 | |
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26 | 29 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts |
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27 | 30 | Date: March 2016 |
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28 | 31 | KernelVersion: 4.7 |
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29 | 32 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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30 | | -Description: (R) Shows the value held by the ETB status register. The value |
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| 33 | +Description: (Read) Shows the value held by the ETB status register. The value |
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31 | 34 | is read directly from HW register STS, 0x00C. |
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32 | 35 | |
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33 | 36 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp |
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34 | 37 | Date: March 2016 |
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35 | 38 | KernelVersion: 4.7 |
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36 | 39 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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37 | | -Description: (R) Shows the value held by the ETB RAM Read Pointer register |
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| 40 | +Description: (Read) Shows the value held by the ETB RAM Read Pointer register |
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38 | 41 | that is used to read entries from the Trace RAM over the APB |
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39 | 42 | interface. The value is read directly from HW register RRP, |
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40 | 43 | 0x014. |
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.. | .. |
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43 | 46 | Date: March 2016 |
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44 | 47 | KernelVersion: 4.7 |
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45 | 48 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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46 | | -Description: (R) Shows the value held by the ETB RAM Write Pointer register |
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| 49 | +Description: (Read) Shows the value held by the ETB RAM Write Pointer register |
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47 | 50 | that is used to sets the write pointer to write entries from |
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48 | 51 | the CoreSight bus into the Trace RAM. The value is read directly |
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49 | 52 | from HW register RWP, 0x018. |
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.. | .. |
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52 | 55 | Date: March 2016 |
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53 | 56 | KernelVersion: 4.7 |
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54 | 57 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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55 | | -Description: (R) Similar to "trigger_cntr" above except that this value is |
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| 58 | +Description: (Read) Similar to "trigger_cntr" above except that this value is |
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56 | 59 | read directly from HW register TRG, 0x01C. |
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57 | 60 | |
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58 | 61 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl |
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59 | 62 | Date: March 2016 |
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60 | 63 | KernelVersion: 4.7 |
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61 | 64 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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62 | | -Description: (R) Shows the value held by the ETB Control register. The value |
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| 65 | +Description: (Read) Shows the value held by the ETB Control register. The value |
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63 | 66 | is read directly from HW register CTL, 0x020. |
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64 | 67 | |
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65 | 68 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr |
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66 | 69 | Date: March 2016 |
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67 | 70 | KernelVersion: 4.7 |
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68 | 71 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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69 | | -Description: (R) Shows the value held by the ETB Formatter and Flush Status |
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| 72 | +Description: (Read) Shows the value held by the ETB Formatter and Flush Status |
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70 | 73 | register. The value is read directly from HW register FFSR, |
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71 | 74 | 0x300. |
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72 | 75 | |
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.. | .. |
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74 | 77 | Date: March 2016 |
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75 | 78 | KernelVersion: 4.7 |
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76 | 79 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> |
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77 | | -Description: (R) Shows the value held by the ETB Formatter and Flush Control |
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| 80 | +Description: (Read) Shows the value held by the ETB Formatter and Flush Control |
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78 | 81 | register. The value is read directly from HW register FFCR, |
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79 | 82 | 0x304. |
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