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2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353 
 kernel/include/dt-bindings/clock/exynos4.h
....@@ -1,13 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
23  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
34  * Author: Andrzej Hajda <a.hajda@samsung.com>
45  *
5
- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
96  * Device Tree binding constants for Exynos4 clock controller.
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-*/
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+ */
118 
129 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
1310 #define _DT_BINDINGS_CLOCK_EXYNOS_4_H
....@@ -190,32 +187,7 @@
190187 #define CLK_MIPI_HSI		349 /* Exynos4210 only */
191188 #define CLK_PIXELASYNCM0	351
192189 #define CLK_PIXELASYNCM1	352
193
-#define CLK_FIMC_LITE0		353 /* Exynos4x12 only */
194
-#define CLK_FIMC_LITE1		354 /* Exynos4x12 only */
195
-#define CLK_PPMUISPX		355 /* Exynos4x12 only */
196
-#define CLK_PPMUISPMX		356 /* Exynos4x12 only */
197
-#define CLK_FIMC_ISP		357 /* Exynos4x12 only */
198
-#define CLK_FIMC_DRC		358 /* Exynos4x12 only */
199
-#define CLK_FIMC_FD		359 /* Exynos4x12 only */
200
-#define CLK_MCUISP		360 /* Exynos4x12 only */
201
-#define CLK_GICISP		361 /* Exynos4x12 only */
202
-#define CLK_SMMU_ISP		362 /* Exynos4x12 only */
203
-#define CLK_SMMU_DRC		363 /* Exynos4x12 only */
204
-#define CLK_SMMU_FD		364 /* Exynos4x12 only */
205
-#define CLK_SMMU_LITE0		365 /* Exynos4x12 only */
206
-#define CLK_SMMU_LITE1		366 /* Exynos4x12 only */
207
-#define CLK_MCUCTL_ISP		367 /* Exynos4x12 only */
208
-#define CLK_MPWM_ISP		368 /* Exynos4x12 only */
209
-#define CLK_I2C0_ISP		369 /* Exynos4x12 only */
210
-#define CLK_I2C1_ISP		370 /* Exynos4x12 only */
211
-#define CLK_MTCADC_ISP		371 /* Exynos4x12 only */
212
-#define CLK_PWM_ISP		372 /* Exynos4x12 only */
213
-#define CLK_WDT_ISP		373 /* Exynos4x12 only */
214
-#define CLK_UART_ISP		374 /* Exynos4x12 only */
215
-#define CLK_ASYNCAXIM		375 /* Exynos4x12 only */
216
-#define CLK_SMMU_ISPCX		376 /* Exynos4x12 only */
217
-#define CLK_SPI0_ISP		377 /* Exynos4x12 only */
218
-#define CLK_SPI1_ISP		378 /* Exynos4x12 only */
190
+#define CLK_ASYNC_G3D		353 /* Exynos4x12 only */
219191 #define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
220192 #define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
221193 #define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
....@@ -257,10 +229,6 @@
257229 #define CLK_PPMUACP		415
258230 
259231 /* div clocks */
260
-#define CLK_DIV_ISP0		450 /* Exynos4x12 only */
261
-#define CLK_DIV_ISP1		451 /* Exynos4x12 only */
262
-#define CLK_DIV_MCUISP0		452 /* Exynos4x12 only */
263
-#define CLK_DIV_MCUISP1		453 /* Exynos4x12 only */
264232 #define CLK_DIV_ACLK200		454 /* Exynos4x12 only */
265233 #define CLK_DIV_ACLK400_MCUISP	455 /* Exynos4x12 only */
266234 #define CLK_DIV_ACP		456