forked from ~ljy/RK356X_SDK_RELEASE

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2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353 
 kernel/drivers/crypto/ccree/cc_driver.c
....@@ -1,5 +1,5 @@
11 // SPDX-License-Identifier: GPL-2.0
2
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
2
+/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */
33 
44 #include <linux/kernel.h>
55 #include <linux/module.h>
....@@ -14,6 +14,8 @@
1414 #include <linux/of.h>
1515 #include <linux/clk.h>
1616 #include <linux/of_address.h>
17
+#include <linux/of_device.h>
18
+#include <linux/pm_runtime.h>
1719 
1820 #include "cc_driver.h"
1921 #include "cc_request_mgr.h"
....@@ -22,7 +24,6 @@
2224 #include "cc_cipher.h"
2325 #include "cc_aead.h"
2426 #include "cc_hash.h"
25
-#include "cc_ivgen.h"
2627 #include "cc_sram_mgr.h"
2728 #include "cc_pm.h"
2829 #include "cc_fips.h"
....@@ -30,38 +31,88 @@
3031 bool cc_dump_desc;
3132 module_param_named(dump_desc, cc_dump_desc, bool, 0600);
3233 MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid");
33
-
3434 bool cc_dump_bytes;
3535 module_param_named(dump_bytes, cc_dump_bytes, bool, 0600);
3636 MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid");
37
+
38
+static bool cc_sec_disable;
39
+module_param_named(sec_disable, cc_sec_disable, bool, 0600);
40
+MODULE_PARM_DESC(cc_sec_disable, "Disable security functions");
3741 
3842 struct cc_hw_data {
3943 	char *name;
4044 	enum cc_hw_rev rev;
4145 	u32 sig;
46
+	u32 cidr_0123;
47
+	u32 pidr_0124;
48
+	int std_bodies;
49
+};
50
+
51
+#define CC_NUM_IDRS 4
52
+#define CC_HW_RESET_LOOP_COUNT 10
53
+
54
+/* Note: PIDR3 holds CMOD/Rev so ignored for HW identification purposes */
55
+static const u32 pidr_0124_offsets[CC_NUM_IDRS] = {
56
+	CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1),
57
+	CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4)
58
+};
59
+
60
+static const u32 cidr_0123_offsets[CC_NUM_IDRS] = {
61
+	CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1),
62
+	CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3)
4263 };
4364 
4465 /* Hardware revisions defs. */
4566 
67
+/* The 703 is a OSCCA only variant of the 713 */
68
+static const struct cc_hw_data cc703_hw = {
69
+	.name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
70
+	.pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA
71
+};
72
+
73
+static const struct cc_hw_data cc713_hw = {
74
+	.name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
75
+	.pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL
76
+};
77
+
4678 static const struct cc_hw_data cc712_hw = {
47
-	.name = "712", .rev = CC_HW_REV_712, .sig =  0xDCC71200U
79
+	.name = "712", .rev = CC_HW_REV_712, .sig =  0xDCC71200U,
80
+	.std_bodies = CC_STD_ALL
4881 };
4982 
5083 static const struct cc_hw_data cc710_hw = {
51
-	.name = "710", .rev = CC_HW_REV_710, .sig =  0xDCC63200U
84
+	.name = "710", .rev = CC_HW_REV_710, .sig =  0xDCC63200U,
85
+	.std_bodies = CC_STD_ALL
5286 };
5387 
5488 static const struct cc_hw_data cc630p_hw = {
55
-	.name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U
89
+	.name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U,
90
+	.std_bodies = CC_STD_ALL
5691 };
5792 
5893 static const struct of_device_id arm_ccree_dev_of_match[] = {
94
+	{ .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw },
95
+	{ .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw },
5996 	{ .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },
6097 	{ .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },
6198 	{ .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },
6299 	{}
63100 };
64101 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);
102
+
103
+static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets)
104
+{
105
+	int i;
106
+	union {
107
+		u8 regs[CC_NUM_IDRS];
108
+		__le32 val;
109
+	} idr;
110
+
111
+	for (i = 0; i < CC_NUM_IDRS; ++i)
112
+		idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]);
113
+
114
+	return le32_to_cpu(idr.val);
115
+}
65116 
66117 void __dump_byte_array(const char *name, const u8 *buf, size_t len)
67118 {
....@@ -84,14 +135,17 @@
84135 	u32 imr;
85136 
86137 	/* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */
138
+	/* if driver suspended return, probably shared interrupt */
139
+	if (pm_runtime_suspended(dev))
140
+		return IRQ_NONE;
87141 
88142 	/* read the interrupt status */
89143 	irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
90144 	dev_dbg(dev, "Got IRR=0x%08X\n", irr);
91
-	if (irr == 0) { /* Probably shared interrupt line */
92
-		dev_err(dev, "Got interrupt with empty IRR\n");
145
+
146
+	if (irr == 0) /* Probably shared interrupt line */
93147 		return IRQ_NONE;
94
-	}
148
+
95149 	imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
96150 
97151 	/* clear interrupt - must be before processing events */
....@@ -99,12 +153,12 @@
99153 
100154 	drvdata->irq = irr;
101155 	/* Completion interrupt - most probable */
102
-	if (irr & CC_COMP_IRQ_MASK) {
103
-		/* Mask AXI completion interrupt - will be unmasked in
104
-		 * Deferred service handler
156
+	if (irr & drvdata->comp_mask) {
157
+		/* Mask all completion interrupts - will be unmasked in
158
+		 * deferred service handler
105159 		 */
106
-		cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_COMP_IRQ_MASK);
107
-		irr &= ~CC_COMP_IRQ_MASK;
160
+		cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);
161
+		irr &= ~drvdata->comp_mask;
108162 		complete_request(drvdata);
109163 	}
110164 #ifdef CONFIG_CRYPTO_FIPS
....@@ -139,16 +193,44 @@
139193 	return IRQ_HANDLED;
140194 }
141195 
196
+bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata)
197
+{
198
+	unsigned int val;
199
+	unsigned int i;
200
+
201
+	/* 712/710/63 has no reset completion indication, always return true */
202
+	if (drvdata->hw_rev <= CC_HW_REV_712)
203
+		return true;
204
+
205
+	for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
206
+		/* in cc7x3 NVM_IS_IDLE indicates that CC reset is
207
+		 *  completed and device is fully functional
208
+		 */
209
+		val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));
210
+		if (val & CC_NVM_IS_IDLE_MASK) {
211
+			/* hw indicate reset completed */
212
+			return true;
213
+		}
214
+		/* allow scheduling other process on the processor */
215
+		schedule();
216
+	}
217
+	/* reset not completed */
218
+	return false;
219
+}
220
+
142221 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
143222 {
144223 	unsigned int val, cache_params;
145224 	struct device *dev = drvdata_to_dev(drvdata);
146225 
147
-	/* Unmask all AXI interrupt sources AXI_CFG1 register */
148
-	val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
149
-	cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
150
-	dev_dbg(dev, "AXIM_CFG=0x%08X\n",
151
-		cc_ioread(drvdata, CC_REG(AXIM_CFG)));
226
+	/* Unmask all AXI interrupt sources AXI_CFG1 register   */
227
+	/* AXI interrupt config are obsoleted startign at cc7x3 */
228
+	if (drvdata->hw_rev <= CC_HW_REV_712) {
229
+		val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
230
+		cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
231
+		dev_dbg(dev, "AXIM_CFG=0x%08X\n",
232
+			cc_ioread(drvdata, CC_REG(AXIM_CFG)));
233
+	}
152234 
153235 	/* Clear all pending interrupts */
154236 	val = cc_ioread(drvdata, CC_REG(HOST_IRR));
....@@ -156,7 +238,7 @@
156238 	cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
157239 
158240 	/* Unmask relevant interrupt cause */
159
-	val = CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK;
241
+	val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK;
160242 
161243 	if (drvdata->hw_rev >= CC_HW_REV_712)
162244 		val |= CC_GPR0_IRQ_MASK;
....@@ -186,56 +268,40 @@
186268 	struct cc_drvdata *new_drvdata;
187269 	struct device *dev = &plat_dev->dev;
188270 	struct device_node *np = dev->of_node;
189
-	u32 signature_val;
271
+	u32 val, hw_rev_pidr, sig_cidr;
190272 	u64 dma_mask;
191273 	const struct cc_hw_data *hw_rev;
192
-	const struct of_device_id *dev_id;
193274 	struct clk *clk;
275
+	int irq;
194276 	int rc = 0;
195277 
196278 	new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
197279 	if (!new_drvdata)
198280 		return -ENOMEM;
199281 
200
-	dev_id = of_match_node(arm_ccree_dev_of_match, np);
201
-	if (!dev_id)
202
-		return -ENODEV;
203
-
204
-	hw_rev = (struct cc_hw_data *)dev_id->data;
282
+	hw_rev = of_device_get_match_data(dev);
205283 	new_drvdata->hw_rev_name = hw_rev->name;
206284 	new_drvdata->hw_rev = hw_rev->rev;
285
+	new_drvdata->std_bodies = hw_rev->std_bodies;
207286 
208287 	if (hw_rev->rev >= CC_HW_REV_712) {
209
-		new_drvdata->hash_len_sz = HASH_LEN_SIZE_712;
210288 		new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
211289 		new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
212290 		new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
213291 	} else {
214
-		new_drvdata->hash_len_sz = HASH_LEN_SIZE_630;
215292 		new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
216293 		new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
217294 		new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
218295 	}
219296 
297
+	new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
298
+
220299 	platform_set_drvdata(plat_dev, new_drvdata);
221300 	new_drvdata->plat_dev = plat_dev;
222301 
223
-	clk = devm_clk_get(dev, NULL);
302
+	clk = devm_clk_get_optional(dev, NULL);
224303 	if (IS_ERR(clk))
225
-		switch (PTR_ERR(clk)) {
226
-		/* Clock is optional so this might be fine */
227
-		case -ENOENT:
228
-			break;
229
-
230
-		/* Clock not available, let's try again soon */
231
-		case -EPROBE_DEFER:
232
-			return -EPROBE_DEFER;
233
-
234
-		default:
235
-			dev_err(dev, "Error getting clock: %ld\n",
236
-				PTR_ERR(clk));
237
-			return PTR_ERR(clk);
238
-		}
304
+		return dev_err_probe(dev, PTR_ERR(clk), "Error getting clock\n");
239305 	new_drvdata->clk = clk;
240306 
241307 	new_drvdata->coherent = of_dma_is_coherent(np);
....@@ -256,30 +322,19 @@
256322 		&req_mem_cc_regs->start, new_drvdata->cc_base);
257323 
258324 	/* Then IRQ */
259
-	new_drvdata->irq = platform_get_irq(plat_dev, 0);
260
-	if (new_drvdata->irq < 0) {
261
-		dev_err(dev, "Failed getting IRQ resource\n");
262
-		return new_drvdata->irq;
263
-	}
264
-
265
-	rc = devm_request_irq(dev, new_drvdata->irq, cc_isr,
266
-			      IRQF_SHARED, "ccree", new_drvdata);
267
-	if (rc) {
268
-		dev_err(dev, "Could not register to interrupt %d\n",
269
-			new_drvdata->irq);
270
-		return rc;
271
-	}
272
-	dev_dbg(dev, "Registered to IRQ: %d\n", new_drvdata->irq);
325
+	irq = platform_get_irq(plat_dev, 0);
326
+	if (irq < 0)
327
+		return irq;
273328 
274329 	init_completion(&new_drvdata->hw_queue_avail);
275330 
276
-	if (!plat_dev->dev.dma_mask)
277
-		plat_dev->dev.dma_mask = &plat_dev->dev.coherent_dma_mask;
331
+	if (!dev->dma_mask)
332
+		dev->dma_mask = &dev->coherent_dma_mask;
278333 
279334 	dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
280335 	while (dma_mask > 0x7fffffffUL) {
281
-		if (dma_supported(&plat_dev->dev, dma_mask)) {
282
-			rc = dma_set_coherent_mask(&plat_dev->dev, dma_mask);
336
+		if (dma_supported(dev, dma_mask)) {
337
+			rc = dma_set_coherent_mask(dev, dma_mask);
283338 			if (!rc)
284339 				break;
285340 		}
....@@ -291,31 +346,109 @@
291346 		return rc;
292347 	}
293348 
294
-	rc = cc_clk_on(new_drvdata);
349
+	rc = clk_prepare_enable(new_drvdata->clk);
295350 	if (rc) {
296351 		dev_err(dev, "Failed to enable clock");
297352 		return rc;
298353 	}
299354 
300
-	/* Verify correct mapping */
301
-	signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
302
-	if (signature_val != hw_rev->sig) {
303
-		dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
304
-			signature_val, hw_rev->sig);
305
-		rc = -EINVAL;
306
-		goto post_clk_err;
355
+	new_drvdata->sec_disabled = cc_sec_disable;
356
+
357
+	pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT);
358
+	pm_runtime_use_autosuspend(dev);
359
+	pm_runtime_set_active(dev);
360
+	pm_runtime_enable(dev);
361
+	rc = pm_runtime_get_sync(dev);
362
+	if (rc < 0) {
363
+		dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc);
364
+		goto post_pm_err;
307365 	}
308
-	dev_dbg(dev, "CC SIGNATURE=0x%08X\n", signature_val);
366
+
367
+	/* Wait for Cryptocell reset completion */
368
+	if (!cc_wait_for_reset_completion(new_drvdata)) {
369
+		dev_err(dev, "Cryptocell reset not completed");
370
+	}
371
+
372
+	if (hw_rev->rev <= CC_HW_REV_712) {
373
+		/* Verify correct mapping */
374
+		val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
375
+		if (val != hw_rev->sig) {
376
+			dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
377
+				val, hw_rev->sig);
378
+			rc = -EINVAL;
379
+			goto post_pm_err;
380
+		}
381
+		sig_cidr = val;
382
+		hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);
383
+	} else {
384
+		/* Verify correct mapping */
385
+		val = cc_read_idr(new_drvdata, pidr_0124_offsets);
386
+		if (val != hw_rev->pidr_0124) {
387
+			dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n",
388
+				val,  hw_rev->pidr_0124);
389
+			rc = -EINVAL;
390
+			goto post_pm_err;
391
+		}
392
+		hw_rev_pidr = val;
393
+
394
+		val = cc_read_idr(new_drvdata, cidr_0123_offsets);
395
+		if (val != hw_rev->cidr_0123) {
396
+			dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n",
397
+			val,  hw_rev->cidr_0123);
398
+			rc = -EINVAL;
399
+			goto post_pm_err;
400
+		}
401
+		sig_cidr = val;
402
+
403
+		/* Check HW engine configuration */
404
+		val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
405
+		switch (val) {
406
+		case CC_PINS_FULL:
407
+			/* This is fine */
408
+			break;
409
+		case CC_PINS_SLIM:
410
+			if (new_drvdata->std_bodies & CC_STD_NIST) {
411
+				dev_warn(dev, "703 mode forced due to HW configuration.\n");
412
+				new_drvdata->std_bodies = CC_STD_OSCCA;
413
+			}
414
+			break;
415
+		default:
416
+			dev_err(dev, "Unsupported engines configuration.\n");
417
+			rc = -EINVAL;
418
+			goto post_pm_err;
419
+		}
420
+
421
+		/* Check security disable state */
422
+		val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
423
+		val &= CC_SECURITY_DISABLED_MASK;
424
+		new_drvdata->sec_disabled |= !!val;
425
+
426
+		if (!new_drvdata->sec_disabled) {
427
+			new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
428
+			if (new_drvdata->std_bodies & CC_STD_NIST)
429
+				new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
430
+		}
431
+	}
432
+
433
+	if (new_drvdata->sec_disabled)
434
+		dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n");
309435 
310436 	/* Display HW versions */
311
-	dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
312
-		 hw_rev->name, cc_ioread(new_drvdata, new_drvdata->ver_offset),
313
-		 DRV_MODULE_VERSION);
437
+	dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n",
438
+		 hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION);
439
+	/* register the driver isr function */
440
+	rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree",
441
+			      new_drvdata);
442
+	if (rc) {
443
+		dev_err(dev, "Could not register to interrupt %d\n", irq);
444
+		goto post_pm_err;
445
+	}
446
+	dev_dbg(dev, "Registered to IRQ: %d\n", irq);
314447 
315448 	rc = init_cc_regs(new_drvdata, true);
316449 	if (rc) {
317450 		dev_err(dev, "init_cc_regs failed\n");
318
-		goto post_clk_err;
451
+		goto post_pm_err;
319452 	}
320453 
321454 	rc = cc_debugfs_init(new_drvdata);
....@@ -326,7 +459,7 @@
326459 
327460 	rc = cc_fips_init(new_drvdata);
328461 	if (rc) {
329
-		dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc);
462
+		dev_err(dev, "cc_fips_init failed 0x%x\n", rc);
330463 		goto post_debugfs_err;
331464 	}
332465 	rc = cc_sram_mgr_init(new_drvdata);
....@@ -338,40 +471,27 @@
338471 	new_drvdata->mlli_sram_addr =
339472 		cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
340473 	if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
341
-		dev_err(dev, "Failed to alloc MLLI Sram buffer\n");
342474 		rc = -ENOMEM;
343
-		goto post_sram_mgr_err;
475
+		goto post_fips_init_err;
344476 	}
345477 
346478 	rc = cc_req_mgr_init(new_drvdata);
347479 	if (rc) {
348480 		dev_err(dev, "cc_req_mgr_init failed\n");
349
-		goto post_sram_mgr_err;
481
+		goto post_fips_init_err;
350482 	}
351483 
352484 	rc = cc_buffer_mgr_init(new_drvdata);
353485 	if (rc) {
354
-		dev_err(dev, "buffer_mgr_init failed\n");
486
+		dev_err(dev, "cc_buffer_mgr_init failed\n");
355487 		goto post_req_mgr_err;
356
-	}
357
-
358
-	rc = cc_pm_init(new_drvdata);
359
-	if (rc) {
360
-		dev_err(dev, "ssi_power_mgr_init failed\n");
361
-		goto post_buf_mgr_err;
362
-	}
363
-
364
-	rc = cc_ivgen_init(new_drvdata);
365
-	if (rc) {
366
-		dev_err(dev, "cc_ivgen_init failed\n");
367
-		goto post_buf_mgr_err;
368488 	}
369489 
370490 	/* Allocate crypto algs */
371491 	rc = cc_cipher_alloc(new_drvdata);
372492 	if (rc) {
373493 		dev_err(dev, "cc_cipher_alloc failed\n");
374
-		goto post_ivgen_err;
494
+		goto post_buf_mgr_err;
375495 	}
376496 
377497 	/* hash must be allocated before aead since hash exports APIs */
....@@ -387,37 +507,34 @@
387507 		goto post_hash_err;
388508 	}
389509 
390
-	/* All set, we can allow autosuspend */
391
-	cc_pm_go(new_drvdata);
392
-
393510 	/* If we got here and FIPS mode is enabled
394511 	 * it means all FIPS test passed, so let TEE
395512 	 * know we're good.
396513 	 */
397514 	cc_set_ree_fips_status(new_drvdata, true);
398515 
516
+	pm_runtime_put(dev);
399517 	return 0;
400518 
401519 post_hash_err:
402520 	cc_hash_free(new_drvdata);
403521 post_cipher_err:
404522 	cc_cipher_free(new_drvdata);
405
-post_ivgen_err:
406
-	cc_ivgen_fini(new_drvdata);
407523 post_buf_mgr_err:
408524 	 cc_buffer_mgr_fini(new_drvdata);
409525 post_req_mgr_err:
410526 	cc_req_mgr_fini(new_drvdata);
411
-post_sram_mgr_err:
412
-	cc_sram_mgr_fini(new_drvdata);
413527 post_fips_init_err:
414528 	cc_fips_fini(new_drvdata);
415529 post_debugfs_err:
416530 	cc_debugfs_fini(new_drvdata);
417531 post_regs_err:
418532 	fini_cc_regs(new_drvdata);
419
-post_clk_err:
420
-	cc_clk_off(new_drvdata);
533
+post_pm_err:
534
+	pm_runtime_put_noidle(dev);
535
+	pm_runtime_disable(dev);
536
+	pm_runtime_set_suspended(dev);
537
+	clk_disable_unprepare(new_drvdata->clk);
421538 	return rc;
422539 }
423540 
....@@ -429,48 +546,30 @@
429546 
430547 static void cleanup_cc_resources(struct platform_device *plat_dev)
431548 {
549
+	struct device *dev = &plat_dev->dev;
432550 	struct cc_drvdata *drvdata =
433551 		(struct cc_drvdata *)platform_get_drvdata(plat_dev);
434552 
435553 	cc_aead_free(drvdata);
436554 	cc_hash_free(drvdata);
437555 	cc_cipher_free(drvdata);
438
-	cc_ivgen_fini(drvdata);
439
-	cc_pm_fini(drvdata);
440556 	cc_buffer_mgr_fini(drvdata);
441557 	cc_req_mgr_fini(drvdata);
442
-	cc_sram_mgr_fini(drvdata);
443558 	cc_fips_fini(drvdata);
444559 	cc_debugfs_fini(drvdata);
445560 	fini_cc_regs(drvdata);
446
-	cc_clk_off(drvdata);
561
+	pm_runtime_put_noidle(dev);
562
+	pm_runtime_disable(dev);
563
+	pm_runtime_set_suspended(dev);
564
+	clk_disable_unprepare(drvdata->clk);
447565 }
448566 
449
-int cc_clk_on(struct cc_drvdata *drvdata)
567
+unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata)
450568 {
451
-	struct clk *clk = drvdata->clk;
452
-	int rc;
453
-
454
-	if (IS_ERR(clk))
455
-		/* Not all devices have a clock associated with CCREE  */
456
-		return 0;
457
-
458
-	rc = clk_prepare_enable(clk);
459
-	if (rc)
460
-		return rc;
461
-
462
-	return 0;
463
-}
464
-
465
-void cc_clk_off(struct cc_drvdata *drvdata)
466
-{
467
-	struct clk *clk = drvdata->clk;
468
-
469
-	if (IS_ERR(clk))
470
-		/* Not all devices have a clock associated with CCREE */
471
-		return;
472
-
473
-	clk_disable_unprepare(clk);
569
+	if (drvdata->hw_rev >= CC_HW_REV_712)
570
+		return HASH_LEN_SIZE_712;
571
+	else
572
+		return HASH_LEN_SIZE_630;
474573 }
475574 
476575 static int ccree_probe(struct platform_device *plat_dev)
....@@ -515,15 +614,17 @@
515614 
516615 static int __init ccree_init(void)
517616 {
518
-	int ret;
617
+	int rc;
519618 
520
-	cc_hash_global_init();
619
+	cc_debugfs_global_init();
521620 
522
-	ret = cc_debugfs_global_init();
523
-	if (ret)
524
-		return ret;
621
+	rc = platform_driver_register(&ccree_driver);
622
+	if (rc) {
623
+		cc_debugfs_global_fini();
624
+		return rc;
625
+	}
525626 
526
-	return platform_driver_register(&ccree_driver);
627
+	return 0;
527628 }
528629 module_init(ccree_init);
529630