.. | .. |
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20 | 20 | Low level power management driver for CCI400 cache coherent |
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21 | 21 | interconnect for ARM platforms. |
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22 | 22 | |
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| 23 | +config ARM_INTEGRATOR_LM |
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| 24 | + bool "ARM Integrator Logic Module bus" |
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| 25 | + depends on HAS_IOMEM |
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| 26 | + depends on ARCH_INTEGRATOR || COMPILE_TEST |
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| 27 | + default ARCH_INTEGRATOR |
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| 28 | + help |
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| 29 | + Say y here to enable support for the ARM Logic Module bus |
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| 30 | + found on the ARM Integrator AP (Application Platform) |
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| 31 | + |
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23 | 32 | config BRCMSTB_GISB_ARB |
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24 | 33 | bool "Broadcom STB GISB bus arbiter" |
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25 | 34 | depends on ARM || ARM64 || MIPS |
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.. | .. |
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29 | 38 | arbiter. This driver provides timeout and target abort error handling |
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30 | 39 | and internal bus master decoding. |
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31 | 40 | |
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| 41 | +config BT1_APB |
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| 42 | + bool "Baikal-T1 APB-bus driver" |
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| 43 | + depends on MIPS_BAIKAL_T1 || COMPILE_TEST |
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| 44 | + select REGMAP_MMIO |
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| 45 | + help |
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| 46 | + Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs. |
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| 47 | + IO requests are routed to this bus by means of the DW AMBA 3 AXI |
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| 48 | + Interconnect. In case of any APB protocol collisions, slave device |
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| 49 | + not responding on timeout an IRQ is raised with an erroneous address |
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| 50 | + reported to the APB terminator (APB Errors Handler Block). This |
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| 51 | + driver provides the interrupt handler to detect the erroneous |
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| 52 | + address, prints an error message about the address fault, updates an |
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| 53 | + errors counter. The counter and the APB-bus operations timeout can be |
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| 54 | + accessed via corresponding sysfs nodes. |
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| 55 | + |
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| 56 | +config BT1_AXI |
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| 57 | + bool "Baikal-T1 AXI-bus driver" |
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| 58 | + depends on MIPS_BAIKAL_T1 || COMPILE_TEST |
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| 59 | + select MFD_SYSCON |
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| 60 | + help |
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| 61 | + AXI3-bus is the main communication bus connecting all high-speed |
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| 62 | + peripheral IP-cores with RAM controller and with MIPS P5600 cores on |
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| 63 | + Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI |
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| 64 | + Interconnect (so called AXI Main Interconnect) routing IO requests |
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| 65 | + from one SoC block to another. This driver provides a way to detect |
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| 66 | + any bus protocol errors and device not responding situations by |
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| 67 | + means of an embedded on top of the interconnect errors handler |
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| 68 | + block (EHB). AXI Interconnect QoS arbitration tuning is currently |
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| 69 | + unsupported. |
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| 70 | + |
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| 71 | +config MOXTET |
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| 72 | + tristate "CZ.NIC Turris Mox module configuration bus" |
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| 73 | + depends on SPI_MASTER && OF |
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| 74 | + help |
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| 75 | + Say yes here to add support for the module configuration bus found |
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| 76 | + on CZ.NIC's Turris Mox. This is needed for the ability to discover |
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| 77 | + the order in which the modules are connected and to get/set some of |
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| 78 | + their settings. For example the GPIOs on Mox SFP module are |
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| 79 | + configured through this bus. |
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| 80 | + |
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32 | 81 | config HISILICON_LPC |
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33 | 82 | bool "Support for ISA I/O space on HiSilicon Hip06/7" |
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34 | | - depends on ARM64 && (ARCH_HISI || COMPILE_TEST) |
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35 | | - select INDIRECT_PIO |
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| 83 | + depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC && !C6X) |
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| 84 | + depends on HAS_IOMEM |
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| 85 | + select INDIRECT_PIO if ARM64 |
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36 | 86 | help |
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37 | 87 | Driver to enable I/O access to devices attached to the Low Pin |
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38 | 88 | Count bus on the HiSilicon Hip06/7 SoC. |
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.. | .. |
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47 | 97 | |
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48 | 98 | config MIPS_CDMM |
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49 | 99 | bool "MIPS Common Device Memory Map (CDMM) Driver" |
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50 | | - depends on CPU_MIPSR2 |
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| 100 | + depends on CPU_MIPSR2 || CPU_MIPSR5 |
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51 | 101 | help |
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52 | 102 | Driver needed for the MIPS Common Device Memory Map bus in MIPS |
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53 | 103 | cores. This bus is for per-CPU tightly coupled devices such as the |
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.. | .. |
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128 | 178 | tristate "Tegra ACONNECT Bus Driver" |
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129 | 179 | depends on ARCH_TEGRA_210_SOC |
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130 | 180 | depends on OF && PM |
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131 | | - select PM_CLK |
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132 | 181 | help |
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133 | 182 | Driver for the Tegra ACONNECT bus which is used to interface with |
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134 | 183 | the devices inside the Audio Processing Engine (APE) for Tegra210. |
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.. | .. |
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139 | 188 | help |
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140 | 189 | Driver for the Tegra Generic Memory Interface bus which can be used |
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141 | 190 | to attach devices such as NOR, UART, FPGA and more. |
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| 191 | + |
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| 192 | +config TI_PWMSS |
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| 193 | + bool |
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| 194 | + default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM || TI_EQEP) |
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| 195 | + help |
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| 196 | + PWM Subsystem driver support for AM33xx SOC. |
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| 197 | + |
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| 198 | + PWM submodules require PWM config space access from submodule |
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| 199 | + drivers and require common parent driver support. |
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142 | 200 | |
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143 | 201 | config TI_SYSC |
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144 | 202 | bool "TI sysc interconnect target module driver" |
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.. | .. |
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164 | 222 | needed to use on-board devices connected to UniPhier SoCs. |
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165 | 223 | |
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166 | 224 | config VEXPRESS_CONFIG |
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167 | | - bool "Versatile Express configuration bus" |
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| 225 | + tristate "Versatile Express configuration bus" |
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168 | 226 | default y if ARCH_VEXPRESS |
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169 | 227 | depends on ARM || ARM64 |
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170 | 228 | depends on OF |
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.. | .. |
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182 | 240 | peripherals. |
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183 | 241 | |
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184 | 242 | source "drivers/bus/fsl-mc/Kconfig" |
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| 243 | +source "drivers/bus/mhi/Kconfig" |
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185 | 244 | |
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186 | 245 | endmenu |
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